Multi-Core, Main-Memory Joins: Sort vs. Hash Revisited · Overview 1 Background Sort vs. Hash Motivation 2 Merge - Sort Join The basic idea Sort Phase Merge Phase Multi-Way Merge

Multi-Core, Main-Memory Joins: Sort vs. Hash Revisited

Presenter: Haonan Wang

Slides Credit: CMU 15-721 Spring 2018

haonanw@mit.edu

March 19, 2019

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Overview

1 BackgroundSort vs. HashMotivation

2 Merge - Sort JoinThe basic ideaSort PhaseMerge PhaseMulti-Way Merge

3 Experiment

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Section 1

Background

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Subsection 1

Sort vs. Hash

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Sort vs. Hash

There are two main approaches for the PARALLEL JOIN ALGORITHMS:→ Hash Join→ Sort-Merge Join

History of Hash VS. Sort

1970s Sorting

1980s Hashing

1990s Equivalent

2000s Hashing

2010s Hashing (Partitioned vs. Non-Partitioned)

2020s ???

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What Is Merge-Sort Join

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SIMD?

What is SIMD?A class of CPU instructions that allow the processor to perform the sameoperation on multiple data points simultaneously.

Both current AMD and Intel CPUs have ISA and microarchitecturesupport SIMD operations.→ MMX, 3DNow!, SSE, SSE2, SSE3, SSE4, AVX

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SIMD Makes Sorting Better Than Hashing?

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Section 2

Merge - Sort Join

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The basic idea for the designing

Partition Phase(Optional)→ Partition R and assign them to workers / cores.

Sort Phase→ Sort the tuples of R and S based on the join key.

Merge Phase→ Scan the sorted relations and compare tuples.→ The outer relation R only needs to be scanned once.

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Subsection 2

Sort Phase

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Sorting Networks(1)

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Sorting Networks(2)

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Sorting Networks(3)

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Sorting Networks(4)

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Sorting Networks(5)

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Sorting Networks(6)

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Sorting Networks Summary(1)

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Sorting Networks Summary(2)

Always has fixed wiring paths for lists with the same number ofelements.

Efficient to execute on modern CPUs because of limited datadependencies and no branches.

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Sorting Network Speed Up With SIMD(1)

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Sorting Network Speed Up With SIMD(2)

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Sorting Network Speed Up With SIMD(3)

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Subsection 3

Merge Phase

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Bitonic Merge Networks

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Merging Larger Lists using Bitonic Merge

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Merging-Sort Tree

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Merging-Sort Hierarchy(Summary)

in-register sorting, with runs that fit into (SIMD) CPU registers;

in-cache sorting, where runs can still be held in a CPU-local cache;

out-of-cache sorting, once runs exceed cache sizes.

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Subsection 4

Multi-Way Merge

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Impact Of Numa

In practice, at least some merging passes will inevitably cross NUMAboundaries.

multisocket systems show an increasing asymmetry, where the NUMAinterconnect bandwidth stays further and further behind theaggregate memory bandwidth that the individual memory controllerscould provide.

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m-way

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Section 3

Experiment

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Settings

Intel Sandy Bridge with a 256-bit AVX instruction set.

Four-socket configuration, with each CPU socket containing 8physical cores and 16 thread contexts by the help of thehyper-threading.

Cache sizes are 32 KiB for L1, 256 KiB for L2, and 20 MiB L3 (thelatter shared by the 16 threads within the socket).The cache line sizeof the system is 64 bytes. TLB1 contains 64/32 entries when using 4KiB/2 MiB pages (respectively) and 512 TLB2 entries (page size 4KiB). Total memory available is 512 GiB (DDR3 at 1600 MHz).

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Scalability

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Result(1)

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Result(2)

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The End

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