M ask D esign T raining M ask D esign T raining Page 1 Quality Layout.
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Quality Layout
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What is Quality Layout ?Quality Layout Consist Of These Elements : Meet Circuit Performance Requirements
Minimize parasitic RC Analog
Efficient Area Usage Anticipate ECO changes Prepare future process/optical shrink Meet or beat allocated area
Manufacture-able Layout (DFM) Debug-able Layout (DFD)
Probe & FIB Fulfill Reliability Guidelines
Electro Migration & Self Heating ESD
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OUTLINES Engineering Layout Checklist
Poly Guidelines Contact Guidelines Diffussion Guidelines Metal and Vias Guidelines Summary
Electromigration and Self Heating Layout Review Checklist
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Poly GuidelinesPolysiliconsIn general, poly has much higher resistance then metal and
therefore much higher delay.
Using poly as an interconnect level can be advantageously used to create very compacts layout. But, poly should never be used as interconnect when the capacitance is high.
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Gate driving Gate driving
Gates should be driven from the middle so that long poly lines are minimized. This means they should be driven between the p’s and n’s not through them.
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Gate spacing Gate Spacing
Stacked series gates should be minimally spaced at Yu apart. Parallel gates need a spacing of Xu between gates (i.e. series gates can be closer).
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No field poly in high speed path
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•Gate poly is worse, gate oxide is 10X then field oxide RC.
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Leg device is needed
There is a Design rule limitation on the poly length. The transistor
performance is very sensitive to the gate width.
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No field poly to connect diffusion
Function of the IC may be jeopardized. EM (electromigration) rule is likely to be violated.
Significant performance impact.
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No bend gates Even the process today allow bent gates and will not give any
significant impact to the performance, the analysis tool make no provision for them.
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Contacts Guidelines There are two kinds of contacts: partially covered and fully
covered. Partially covered contacts cannot carry as much current as fully covered contacts.
Definitions
Fully/Partially Covered: A fully covered contacts has at least 0.16u coverage on all sides. A partially covered contact has 0.0 metal coverage past the edge of the contact. This mean that during process, if the mask moves, the partially covered contact may not be covered all the way with metal.
Fully/Partially Strapped: Strapping is a term indicating how many contacts connect the device to metal1. Fully strapped means that as many contact as will fit have been placed on the device. Partially strapped means that some of the contacts is missing.
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Strapping Guidelines At least 40% of length with minimum-spaced fully-covered contacts. At least 80% of length with minimum-spaced partially-covered contacts. Do not break S/D strapping Based on simulations of conductivity degradation Static Timing Analysis tool assumes all junctions are fully strapped in its transistor
models.
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Diffusion stretching Only stretch VCC/VSS (not signal) diffusion to make room for
signal routes. Based on observation of the impact on diffusion loading on the
output node We don’t care about diffusion loading on the VCC/VSS
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Supply and Interleaving guideline
Connect signal diffusions inside and supplies outside Signals are sensitive to diffusion loading, supplies are not Typical diffusion loading
area = 0.48fF/u2periphery = 0.05fF/u
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Metal and Vias Guidelines Ohm per square resistance
P86X process
Contact 15.0
Via1 7.0
Via2 7.0
Via3 7.0
Via4 7.0
Via5 6.0
Poly 16.10
Metal1 0.085
Metal2 0.062
Metal3 0.062
Metal4 0.062
Metal5 0.062
Metal6 0.020
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MetalsMetal1 will be unusable for longer routes as refer to the chart of
ohm/square.Metal1 is more resistive compared to others metal layer, therefore
move to Metal2 as soon as possible when do a signal routing to minimize the RC delay.
ViasVias are allowed to be stacked.Via stacking rules:1. Via1 may stack on well, diff and poly and directly on top of
contact.2. Via2 may stack on contact and directly Via1 without constraint.3. Via3 may stack on contact, Via1 and directly Via2 without
constraint.4. Via4 may stack on contact, Via1, Via2 and directly Via3 without
constraint.
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BKM on metal routingAvoid Small Jog Segments (< 1x MDR width)
- Small jog segments are defined as being less than 1X minimum design rule line width.
- No small jog segments on diffusion, poly, metal1 – metal5.< 1X MDR Width
Insufficient room for “Serifs and “Cutouts”
Pinching Risk
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Small Jog Segment Recommendations
1X MDR Width 2X MDR Width
0.5X MDR Width
2X MDR Width
Increase Jog Separation Distance
Increase Jog Segment Size
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Minimize the Total Number of Jog Segments
Fewer number of vertices to correct. Less pattern distortion risk.
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BetterUndesirable
Undesirable Better
Landing Pad Recommendations
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Layer changes / Jumpers Layer Changes / Jumpers
Minimize the number of metal layer changes while routing a signal.
– Metal layer changes are expensive in area. – Every extra via increases resistance quite a bit and impacts
signal timing. No Poly jumpers
– Poly is very resistive
What’s Wrong With This Layout ?
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Summary Shareable Power/Ground
Ensure shareable power/ground at diffusion edges if possible. Always connect to bigger supply (ie: metal2 with 2 vias width).
Well Taps & Substrate Taps Have well taps connect to VDD or signal specified in schematic. Have substrate taps connect to GND.
Shareable Nodes Share nodes both internally and externally as much as possible.
– Sharing nodes can reduce cell or block size/area.– Sharing nodes can reduce contacts, vias and metal layers
used. Help to improve circuit performance. Not applicable for special circuit (ie: analog – matching layout).
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Metal Directions Use consistent metal directions for M1, M2, and M3. Make
sure that tracks are not blocked by using inconsistent directions. M1 and M3 vertical, M2 and M4 horizontal.
Routing Jogs / turning points Avoid making unnecessary jogs in routing (i.e. if a wire can go
straight it should). This will help performance and area. Aligned the placement of connectors to signal to avoid creating
unnecessary curves / corners.
Signal Width Try to maintain uniform/even width for a signal. Check with DE or layout lead on critical / HV signal width
requirement.
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EM and SH
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EM definitionsEM is a problem that occurs when current only moves in one
direction and pulls the atoms of the metal along with it. This movement will eventually leave gaps in the meatl causing open circuits failures. It can also cause increase resistance especially in contact and Via’s causing a speed failure over time.
SH definitionsSH or self heat is a problem that occurs when current is alternating
or not just flowing in the same direction all the time. Whereas in EM the metal only moves in one direction, in SH the atoms move in one direction and then back again making a net movement of zero. The problem occurs when too much currents flows heating up the metal and causing it to deteriorate and increase the resistance.
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Layout checklistItems to check Status
1 Half design rules to cell boundary
2 Diffussion
a. Minimize source/drain width
b. Power source should be at both ends of the cell.
c. Shared diffussion
d. Diffussion height align
3 Poly
a. Poly gate driving in the middle
b. No poly jumpers
c. No poly bends
d. P & N devices orientation are the same
4 Contact
a. Full strapping contact and centralized.
b. At least two contact for each input/connection.
5 Metal
a. No notches
b. No metal jogs
c. Use uniform width of metal routing.
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6 Labeling
a. Label all the nodes as the schematic has and case-sensitive.
b. All IO pins must have pin name.
7 Power/Ground source
a. Power/ground must directly connected from the main vcc/vss bus, insteads of connect from the wellTab or substrate tap.
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Q & A
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