Lecture 7 Modified Nodal Analysis and SPICE Simulation ...pages.mtu.edu/~zhuofeng/EE5780Fall2013_files/Lecture_07_Spice... · Lecture 7 Modified Nodal Analysis and SPICE Simulation
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Z. Feng MTU EE5780 Advanced VLSI CAD7.1
EE5780 Advanced VLSI CAD
Lecture 7 Modified Nodal Analysis and SPICE Simulation
Zhuo Feng
Z. Feng MTU EE5780 Advanced VLSI CAD7.2
Introduction to SPICE■ Simulation Program with Integrated Circuit Emphasis
► Developed in 1970’s at Berkeley► Many commercial versions are available► HSPICE is a robust industry standard
▼Has many enhancements that we will use
■ Written in FORTRAN for punch-card machines► Circuits elements are called cards► Complete description is called a SPICE deck
Z. Feng MTU EE5780 Advanced VLSI CAD7.3
Writing Spice Decks■ Writing a SPICE deck is like writing a good program
► Plan: sketch schematic on paper or in editor▼Modify existing decks whenever possible
► Code: strive for clarity▼Start with name, email, date, purpose▼Generously comment
► Test:▼Predict what results should be▼Compare with actual▼Garbage In, Garbage Out!
Z. Feng MTU EE5780 Advanced VLSI CAD7.4
Example: RC Circuit* rc.sp* David_Harris@hmc.edu 2/2/03* Find the response of RC circuit to rising input
*------------------------------------------------* Parameters and models*------------------------------------------------.option post
*------------------------------------------------* Simulation netlist*------------------------------------------------Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8R1 in out 2kC1 out gnd 100f
*------------------------------------------------* Stimulus*------------------------------------------------.tran 20ps 800ps.plot v(in) v(out).end
R1 = 2K
C1 =100fF
Vin+
Vout-
Z. Feng MTU EE5780 Advanced VLSI CAD7.5
Result (Textual)legend:
a: v(in)b: v(out)
time v(in)(ab ) 0. 500.0000m 1.0000 1.5000 2.0000
+ + + + + 0. 0. -2------+------+------+------+------+------+------+------+-
20.0000p 0. 2 + + + + + + + + 40.0000p 0. 2 + + + + + + + + 60.0000p 0. 2 + + + + + + + + 80.0000p 0. 2 + + + + + + + + 100.0000p 0. 2 + + + + + + + + 120.0000p 720.000m +b + + a+ + + + + + 140.0000p 1.440 + b + + + + + a + + + 160.0000p 1.800 + +b + + + + + +a + 180.0000p 1.800 + + b + + + + + +a + 200.0000p 1.800 -+------+------+b-----+------+------+------+------+a-----+-220.0000p 1.800 + + + b + + + + +a + 240.0000p 1.800 + + + +b + + + +a + 260.0000p 1.800 + + + + b + + + +a + 280.0000p 1.800 + + + + b+ + + +a + 300.0000p 1.800 + + + + +b + + +a + 320.0000p 1.800 + + + + + b + + +a + 340.0000p 1.800 + + + + + b + + +a + 360.0000p 1.800 + + + + + b + +a + 380.0000p 1.800 + + + + + +b + +a + 400.0000p 1.800 -+------+------+------+------+------+--b---+------+a-----+-420.0000p 1.800 + + + + + + b + +a + 440.0000p 1.800 + + + + + + b + +a + 460.0000p 1.800 + + + + + + b+ +a + 480.0000p 1.800 + + + + + + b +a + 500.0000p 1.800 + + + + + + +b +a + 520.0000p 1.800 + + + + + + +b +a + 540.0000p 1.800 + + + + + + + b +a + 560.0000p 1.800 + + + + + + + b +a + 580.0000p 1.800 + + + + + + + b +a + 600.0000p 1.800 -+------+------+------+------+------+------+---b--+a-----+-620.0000p 1.800 + + + + + + + b +a + 640.0000p 1.800 + + + + + + + b +a + 660.0000p 1.800 + + + + + + + b +a + 680.0000p 1.800 + + + + + + + b +a + 700.0000p 1.800 + + + + + + + b+a + 720.0000p 1.800 + + + + + + + b+a + 740.0000p 1.800 + + + + + + + b+a + 760.0000p 1.800 + + + + + + + b+a + 780.0000p 1.800 + + + + + + + ba + 800.0000p 1.800 -+------+------+------+------+------+------+------ba-----+-
+ + + + +
Z. Feng MTU EE5780 Advanced VLSI CAD7.6
Result (Graphical)
t(s)0.0 100p 200p 300p 400p 500p 600p 700p 800p 900p
0.0
0.5
1.0
1.5
2.0 v(in)
v(out)
Z. Feng MTU EE5780 Advanced VLSI CAD7.7
Sources■ DC Source
Vdd vdd gnd 2.5
■ Piecewise Linear SourceVin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8
■ Pulsed SourceVck clk gnd PULSE 0 1.8 0ps 100ps 100ps 300ps 800ps
PULSE v1 v2 td tr tf pw per
v1
v2
td tr tfpw
per
Z. Feng MTU EE5780 Advanced VLSI CAD7.8
SPICE Elements
Letter ElementR ResistorC CapacitorL InductorK Mutual InductorV Independent voltage sourceI Independent current sourceM MOSFETD DiodeQ Bipolar transistorW Lossy transmission lineX SubcircuitE Voltage-controlled voltage sourceG Voltage-controlled current sourceH Current-controlled voltage sourceF Current-controlled current source
Z. Feng MTU EE5780 Advanced VLSI CAD7.9
Units
Letter Unit Magnitudea atto 10-18
f fempto 10-15
p pico 10-12
n nano 10-9
u micro 10-6
m mili 10-3
k kilo 103
x mega 106
g giga 109
Ex: 100 femptofarad capacitor = 100fF, 100f, 100e-15
Z. Feng MTU EE5780 Advanced VLSI CAD7.10
DC Analysis* mosiv.sp
*------------------------------------------------* Parameters and models*------------------------------------------------.include '../models/tsmc180/models.sp'.temp 70.option post
*------------------------------------------------* Simulation netlist*------------------------------------------------*nmosVgs g gnd 0Vds d gnd 0M1 d g gnd gnd NMOS W=0.36u L=0.18u
*------------------------------------------------* Stimulus*------------------------------------------------.dc Vds 0 1.8 0.05 SWEEP Vgs 0 1.8 0.3.end
Vgs Vds
Ids
4/2
Z. Feng MTU EE5780 Advanced VLSI CAD7.11
I-V Characteristics
Vds
0.0 0.3 0.6 0.9 1.2 1.5 1.8
Ids(A)
0
50
100
150
200
250
Vgs = 1.8
Vgs = 1.5
Vgs = 1.2
Vgs = 0.9
Vgs = 0.6
■ NMOS I-V►Vgs dependence►Saturation
Z. Feng MTU EE5780 Advanced VLSI CAD7.12
MOSFET ElementsM element for MOSFET
Mname drain gate source body type+ W=<width> L=<length>+ AS=<area source> AD = <area drain> + PS=<perimeter source> PD=<perimeter drain>
Z. Feng MTU EE5780 Advanced VLSI CAD7.13
Transient Analysis* inv.sp
* Parameters and models*------------------------------------------------.param SUPPLY=1.8.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post
* Simulation netlist*------------------------------------------------Vdd vdd gnd 'SUPPLY'Vin a gnd PULSE 0 'SUPPLY' 50ps 0ps 0ps 100ps 200psM1 y a gnd gnd NMOS W=4 L=2 + AS=20 PS=18 AD=20 PD=18M2 y a vdd vdd PMOS W=8 L=2+ AS=40 PS=26 AD=40 PD=26
* Stimulus*------------------------------------------------.tran 1ps 200ps.end
a y
4/2
8/2
Z. Feng MTU EE5780 Advanced VLSI CAD7.14
Transient Results
(V)
0.0
1.0
t(s)0.0 50p 100p 150p 200p
v(a)
v(y)
tpdr = 15pstpdf = 12ps
tf = 10ps
tr = 16ps
0.36
1.44
1.8
■ Unloaded inverter► Overshoot► Very fast edges
Z. Feng MTU EE5780 Advanced VLSI CAD7.15
Subcircuits■ Declare common elements as subcircuits
■ Ex: Fanout-of-4 Inverter Delay► Reuse inv► Shaping► Loading
.subckt inv a y N=4 P=8M1 y a gnd gnd NMOS W='N' L=2 + AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10'M2 y a vdd vdd PMOS W='P' L=2+ AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10'.ends
a b c d eX1 X2 X3 X41
2
4
8
16
32
64
128 fX5256
512
Shape input
DeviceUnderTest Load
Load onLoad
Z. Feng MTU EE5780 Advanced VLSI CAD7.16
FO4 Inverter Delay* fo4.sp
* Parameters and models*----------------------------------------------------------------------.param SUPPLY=1.8.param H=4.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post
* Subcircuits*----------------------------------------------------------------------.global vdd gnd.include '../lib/inv.sp'
* Simulation netlist*----------------------------------------------------------------------Vdd vdd gnd 'SUPPLY'Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000psX1 a b inv * shape input waveformX2 b c inv M='H' * reshape input waveform
Z. Feng MTU EE5780 Advanced VLSI CAD7.17
FO4 Inverter Delay Cont.X3 c d inv M='H**2' * device under testX4 d e inv M='H**3' * loadx5 e f inv M='H**4' * load on load
* Stimulus*----------------------------------------------------------------------.tran 1ps 1000ps.measure tpdr * rising prop delay+ TRIG v(c) VAL='SUPPLY/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf * falling prop delay+ TRIG v(c) VAL='SUPPLY/2' RISE=1+ TARG v(d) VAL='SUPPLY/2' FALL=1 .measure tpd param='(tpdr+tpdf)/2' * average prop delay.measure trise * rise time+ TRIG v(d) VAL='0.2*SUPPLY' RISE=1+ TARG v(d) VAL='0.8*SUPPLY' RISE=1.measure tfall * fall time+ TRIG v(d) VAL='0.8*SUPPLY' FALL=1+ TARG v(d) VAL='0.2*SUPPLY' FALL=1.end
Z. Feng MTU EE5780 Advanced VLSI CAD7.18
FO4 Results
(V)
0.0
0.5
1.0
1.5
2.0
t(s)0.0 200p 400p 600p 800p 1n
a
b
c
d
e
ftpdf = 66ps tpdr = 83ps
Z. Feng MTU EE5780 Advanced VLSI CAD7.19
Power Measurement■ HSPICE can measure power
► Instantaneous P(t)►Or average P over some interval
.print P(vdd)
.measure pwr AVG P(vdd) FROM=0ns TO=10ns
■ Power in single gate►Connect to separate VDD supply►Be careful about input power
Z. Feng MTU EE5780 Advanced VLSI CAD7.20
■ How is SPICE simulator created?►N equations in terms of N unknown Node voltages►More generally using modified nodal analysis
G(v)i 1v2v
3v
4vC
R
v
Z. Feng MTU EE5780 Advanced VLSI CAD7.21
Time Domain Equations at node 1:
If we do this for all N nodes:
N dimensional vector of unknownnode voltages
vector of independent sources
nonlinear operator
0)()()(12
4131 vvGR
vvdt
vvdC
0))(),(),(( tutxtxF Xx
)0(
)(tx
)(tu
F
Z. Feng MTU EE5780 Advanced VLSI CAD7.22
■ Closed form solution is not possible for arbitrary order of differential equations
■ We must approximate the solution of:
■ This is facilitated in SPICE via numerical solutions
0))(),(),(( tutxtxF Xx
)0(
Z. Feng MTU EE5780 Advanced VLSI CAD7.23
■ Basic circuit analyses►(Nonlinear) DC analysis
▼Finds the DC operating point of the circuit▼Solves a set of nonlinear algebraic eqns
►AC analysis▼Performs frequency-domain small-signal analysis▼Require a preceding DC analysis▼Solves a set of complex linear eqns
►(Nonlinear) transient analysis▼Computes the time-domain circuit transient response▼Solves a set of nonlinear different eqns▼Converts to a set nonlinear algebraic of eqns using
numerical integration
Z. Feng MTU EE5780 Advanced VLSI CAD7.24
■ SPICE offers practical techniques to solve circuit problems in time & freq. domains
► Interface to device models▼Transistors, diodes, nonlinear caps etc
► Sparse linear solver
► Nonlinear solver – Newton-Raphson method
► Numerical integration
► Convergence & time-step control
Z. Feng MTU EE5780 Advanced VLSI CAD7.25
■ Circuit equations are usually formulated using
►Nodal analysis ▼N equations in N nodal voltages
►Modified analysis▼Circuit unknowns are nodal voltages & some branch
currents▼Branch current variables are added to handle
– Voltages sources– Inductors– Current controlled voltage source etc
■ Formulations can be done in both time and frequency
Z. Feng MTU EE5780 Advanced VLSI CAD7.26
How do we set up a matrix problem given a list oflinear(ized) circuit elements?
Similar to reading a netlist for a linear circuit:
* Element Name From To Value
3
2
1
1
RRRI
2110
0201
1005101mA
Z. Feng MTU EE5780 Advanced VLSI CAD7.27
The nodal analysis matrix equations areeasily constructed via KCL at each node:
1I 1R
2R
3RmA1
5
10010
1 2
0
JvY
Z. Feng MTU EE5780 Advanced VLSI CAD7.28
■ Naïve approach► a) Write down the KCL eqn for each node► b) Combine all of them to a get N eqns in N node voltages
■ Intuitive for hand analysis
■ Computer programs use a more convenient “element” centric approach► Element stamps
Z. Feng MTU EE5780 Advanced VLSI CAD7.29
Instead of converting the netlist into a graph and writing KCL eqns, stamp in elements one at a time:
Stamps: add to existing matrix entries
RR
RR11
11 Fromrow
Torow
Fromcol.
Tocol.
j
i
i j
i
jRY
Z. Feng MTU EE5780 Advanced VLSI CAD7.30
RHS of equations are stamped in a similar way:
II
i
jI
From row
Torow
ij
J
Z. Feng MTU EE5780 Advanced VLSI CAD7.31
Stamping our simple example one element at a time:
10002521
1001110
3
2
1
1
RRR
mAI
01
2
1
322
221 IVV
GGGGGG
Z. Feng MTU EE5780 Advanced VLSI CAD7.32
We know that nonlinear elements are firstconverted to linear components, then stamped
EQI EQG
Z. Feng MTU EE5780 Advanced VLSI CAD7.33
For 3 & 4 terminal elements we know that the linearized models have linear controlled sources
Gdsv
D DG
S S
gsv
gsmvg dsr
We can stamp in MOSFETs in terms of a completestamp, or in terms of simpler element stamps
Z. Feng MTU EE5780 Advanced VLSI CAD7.34
Voltage controlled current source
kv 0I
k
kmvgi
p
q
Voltmeter
mm
mm
gggg
k
p
qrow
row
colcol
Large value that does not fall on diagonal of Y!
Z. Feng MTU EE5780 Advanced VLSI CAD7.35
All other types of controlled sources includevoltage sources
Voltage sources are inherently incompatiblewith nodal analysis
Grounded voltages sources are easily accommodated
1
0
v2
21
2
1
vv
Z. Feng MTU EE5780 Advanced VLSI CAD7.36
But a voltage source in between nodes is more difficult
Node voltages and are not independentk
k
Z. Feng MTU EE5780 Advanced VLSI CAD7.37
We no longer have N independent node voltagevariables
So we can potentially eliminate one equation and one variable (section 2.3 of reference [1])
But the more popular solution is modified nodalanalysis (MNA)
i
Vk
Create one extra variable and one extra equation
Z. Feng MTU EE5780 Advanced VLSI CAD7.38
Extra variable: voltage source current
Allows us to write KCL at nodes and
Extra equation
Advantage: now have an easy way of printingcurrent results - - ammeter
Vvvk
k
Z. Feng MTU EE5780 Advanced VLSI CAD7.39
Voltage source stamp:
Vi0111
1
row
row
row
col colcol
k
k
1N
1N
Z. Feng MTU EE5780 Advanced VLSI CAD7.40
Current-controlled current source (e.g. BJT) has to stamp in an ammeter and a controlled current source
12 ii 1i
Z. Feng MTU EE5780 Advanced VLSI CAD7.41
In general, we would not blindly build the matrixfrom an input netlist and then attempt to solve it
Various illegal ckts are possible:
Cutsets of current sources
Z. Feng MTU EE5780 Advanced VLSI CAD7.42
Loops of voltage sources
Dangling nodes
Z. Feng MTU EE5780 Advanced VLSI CAD7.43
■ Once we efficiently formulate MNA equations, an efficient solution to is even more important
■ For large ckts the matrix is really sparse► Number of entries in Y is a function of number of elements
connected to the corresponding node
■ Inverting a sparse matrix is never a good idea since the inverse is not sparse!
■ Instead direct solution methods employ Gaussian Elimination or LU factorization
JvY
Z. Feng MTU EE5780 Advanced VLSI CAD7.44
ckt file
dc nonlinear soln. open C’s ; short L’s
insert TR models for L’s and C’s
“dc” nonlinear soln. for equivalent CKT
finaltt
0t
ttt
?
Done
■ TR analysis flow (Chap. 4 of ref. 2)
Z. Feng MTU EE5780 Advanced VLSI CAD7.45
■ One-step integration approximation
dtdvCi C
v i
tt
t
diC
tvttv )(1)()(
)()(2
)()(
)(
ttititttit
titdi
tt
i
Forward Euler (FE)
Backward Euler (BE)
Trapezoidal (TR)
Z. Feng MTU EE5780 Advanced VLSI CAD7.46
)(ti
1t 2t t12 ttt
)()( 12
1titdttit
t Forward Euler
■ FE is explicit, and no nonlinear iterations are required► Extremely difficult to use in practice
Z. Feng MTU EE5780 Advanced VLSI CAD7.47
)(ti
1t 2t t
)()( 22
1titdttit
t Backward Euler
■ BE is implicit► Much more robust than FE► Can also make unstable responses appear stable
Z. Feng MTU EE5780 Advanced VLSI CAD7.48
)(ti
1t 2t t
)()(2
)( 212
1tititdttit
t
Trapezoidal
■ TR is implicit too► Works similarly to BE► Incurs less error
Z. Feng MTU EE5780 Advanced VLSI CAD7.49
■ FE Capacitor Companion Model
dtdvCi C
v i
)()()( tiCttvttv
)( tti
)()( titditt
t
Z. Feng MTU EE5780 Advanced VLSI CAD7.50
■ BE Capacitor Companion Model► Thevenin
)()( ttitditt
t
dtdvCi C
v i
CtReq
)( tti )(tvVeq
Z. Feng MTU EE5780 Advanced VLSI CAD7.51
■ BE Capacitor Companion Model► Norton
tCGeq
)(tvt
CIeq
)( ttv
)( tti
Z. Feng MTU EE5780 Advanced VLSI CAD7.52
■ TR Capacitor Companion Model► Thevenin
)()(2
)( ttititditt
t
dtdvCi C
v i
CtReq 2
)( tti )(
2)( ti
CttvVeq
Z. Feng MTU EE5780 Advanced VLSI CAD7.53
■ TR Capacitor Companion Model► Norton
tCGeq
2)()(2 titv
tCIeq
)( ttv
)( tti
Z. Feng MTU EE5780 Advanced VLSI CAD7.54
■ TR Inductor Companion Model► Norton
)()(2
)( ttvtvtdvtt
t
vi
L dt
Ldiv dvL
titti )(1)()(
LtGeq 2
)()(
2titv
LtIeq
)( ttv
)( tti
Z. Feng MTU EE5780 Advanced VLSI CAD7.55
■ TR Inductor Companion Model► Thevenin
tLReq
2
)( tti )(2)( ti
tLtvVeq
Z. Feng MTU EE5780 Advanced VLSI CAD7.56
■ Nonlinear DC analysis (Chapter 10.6 – 10.8 of Ref. 2)
►Store device equations and their partial derivatives w.r.t. branch voltages for efficient N-R procedure:
▼Insert linearized models into MNA formulation (first order Taylor series at operating point)
▼Solve the linear ckt to complete one N-R iteration
▼Use the solution as operating pt. for next linearization step
Z. Feng MTU EE5780 Advanced VLSI CAD7.57
Diode equations and companion model for N-R
21 vvvd 1
2
)( 1 TVdv
eIi sd
Td
Vv
T
s
d
d eVI
vi
)( 11 kd
kd
kd
dkd
kd vv
viii
)( kd
kd
dkd v
vii
kd
d
vi
StoredModelEqns.
Z. Feng MTU EE5780 Advanced VLSI CAD7.58
Diodes are modeled by Norton equivalentcompanion models
Some sort of voltage limiting scheme isrequired to make N-R iterations robust
Solve to obtainand so on…
1kv
)( kd
kd
dKdeq v
viiI
kd
deq v
iG
Z. Feng MTU EE5780 Advanced VLSI CAD7.59
■ Recap: linear transient analysis►Replace each of C’s and L’s by a companion
model – numerical integration▼Forward Euler, Backward Euler, Trapezoidal ▼Norton or Thevenin models
►Solve the equivalent linear circuit at the current time step
►Update all the companion models and move to the next time step
Z. Feng MTU EE5780 Advanced VLSI CAD7.60
■ Example: BE capacitor companion models►Thevenin
)()( ttitditt
t
dtdvCi C
v i
CtReq
)( tti )(tvVeq
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►Norton
tCGeq
)(tvt
CIeq
)( ttv
)( tti
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■ We combine the above two in nonlinear transient analysis
tnt 1nt
)(tv
Numerical integration
N-R iterations
Z. Feng MTU EE5780 Advanced VLSI CAD7.63
■ Start from some initial condition at time t0
■ Move to the next time step by replacing all the C’s & L’s by a companion model
► Solve the equivalent nonlinear DC problem at the new time point▼Use the solution at the previous time step as the initial guess
for N-R
▼ Iterate till convergence
■ Repeat till reaching the ending time
■ Nonlinear dynamic elements need to be handled more carefully
► Charge conservation – more on this later
Z. Feng MTU EE5780 Advanced VLSI CAD7.64
What about nonlinear elements with more than2 terminals?
Nonlinear equations:
Once again, model by first 2 terms of Taylor series
1i 2i
2v1v3i
),( 2111 vvgi ),( 2122 vvgi
213 iii Port Equations
Z. Feng MTU EE5780 Advanced VLSI CAD7.65
22
11
1
121111
11 ),( v
vgv
vgvvgiii
kk
kkkkk
22
21
1
221222
12 ),( v
vgv
vgvvgiii
kk
kkkkk
22
2
2
11
1
2
1
1
212211331
3 ),(),(
vvg
vgv
vg
vg
vvgvvgiii
Kk
kkkkkkk
Z. Feng MTU EE5780 Advanced VLSI CAD7.66
3-Terminal MOSFET Stamp:2v1v
Consider the current contribution at each nodeNote that we must translate port voltages to node voltages
a b
c
22
11
1
121111
11 ),( v
vgv
vgvvgiii
kk
kkkkk
11ki
cb
ca
vvv
vvv
2
1
ckk
bk
ak
kkkkk vvg
vgv
vgv
vgvvgiii
2
1
1
1
2
1
1
121111
11 ),(
Z. Feng MTU EE5780 Advanced VLSI CAD7.67
3-Terminal MOSFET Stamp:2v1v
Most solvers are setup to solve for instead ofv 1kv
2
2
1
2
2
1
1
1
2
2
2
1
1
2
1
1
2
2
1
2
2
2
1
2
2
1
1
1
2
1
1
1
vg
vg
vg
vg
vg
vg
vg
vg
vg
vg
vg
vg
vg
vg
vg
vg
kkkkkkkk
kkkk
kkkk
a
b
c
a b cv
),(
),(
),(
),(
212
211
212
211
kk
kk
kk
kk
vvg
vvg
vvg
vvg
a b
c
c
b
a
v
v
v
Z. Feng MTU EE5780 Advanced VLSI CAD7.68
MOSFETs (3 terminal)
Triode Region
dsds
dsTHgsds vvvvvi
1
2)(
2
THgsds vvv
0 THgs vv
LWC ox
di
si
gidsv
gsv
Z. Feng MTU EE5780 Advanced VLSI CAD7.69
Saturation Region
Cutoff Region
dsTHgsds vvvi 1)(
22
THgsds vvv
THgs vv 0dsi
Z. Feng MTU EE5780 Advanced VLSI CAD7.70
dc port equations:
),( dsgsdsd vvii
0gi
),( dsgsdsds vviii
)(
)(
),(
1
1
1
kds
kds
kds
ds
kgs
kgs
kgs
ds
kds
kgsds
kd
kd
kd
vvvi
vvvi
vviiii
Z. Feng MTU EE5780 Advanced VLSI CAD7.71
dsi
kdsi
gsv
kdsv dsv
THgsds Vvv
m
kgs
ds gvi
dskds
ds Gvi
kds
kds
kgs
km
kds
kds vGvgii 1
Z. Feng MTU EE5780 Advanced VLSI CAD7.72
kds
kds
kgsm
kds
kds vGvgii 1
Equivalent ckt model for N-R
kgs
kgs
kgs vvv 1
kds
kds
kds vvv 1
kgsv
G
S
1kdsi
kgs
km vg k
dsi kdsG k
dsv
Z. Feng MTU EE5780 Advanced VLSI CAD7.73
Stamping in terms for all of these 2-terminalelements is equivalent to applying MOSFET stamp
Note the large off-diagonal terms that are createdby sgm '
Could also build models to solve forand directly1k
dsv1k
gsv
Z. Feng MTU EE5780 Advanced VLSI CAD7.74
Simple Example
INV
1R
2R
3R
1MDDV
1 2
0
DDV3R
12kv
kdsG
kEQI
11kk
mvg11kv2RINV
1R
kds
kds
kgs
km
kds
kEQ vGvgiI
kgs
dskm v
ig
kds
dskds v
iG
Z. Feng MTU EE5780 Advanced VLSI CAD7.75
Now formulate the nodal equations forthis linearized equivalent ckt
DDV3R
12kv
kdsG
kEQI
11kk
mvg11kv2RINV
1R
Z. Feng MTU EE5780 Advanced VLSI CAD7.76
■ and values change at each N-R iteration
■ Damping methods control the N-R convergence► More of a problem for BJTS
■ In general, we would include the 4-th terminal of the MOSFET (body effect)
dsm Gg , EQI
Z. Feng MTU EE5780 Advanced VLSI CAD7.77
■ We use dc nonlinear algorithms find solution at t=0 AND for all timepoints
■ Energy storage elements are properly considered by numerical integration
■ How about nonlinear capacitors?
Ct
2
Z. Feng MTU EE5780 Advanced VLSI CAD7.78
Conventional NL device models► ids = f(vds, vgs, vsb) -- 30+ parameters► Accurate evaluation can be very expensive
NR requires full evaluation of models► Derivatives required for Jacobian
▼Expensive to evaluate -- can consume 50-80% of computation time
SC-based approach ► No derivatives to re-organize – approximate Jacobian► Will work with table models, measured data► Reduced model evaluation time, but is based on:
▼Slower convergence (depending on the Japprox)▼Matrix update required for varying timesteps▼Selection of representative linear model in Japprox
Z. Feng MTU EE5780 Advanced VLSI CAD7.79
Newton-Raphson
Good convergence properties
Reliable when implemented with a step-limiting mechanism (damped)
Requires explicit differentiation
n-D case: Jacobian Matrix stamping (update) and re-factorization x0
x2
x1
Z. Feng MTU EE5780 Advanced VLSI CAD7.80
Successive Chord J(x) represents a fixed gradient
(Jacobian)
No explicit differentiation
Reliable when implemented with a step-limiting mechanism (damped)
n-D case: Single Jacobian factorization improvement by optional updates
x0
x2
x1
Z. Feng MTU EE5780 Advanced VLSI CAD7.81
NR has varying R, I SC has fixed R
Linearized network changes for each NR step, i.e. J(xn)
Single linearized network for SC steps, Japprox
Newton-Raphson Successive Chord
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