Lecture 22: PLLs and DLLs
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Lecture 22: PLLs and DLLs
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 2
Outline Clock System Architecture Phase-Locked Loops Delay-Locked Loops
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 3
Clock Generation
Low frequency:– Buffer input clock and drive to all registers
High frequency– Buffer delay introduces large skew relative to
input clocks• Makes it difficult to sample input data
– Distributing a very fast clock on a PCB is hard
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 4
Zero-Delay Buffer
If the periodic clock is delayed by Tc, it is indistinguishable from the original clock
Build feedback system to guarantee this delay
Phase-Locked Loop (PLL)
Delay-Locked Loop (DLL)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 5
Frequency Multiplication
PLLs can multiply the clock frequency– Distribute a lower frequency on the board– Multiply it up on-chip– Possible to adjust the frequency on the fly
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 6
Phase and Frequency
Analyze PLLs and DLLs in term of phase (t) rather than voltage v(t)
Input and output clocks may
deviate from locked phase– Small signal analysis
1 mod2clk
0 mod2
t
t
0
2t
t f t dt
in in
out out
t t t
t N t t
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 7
Linear System Model Treat PLL/DLL as a linear system
– Compute deviation from locked position– Assume small deviations from locked– Treat system as linear for these small changes
Analysis is not valid far from lock– e.g. during acquisition at startup
Continuous time assumption– PLL/DLL is really a discrete time system
• Updates once per cycle– If the bandwidth << 1/10 clock freq, treat as continuous
Use Laplace transforms and standard analysis of linear continuous-time feedback control systems
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 8
Phase-Locked Loop (PLL)
System
Linear Model
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 9
Voltage-Controlled Oscillator VCO
ctrl ctrl0 ctrl
ctrl
2
outvco
out vco
ctrl
V t V V t
fK
V
s K
V s s
-+
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 10
Alternative Delay Elements
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 11
Frequency Divider
Divide clock by N– Use mod-N counter
outfb
outfb
ff
N
N
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 12
Phase Detector
Difference of input and
feedback clock phase
Often built from phase-frequency detector (PFD)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 13
Phase Detector Convert up and down pulses into current proportional to phase
error using a charge pump
cp
err 2pd
pd
I s IK
s
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 14
Loop Filter
Convert charge pump
current into Vctrl
Use proportional-integral control (PI) to generate a control signal dependent on the error and its integral– Drives error to 0
ctrl
pd
1V sR
I s sC (negligible)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 15
PLL Loop Dynamics
Closed loop transfer function of PLL
This is a second order system
n indicates loop bandwidth
indicates damping; choose 0.7 – 1 to avoid ringing
vco
out
vcoin
21
21 11
pd
pd
KK R
s sC sH s
Ks K RN sC s
vco
2
2 2
2
2
2
cpn
n n
n n n
I Ks NCH s N
s sRC
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 16
Delay Locked Loop
Delays input clock rather than creating a new clock with an oscillator
Cannot perform frequency multiplication More stable and easier to design
– 1st order rather than 2nd
State variable is now time (T)
– Locks when loop delay is exactly Tc
– Deviations of T from locked value
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 17
Delay-Locked Loop (DLL)
System
Linear Model
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 18
Delay Line
Delay input clock
Typically use voltage-controlled delay line
out
ctrlvcdl
T sK
V s
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 19
Phase Detector
Detect phase error
Typically use PFD and charge pump, as in PLL
err
pd cp
c
I s I
T s T
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 20
Loop Filter
Convert error current
into control voltage
Integral control is sufficient Typically use a capacitor as the loop filter
ctrl 1I
pd
V s K
I s s sC
CMOS VLSI DesignCMOS VLSI Design 4th Ed.22: PLLs and DLLs 21
DLL Loop Dynamics
Closed loop transfer function of DLL
This is a first order system
indicates time constant (inverse of bandwidth)
– Choose at least 10Tc for continuous time approx.
out
in
1
1
T sH s
T s s
1 c
pd I vcdl cp vcdl
CT
K K K I K
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