Lecture 04 Review of MOSFET - ece.uic.eduzyang/Teaching/20182019SpringECE541/Downloads/... · MOS Transistors - Types and Symbols D S G D S G G S D D S G NMOSEnhancement NMOS PMOS

ECE 541/ME 541Microelectronic Fabrication Techniques

Lecture 04 Review of MOSFET

Zheng Yang(ERF 3017, email: yangzhen@uic.edu)

What is a Transistor?

VGS VT

RonS D

A Switch!

An MOS Transistor

The MOS Transistor

Polysilicon Aluminum

MOS Transistors -Types and Symbols

NMOS Enhancement NMOS

Depletion

Enhancement

NMOS withBulk Contact

The Gate Capacitance

Cross section

Gate oxide

Polysilicon gate

Top view

Gate-bulkoverlap

Source

Threshold Voltage: Concept

p-substrate

DepletionRegion

n-channel

The Threshold Voltage

The Body Effect

-2.5 -2 -1.5 -1 -0.5 00.4

Current-Voltage Relations

QuadraticRelationship

0 0.5 1 1.5 2 2.50

VDS (V)

)VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

Transistor in Linear

p-substrate

V(x) +–

MOS transistor and its bias conditions

Transistor in Saturation

VDS > VGS - VT

VGS - VT+-

Pinch-off

Current-Voltage Relations Long-Channel Device

Velocity Saturation

(V/µm)c = 1.5

sat = 105

Constant mobility (slope = µ)

Constant velocity

Perspective

IDLong-channel device

Short-channel device

VDSVDSAT VGS - VT

VGS = VDD

ID versus VGS

0 0.5 1 1.5 2 2.50

6x 10-4

VGS(V)

0 0.5 1 1.5 2 2.50

2.5x 10-4

VGS(V)

quadratic

linear

Long Channel Short Channel

ID versus VDS

VDS(V)0 0.5 1 1.5 2 2.50

2.5x 10

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

6x 10-4

VDS(V)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

Long Channel Short Channel

A PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

VDS (V)

Assume all variablesnegative!

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V

Outline(1) MOS fundamentals

(3) MOS C-V characteristics

(2) MOS electrostatic: Quantitative analysis

(4) MOSFET

(5) MOSFET small-signal equivalent circuit

(6) Non-ideal MOS

(1) MOS fundamentals

Metal-oxide-semiconductor FET is the most important device in modern microelectronics.

Hightlights– Ideal MOS structure electrostatics– MOS band diagram under applied bias– Gate voltage relationship– capacitance-voltage relationship under low frequency

and under high frequency.

MOSFET

electrons

N-channelMOSFET(NMOS)uses p-type substrate

MOSFET operation

Pinch-off

VG3 > VG2 > VG1

When a positive voltage VG is applied to the gate relative to the substrate, mobile negative charges (electrons) gets attracted to Si-oxide interface. These induced electrons form the channel.

For a given value of VG, the current ID increases with VD, and finally saturates.

Ideal MOS capacitor

Oxide has zero charge, and no current can pass through it.No charge centers are present in the oxide or at the oxide-semiconductor interface.Semiconductor is uniformly dopedM = S

= + (EC – EF)FB

Let us consider a simple MOS capacitor and call it “ideal”

Equilibrium energy band diagram for an ideal MOS structure

Effect of an applied bias

Let us ground the semiconductor and start applying different voltages, VG, to the gate

VG can be positive, negative or zero with respect to the semiconductor

EF, metal – EF, semiconductor = – q VG

(Since electron energy = q V, when V < 0, electron energy increases)

Since oxide has no charge, d Eoxide / dx = / = 0; i.e. the E-field inside the oxide is constant.

Consider p-type Si, apply VG < 0

m' Accumulation

of holes

ioxide

oxide 1const.0 EE

The oxide energy band has constant slope as shown. No current flows in Si EF in Si is constant.

Negative voltage attracts holes to the Si-oxide interface.This is called accumulation condition.Ei – EF shouldincreases near thesurface of Si.

Accumulation condition, VG < 0, p-type Si

––––

Sheet of holes

smallcharge density

M O p-type SiVG < 0

Sheet ofelectrons

Accumulation of holes nearsilicon surface, and electronsnear the metal surface.

Similar to a parallel platecapacitor structure.

Consider p-type Si, apply VG > 0 (Depletion condition)

ECEiEFsEV

DepletionE

positive

0negative

+- - - -

- - - -

Finite depletion layerwidth

Consider p-Si, apply VG >> 0 (Inversion condition)

- - - - - - -

- - - - - - --

Immobile acceptors

Mobile electrons

Inversion condition

If we continue to increase the positive gate voltage, the bands at the semiconductor bends more strongly. At sufficiently high voltage, Ei can be below EF indicating large concentration of electrons in the conduction band.

We say the material near the surface is “inverted”. The “inverted”layer is not gotten by doping, but by applying E-field. Where did we get the electrons from?

When Ei(surface) – Ei(bulk) = 2 [EF – Ei(bulk)], the condition isstart of “inversion”, and the voltage VG applied to gate is called VT(threshold voltage). For VG > VT, the Si surface is inverted.

Energy band diagrams and charge density diagrams describing MOS capacitor in n-type Si

Energy band diagrams and charge density diagrams describing MOS capacitor in p-type Si

Example 1

Construct line plots that visually identify the voltage ranges corresponding to accumulation, depletion and inversion in ideal n-type Si (i.e. p-channel) and p-type Si (i.e. n-channel) MOS devices.

Answer:

(2) MOS electrostatic: Quantitative analysis

Highlights

Derive analytical expressions for the charge density, electric field and the electrostatic potential.

Expression for the depletion layer width

Describe delta depletion solution

Derive gate voltage relationship

– Gate voltage required to obtain inversion

Electrostatic potential, (x)

Define a new term, (x) taken to be the potential inside the semiconductor at a given point x. [The symbol instead of V used in MOS work to avoid confusion with externally applied voltage, V]

)]((bulk)[1)( ii xEEq

(surface)](bulk)[1iiS EE

](bulk)[1FiF EE

Potential at any point x

Surface potential

F > 0 means p-type F < 0 means n-type

| F | related to doping concentration

Electrostatic parameters

S = 2F at the depletion-inversiontransition point

S is positive if the band bends downward

Example 2Consider the following F and S parameters. Indicate whether the semiconductor is p-type or n-type, specify the biasing condition, and draw the energy band diagram at the biasing condition.(i) F = 12 kT/q; S = 12 kT/q

F = +12 kT/q means that Ei – EF in the semiconductor is 12 kT (a positive value); So, p-type. NA = ni exp [(Ei – EF ) / kT]

S=12 kT/q means Ei (bulk) – Ei(surface) = 12 kT; i.e. the band bends downward near the surface.

EiEFEV

Example 2 (continued)

(ii) F = 9 kT/q; S = 18 kT/q

here F = 9 kT/q means [Ei(bulk) – EF] = 9 kT; i.e., Ei is below EF. Thus the semiconductor is n-type.

S= 18 kT/q means that Ei (bulk) – Ei(surface) = –18 kT; So bandbends upwards near the surface. The surface is “inverted” sincethe surface has the same number of holes as the bulk has electrons.

EiEFEV

Delta-depletion solution

Consider p-type siliconAccumulation condition

The accumulation chargesare mobile holes, and appearclose to the surface and fall-offrapidly as x increases.Assume that the free carrier concentration at the oxide-semiconductor interface is a -function.

VG < 0p-Si

Accumulation of holes

Charge on metal = QM

Charge on semiconductor = (charge on metal) |QAccumulation| = |QM|

Homo-pn-junction Diode

npbi lnln

xxxxqNV

xxxxqNxV

xxxxqN

oxxxxqNx

Emax = q NA xp/ = q ND xn/

W = xn + xp

Review

Schottky diode

WxWxqN

for00forD

0fordd

FBFCBbi )(1 EEq

Si )(2/

Review

Delta depletion solution (cont.)Consider p-type Si, depletion conditionApply VG such that s < 2 FCharges in Si are immobile ions - results in depletionlayer similar to that in pnjunction or Schottky diode.

VG > 0

Depletion of holes

wQM|q NA A W| = |QM|() (+)

If surface potential is s (with respect to the bulk), then the depletion layer width W will be

Si and2E

At the start of inversion, s = 2 F and 21

SiT 22

xdE/dx = qNA/si

Depletion layer width, W and E-field

For a p+n junction, or a MS (n-Si) junction, the depletion layer width is given by:

Where Vbi is related to the amount of band bending. Vbi in Volts is numericallyequal to the amount of band bending in eV.

VqNWqN

For MOS, the same equation applies, except that Vbi is replaced by s.

2or2Si)(in//

||qN||qN

n-type p-type

Review

Delta depletion solution (cont.)

Depletion of holes

Inversion electrons:-function-like

Consider p-Si, strong inversion.

Once inversion charges appear, they remain close to the surface since they are mobile. Any additionalvoltage to the gate results in extra QM in gate and get compensated by extra inversion electrons in semiconductor.

So, depletion layer does not have to increase to balance the charge on the metal. Electrons appear as -function near the surface. Maximum depletion layer width W = WT

Gate voltage relationship

Applied gate voltage will be equal to the voltage across the oxide plus the voltage across the semiconductor. Consider p-type Si.

VG > 0

Semiox

VG= ox +Semi

Semi = (x = 0) (bulk)= S

ox = xox Eox

Since the interface does not have any charges up to inversion, wecan say that ox Eox = Si ESi

Eox = (Si / ox) ESi

Gate voltage relationship (cont.)

20for2

qNqNWqN

oxoxsG

20for2

Gate-voltage relationship (Alternative method)

VG= ox+ Semi

ox= QM/Cox = Qs/Cox where Cox is oxide capacitance and Qs is the depletion layer charge in semiconductor

Qs = q A NAWCox = ox A / xox

Consider p-type silicon

qNxWqNxV

WqNxx/AWNAq

(same as before)

(3) MOS C-V characteristics

The measured MOS capacitance (called gate capacitance) varies with the applied gate voltage

– A very powerful diagnostic tool for identifying any deviations from the ideal in both oxide and semiconductor

– Routinely monitored during MOS device fabricationMeasurement of C-V characteristics

– Apply any dc bias, and superimpose a small ac signal– Generally measured at 1 MHz (high frequency) or at variable

frequencies between 1KHz to 1 MHz– The dc bias VG is slowly varied to get quasi-continuous C-V

characteristics

C-V characteristics of MOS-capacitor on p- and n-type Si

n-type

The C-V data depends on the measurement frequency as well.The dotted line represents the low-frequency C-V data.

p-type

Measured C-V characteristics on an n-type Si

ND = 9.0 1014 cm3

xox = 0.119 m

MOS-capacitor under accumulation

VG < 0

Accumulation of holes

Consider p-type Si under accumulation.

VG < 0.Looks similar to parallelplate capacitor.

CG = Cox

where Cox = (ox A) / xox

Thus, for all accumulation conditions, the gate capacitance is equalthe oxide capacitance.

MOS-capacitor under depletion

Depletion condition:VG > 0

CG is Cox in series with Cs where Cs can be defined as “semiconductor capacitance”

Cox=ox A / xoxCs = Si A / W

CG = Cox Cs/(Cox + CS)

where s is surface potential

In this case, the gate capacitance decreases as the gate voltage is increased. Why?

VG > 0

p-type Si

Depletion of holes

MOS-capacitor under inversion

VG >>0

Depletion of holes

Inversion electrons- function

VG = VT and VG > VT

Inversion condition s = 2 F

SiT 22

At high frequency, inversionelectrons are not able to respondto ac voltage. So, to balance the charge on the metal, the depletion layer width will vary with the ac.

Cox=ox A/xox

Cs = Si A/WT

CG ( ) = Cox Cs / (Cox + CS)

So, CG will be constant for VG VT

MOS-capacitor under inversion

At low frequency, the inversion electrons will be able to respond to the ac voltage (Why?). So, the gate capacitance will be equal to the “oxide capacitance” (similar to a parallel plate capacitance).

CG ( 0) = Cox= ox A / xox

p-type Si

Low frequency

High frequency

Cox Cs / (Cox+Cs)For VG > VT, the highfrequency capacitance remains constant. Why?

Example 3Consider n-type silicon doped with NA=1016 cm3. The oxide thickness is 100 nm. Plot the CG vs. VG characteristics when VG is varied slowlyfrom 5 V to +5 V. Assume MOS has area of 1 cm2.

Find Cox.

Find Cs (min) when W = WT (Note that Cs decreases as the depletionlayer width increases. It is minimum when the depletion layer widthis maximum, i.e. when W = WT).

F105.3cm1cm10100

F/cm109.89.3 827

μm31.0cm101.3V357.02cm10C106.1

F/cm1085.89.112 52/1

F104.3cm1cm101.3

F/cm1085.89.11(min) 825

CG(min) = (3.51083.4108) /(3.5108 +3.4108) F = 1.7 108 F

Example 3 (continued)

SioxsTG 2when2

= 2.15 V

Plot the C-V characteristics 34.7 nF

p-type

2.17 V

34.7nFlow-f

high-f

Explain why CG does notvary for VG > VT

Question: How will you calculate CG when VG = 1V?Answer: Calculate s when VG = 1V using the eqn. above. From s find W, then calculate Cs. Then, calculate CG = (Cox Cs) / (Cox + Cs)

MOS-capacitor characteristics: Deep depletion

The previous discussions pertain to the condition when the gate voltage is ramped slowly, from accumulation condition to depletion and then to inversion condition. When the ramp rate is high, the inversion layer does not form and does not have time to equilibrate. This is called “deep depletion” condition. In this case, W will continue to increase beyond WT and CG will continue to decrease as shown when the dc bias is varied from accumulation bias to deep depletion bias.

To calculate W under deep depletion condition, invert the VG versus s relationship. Solve for s

1/2 and hence s. Then, calculate Wusing W versus s relationship.

Some observations

• VT = gate voltage required for start of inversion= (+) for p-type Si= () for n-type Si

SioxFT 222

(+) - for p-type Si() - for n-type Si

• Higher the doping, higher the |VT| value• Cmax = Cox and Cmin = Cox Cs / (Cox + Cs)• Lower the doping, lower Cs and hence lower Cmin

Doping dependence of MOS-capacitor high frequency C-V characteristics, with xox = 0.1m

MOS-capacitor under deep depletion

SioxsG

Cs = Si A / W

Cox=ox A / xox

CG = Cox Cs / (Cox + Cs)

n-type Si

Example 4

Consider example 1. Plot C-V characteristics if VG is variedfrom 5 V to + 5 V rapidly.

CG (5 V) = Cox=34.7 nF, as before.CG (VG = VT) = 17 nF, as before.

where691

10101061231010005

Solving for s , we get s = 2.38 V

CG (VG > VT) will continue to reduce (unlike the quasi-steady state condition of example 1). When VG = 5 V,

W = 0.545 m; Cs = 18.3 nF; CG= 12 nF 5V2.15 V

34.7 nF

Not under steady state

(4) MOSFET

MOSFET based ICs have become dominant technology in the semiconductor industry.

Qualitative theory of operation

Quantitative ID vs. VDS characteristics

Small-signal equivalent circuits.

N-channel MOSFETSubstrate: p-type Si

Qualitative discussion: NMOS

N+ N+ 0 < VG < VT ; VDS small or large no channel, no current

VG > VT ; VDS 0ID increases with VDS

VG > VT; VDS small, > 0ID increases with VDS , but rate of increase decreases.

VG > VT; VDS pinch-offID reaches a saturation value, ID,satThe VDS value is called VDS,sat

VG > VT; VDS > VDS,satID does not increase further, saturation region.

ID-VDS characteristics for NMOS derived fromqualitative discussions

Saturationregion

Linearregion

ID-VDS characteristics expected from a long channel (L << L) MOSFET (n-channel), for various values of VG

Threshold voltage for NMOS and PMOS

When VG = VT, s = 2 F; using equation 16.28, we get expression for VT.

SioxFT 222

Ideal n-channel(p-silicon) deviceboth terms positive

SioxFT 222

/||qNxV

Ideal p-channel(n-silicon) deviceboth terms negative

Si/ ox = (Si o) / (ox o) = 11.9 / 3.9 3

Quantitative ID-VDS relationships

QN = inversion layer charge0

G (VG)

S D (VDS)

Let be the potential along the channel

For VG < VT, Inversion layer charge is zero.For VG > VT, Qn(y) = QG = Cox (VG VT)

In general, Jn= q n n E when the diffusion current is neglected.Here, current ID is the same everywhere, but Jn (current density)can vary from position to position.

Device structure, dimension, and coordinate orientations assumed in the quantitative analysis

Quantitative ID-VDS relationships (Shockley model)

ynqnqJJ y d

Esince

To find current, we have to multiply the above with area, but Jny,n, etc. are functions of x and z. Hence,

areaunitcharge)()(dd

dddddd

/yQyQy

ZxJZzxJI yy

Integrating the above equation, and noting that ID is constant, we get

d)(n0nDDS yQ

V Since we know expression for Qn(y) in terms of , we can integrate this to get ID

Quantitative ID-VDS Relationships (cont.)

DSTGoxn

DVVVVC

LZI satDS,DS0 VV TG VV ;

ID will increase as VDS is increased, but when VG – VDS = VT, pinch-off of channel occurs, and current saturates when VDS is increased further. This value of VDS is called VDS,sat. i.e., VDS,sat = VG – VT and the current when VDS= VDS,sat is called IDS,sat.

satD, 2VV

satDS,D VV TG VV ;

Here, Cox is the oxide capacitance per unit area, Cox = ox / xox

Example 5

Plot the ID vs. VDS characteristics for an NMOS with the followingparameters:

Substrate doping: 1016 cm–3. Oxide thickness = 100 nmGate width = 15m; Gate length = 1 m. Assume n = 500 cm2/(Vs)

satD, 2VV

satDS,DS VV TG VV ;

Find Cox: Cox = ox/ xox= 33.3 nF/cm2

Find ID,sat for different values of VG and plot the graph

VDS,sat = VG – VT

V15222221

SioxFT .qNxV

(5) MOSFET small-signal equivalent circuitThe dc characteristics for NMOS are reviewed below.

DSTGoxn

DVVVVC

LZI satDS,DS0 VV TG VV ;

satD, 2VV

satDS,DS VV TG VV ;

Saturation regionLinear region

MOSFET ac response

MOSFET ac response is routinely expressed in terms of small-signal equivalent circuits. This circuit can be derived from thetwo-port network shown below:

MOSFETinput outputG

The input looks like an open circuit, except for the presenceof the gate capacitor.

At output, we have a current ID which is controlled by VG and VDS.

ID = f (VG, VDS )

MOSFET small-signal equivalent circuit

ddgmd vgvgi DSG

gm = trans-conductance

gd = drain or channel conductance

Any ac signal in VG or VDS will result in corresponding ac variation in ID

where and

Note: id, vg and vd are small-signal ac currents and voltages. They are different from ID, VG and VDS which are dc currents and voltages.

Small-signal equivalent circuit

So, the equivalent circuit at low-frequency looks like (neglecting the gate capacitance low frequency):

For high-frequency, we have to include the capacitive effects:

MOSFET small-signal parameters

When VDS < VDS,sat (i.e., below pinch-off or linear region)

)( DSTGoxn

d VVVLCZg

m VLCZg

When VDS > VDS,sat (i.e., above pinch-off or saturation region)

gd = 0

)( TGoxn

m VVLCZg

Note: the parameters depend on the dc bias, VG and VDS

Frequency response of MOSFET

The cut-off frequency fT is defined as the frequency when the current gain is 1.

Input current = GGvCJ

Output current = Gmvg

vG here is ac signalCGS is approximately equal to the gate capacitance, Z L Cox

So, at fT, 12 GGST

Gm vCf

mT 2 C

CG-VG characteristics: MOS-C versus MOSFET

CG vs. VG characteristics of a MOSFET with VDS = 0

CG vs. VG characteristics of a MOSFET at high frequency looks similar to the low-frequency response (unlike the MOS-C). This is because, even at high frequency, the source and drain can supply the minority carriers required for the structure to follow the ac fluctuations in the gate potential when the device is inversion biased.

Enhancement mode MOSFETs

The devices we discussed so far are called “enhancement-modeMOSFETs.

For NMOS, VT is positive and one has to apply a positive gate voltage to turn on the device. At zero gate voltage, the device will be off.

For PMOS, VT is negative and one has to apply a negative gate voltage to turn on the device. At zero gate voltage, the device will be off.

Exercise: Draw the ID-VDS characteristics for NMOS and PMOSenhancement-mode devices.

Next class, we will discuss depletion-mode devices.

(6) Non-ideal MOS

So far, we have discussed MOS characteristics making some assumptions - calling it “ideal”.

– Assumed that the M = S , i.e. the bands are flat when no voltage is applied.

– Assumed that the oxide and oxide-semiconductor interface are free of charges.

These assumptions do not hold good in an actual MOS device, and we have to consider the deviations from the ideal case. For the purpose of discussions, we call these as “real”.

Metal-semiconductor work function difference - ideal

When M = S , the Fermi level is aligned before we make the device. So, when the MOS structure is made, the band remains flat when the applied gate voltage is zero.

Assumption MS = M – S = 0

EFSEFM

Flat band condition

Metal-semiconductor work function difference - real

M depends on the metal.Example: M (Al) 4 eV, M (Au) 5.1 eV

S depends on the semiconductor doping. S = + (EC – EF)FB

So, MS = M – S 0 in a “real” device.

So, actual band alignment before making the MOS-C structure looks as shown for Al-Si (p)

M = Al

Band diagram for MS = M – S 0

M = Al EFS

We have to apply a gate voltage = MS/q to get flat-band condition.

Polysilicon gate MOS

Modern day devices generally use heavily doped polysilicon asthe gate material.

For p+-polysilicon gate, EFM can be assumed to be at EV.For n+-polysilicon gate, EFM can be assumed to be at EC.

Question: If the substrate is intrinsic silicon, and the gate material is p+-polysilicon, calculate MS. (MS = Eg / 2 = 0.55 eV)

Question: If the substrate is n+-silicon, and the gate material is p+-polysilicon, calculate MS. (MS = + 1.1 eV)Show MS by drawing the band diagram.

What is the voltage that has to be applied to the gate to getflat-band condition? VG = 0.55 eV/q = 0.55 V

Interface and oxide charges

For the “ideal” device, we have assumed that the oxide and the interface is devoid of any excess charges. This is not true in practice.

+ + + + + + + + + + + + + + + + ++

Qmetal Assume that all these chargesare situated close to the interfaceon the oxide side (even thoughthey aren’t) and their concentrationis Qi Coulombs/cm2.

Qi = net interface charges in C/cm2

Effect of interface charges, Qi (C/cm2)

The interface charge Qi in the oxide (assumed positive) will induce some negative charges (Qi /cm2) in the semiconductor. The effectis as though we have applied a positive gate voltage to the gate, andthe negative charges in the semiconductor causes band bending. Toget “flat-band” condition, we have to apply a negative voltage to the gate.

Voltage to be applied to the gate to get flat-band condition ox

i wherex

Qi is usually positive (but can be both positive or negative in general).

Effects of work function difference and interface charges

If we consider the effects of work function difference and theinterface charges, the silicon band diagram may not be “flat” even when no voltage is applied to the gate. Hence, a correctionhas to be applied to the threshold voltage calculations carried outearlier assuming “ideal” MOS conditions.

qV voltage to be applied to the gate to

get flat band condition.=

'TFBT VVV where VT

’ is the threshold voltage assumingideal conditions (using equation 17.1 in text).

Effects of MS and Qi on CG-VG characteristics of MOS-capacitor

n-type

p-type

VFB VFB

A horizontal shift in C-V curve is observed. Routinely used to characterize MOS-C during IC fabrication.

actual

idealactual

Enhancement and depletion mode MOSFETs

Device is “off” when VG = 0 enhancement-mode MOSFETDevice is “on” when VG = 0 depletion-mode MOSFET

Threshold adjustment using ion implantation

p-type Siox

ionT C

Boron (+) ionsPhosphorous () ions

= positive shift for acceptor implantation

= negative shift for donor implantation

Bdose= # of boron ions/cm2 ; Pdose= # of phosphorus ions/cm2

Example 6

Consider an NMOS with oxide thickness of 0.1 m. The thresholdvoltage measured to be 0.5 V. Calculate the boron or phosphorousions to be implanted to make VT equal to 2 V.

VT = +1.5 V a positive shift. So use boron ions

14ox F/cm10453

cm1010F/cm1085893

ionsCBqVT Calculate B ions. (3.2 1011 ions/cm2)

During IC fabrication, ion-implantation is routinely used to tailor the the threshold voltage MOSFET device.

Lecture 04 Review of MOSFET - ece.uic.eduzyang/Teaching/20182019SpringECE541/Downloads/... · MOS Transistors - Types and Symbols D S G D S G G S D D S G NMOSEnhancement NMOS PMOS

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