Honeywell Advanced Photonics Development Overview ATLAS Meeting January 7, 1999 John Lehman Honeywell Technology Center lehman_john@htc.honeywell.com .
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Honeywell Advanced Photonics Honeywell Advanced Photonics Development OverviewDevelopment Overview
ATLAS Meeting
January 7, 1999
John LehmanHoneywell Technology Center
lehman_john@htc.honeywell.com
www.htc.honeywell.com
Oxide VCSEL Development Status/ImpactOxide VCSEL Development Status/Impact
• Low threshold/high slope efficiency demonstrated– Needed for low power operation/relaxes threshold/bias
uniformity requirements
• High temperature operation demonstrated– Slope efficiency less temp. dependent than implants - less
variation in output power– Required for military/rugged applications
• Uniformity demonstrated – Permits expansion to larger arrays (1D or 2D)
• Reliability demonstrated (preliminary) – Required
• Currently working to understand optimum device size for OMNET
““Planar” Trench-Defined Oxide StructurePlanar” Trench-Defined Oxide Structure
• Oxide layer exposed by etching trenches surrounding device
• Polymer Planarization not required
• Improved reliability/robustness
• Interconnect metal readily patterned
• More amenable to array fabrication
Honeywell Oxide VCSEL ReliabilityHoneywell Oxide VCSEL Reliability
• Over 240 oxide VCSELs samples • A variety of temperatures and currents used to stress
devices• Preliminary data indicates oxide VCSEL reliability is
equal to or better than implanted VCSELs (current Honeywell VCSEL MTTF > 107 hours at 40C 10mA)
• Oxide VCSELs show no degradation under 85%RH 85C exposure non-hermetic packaging
• Exposures made at Phillips Laboratory NM. • Honeywell Standard VCSEL• Exposure to 4.5 MeV protons• Total dose 1.51 x 1014 p/cm2 (119 Mrad total dose ; 4.9 x 1010 ions/cm2/sec flux)• Device recovers after 20mA constant current for 17 hrs.
Post irradiation
Pre-irradiation
Post anneal
Pre-irradiation
VCSEL Demonstrates Operation in 119 Mrad Total Dose (4.5 MeV protons) Environment
Baseline and Proton exposure L-I-V Baseline and post exposure anneal L-I-V
High speed properties of irradiated VCSEL
• Standard implanted VCSEL structure (850 nm)
• > 10 Mrad total dose (4.5 MeV protons)
• tr = 83 psec; tf = 104 psec
Uniformity & Yield of 3"-dia MOVPE-Grown Uniformity & Yield of 3"-dia MOVPE-Grown Planar Oxide-Confined VCSEL WaferPlanar Oxide-Confined VCSEL Wafer
157
141
125
109
93
77
61
45
29
13
169
161
153
145
137
129
121113
10597
8981
7365
5749
4133
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Lop
(mW
) at
3m
A
Row #
Collumn #
•HTC Wafer Growth/Process
•High Wafer Yield (99.7%est.)
•High Uniformity
•Utilizes In-House Commercially-Available MOVPE Chamber
•Material growth compatible with HI-Micro-Switch VCSEL Production
Uniformity at RT (1207a, 12x1 array, 5 um devices, at Iop =3mA)
-
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
4 8 12 16 20 24 28 32
Distance across wafer chord (mm)
840
842
844
846
848
850
852
854
856
858
860
Wa
ve
len
gth
(n
m)
I th
Ithest
Rs(kOhm)
N slp
V op
L op
Ne(%)/10
W op
Next Generation VCSEL Array Next Generation VCSEL Array UniformityUniformity
Current (mA)
Ou
tpu
t P
ow
er (
mW
)
Vo
ltag
e (
V)
0
1
2
3
4
5
6
7
8
9
10
0 1 2 3 4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0Ith Vop Lop
slp
Max 0.3 1.88 0.9 0.532Min 0.24 1.87 0.86 0.509Stnd Dev. 0.027 0.004 0.011 0.006
Vop = 2 mA
12 channels 250m pitch
Comparison COTS and ROV VCSELComparison COTS and ROV VCSEL SpecsSpecs (Honeywell HFE4080-321 vs. Oxide typical 5um… Test conditions: 0C < T < 70C)(Honeywell HFE4080-321 vs. Oxide typical 5um… Test conditions: 0C < T < 70C)
Parameter Typical Typicalstand (5um)COTS ROVs Units Change
Operating Current 12 3 mA 4xOutput Power 1.2 1.2 mW 1xThreshold Current 3.5 0.35 mA 10xSlope Efficiency 0.25 0.5 mW/mA 2xSlope Variation -0.5 -0.25 %/K 0.5xWallplug Efficiency 6 21 % 3.5xEfficiency Variation -0.5 -0.22 %/K 0.44xForward Voltage 1.8 2* Volts 1.11xSeries Resistance 30 180* Ohms 6xDivergence 15 30 FW(1/e2) deg. 2xThermal resistance 0.9 3* K/mW 3.3xPeak Wavelength 850 850 nm -Temp. Coefficient 0.06 0.06 nm/K -Spectral BW 0.5 1* nm 2xRIN@1GHz -128 -140 dB/Hz -Rise and Fall time 100 <100 ps
* Quite sensitive to size variation
0.0
0.5
1.0
1.5
2.0
2.5
0 2 4 6 8 10 12
current (mA)
Po
wer
(m
W)
0C
20C
40C
50C
60C
80C
100C
150C
150C
100C
80C60C
50C40C
0C
20C
Oxide VCSELs Demonstrating Range ofOxide VCSELs Demonstrating Range ofHigh and Wide Temperature OperationHigh and Wide Temperature Operation
0
0.5
1
1.5
2
2.5
3
0 20 40 60 80 100 120 140 160
Temperature (C)
Th
res
ho
ld c
urr
en
t (m
A)
830 nm
840 nm
850 nm
860 nm
Threshold current temperature Threshold current temperature dependence - Oxide VCSELdependence - Oxide VCSEL
5 um diameter
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 20 40 60 80 100 120 140 160
Temperature (C)
Ou
tpu
t P
ow
er
(mW
) @
3m
A
830 nm
840 nm
850 nm
860 nm
Output Power (3mA) temperature Output Power (3mA) temperature dependence - Oxide VCSELdependence - Oxide VCSEL
0
0.5
1
1.5
2
2.5
3
-55 -35 -15 5 25 45 65 85 105 125
Temperature (C)
Po
we
r:It
h:N
slp
I th ox
n ox
P(3mA) ox
Ith im x10
n im
P(12mA) im
850nm model
Comparison of Temperature performance - Comparison of Temperature performance - Oxide VCSEL/ImplantOxide VCSEL/Implant
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
-50 0 50 100
Temperature (C)
Po
we
r P
en
alt
y (
dB
) Pisi(2)
Per(2)
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
-50 0 50 100
Temperature (C)
Po
we
r P
en
alt
y (
dB
)
Pisi(2)
Per(2)
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
-50 0 50 100
Temperature (C)
Po
we
r P
en
alt
y (
dB
)
Pisi(2)
Per(2)
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
-50 0 50 100
Temperature (C)
Po
we
r P
en
alt
y (
dB
)
Pisi(2)
Per(2)
3mA - 30% 3mA + 30%
0.2mA + 30% 0.2mA - 30%
Low Threshold VCSEL less sensitive to bias Low Threshold VCSEL less sensitive to bias variationsvariations
Oxide Aperture size performance Oxide Aperture size performance summarysummary
Ith (mA) Vop
(V)R () (mW/mA) Speed
(packagedw/driver)
Zero-bias(1Gb/s)
CouplingTolerance/noise
Small(2-4 m)
0.22 2.3-2.7
210-300
0.28-0.44 RC –limit/needspeaking for >0.5 Gb/s– lowimped. drive
yes Excellent (SM)
Medium(5-9 m)
0.35 – 0.7 1.8-2.1
110-175
0.5-0.6 RC –limit/needspeaking for >1.0 Gb/s – lowimped. drive
yes Poor (2-3modes)
Large(13-18 m)
1.0 – 2.5 1.8-2.1*
30 -60
0.5-0.6 RC supports 2.5- 4 Gb/s
no Good (>6modes)
*Vop for med. Is 3 mA; large is 10mA
Oxide VCSEL Aperture Size Dependent Oxide VCSEL Aperture Size Dependent ParametersParameters
Parameters vs Oxide size for Iop = 3mA
0
0.5
1
1.5
2
2.5
0 1 2 3 4 5 6 7 8 9 10
Diameter (um)
Vo
p(V
); P
op
(mW
); It
h(m
A);
fm
ax
(GH
z)
0
1
2
3
4
5
6
7
Rs
(Oh
ms
)/1
00
; P
dis
(mW
);
10
xN
sl(
mW
/mA
)
Ith
Rs/1
Nslx10
Pdis
Vop
Pop
Near Field and FF Photos of Oxide Near Field and FF Photos of Oxide VCSELsVCSELs
2.5um-dia SM Oxide 9.5um-dia MM Oxide
Near Field
Far Field
(HW)=13.50 (HW)=14.50
00.10.20.30.40.50.60.70.80.9
11.1
0 50 100 150 200 250 300
Displacement (um)
Fib
er
Co
up
lin
g
1206B G5 M2 (2um) 3ma 1206B G5 M3 (3um) 3ma
1206B G5 M5 (5um) 3ma 1206B G5 M9 (9um) 3ma
Standard Implant 699 (10ma) 1201A-53 (13.5 um) 10ma
1201A-63 (18.5um) 10ma 1201A-73 (23.5um) 10ma
50%
62.5um MM
Coupling vs Fiber DisplacementCoupling vs Fiber Displacement
1Gb/s PRBS NRZ Eye diagram for Single-Mode oxide VCSEL: 1206bM2 2m-dia; Ith = 0.24mA; Ihi = 3mA
HP83487A head Il = 0
Gbit Ethernet RX: Il = IthGbit Ethernet RX: Il = 0
HP83487A head Il = Ith
Biased and Unbiased BER Characteristic for Single-Mode Oxide VCSEL: 1206b-G5-M2 (2-m dia): 1Gbit/s; Ith = 0.24mA
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-27 -26 -25 -24 -23 -22
Average Received Power (dBm)
log
(BE
R)
LowBias = 0.98V BaselineLowBias =0.00V BaselineLowBias=0.98V 6dB Vertical MSL at VCSELLowBias=0.00V 6dB Vertical MSL at VCSELLowBias=0.98V 3dB Vertical MSL at Tri-connectLowBias=0V 3dB Vertical MSL at Tri-connectLowBias=0.98V 6dB Vertical MSL at Tri-connectLowBias = 0V (I=0) 6dB Vertical MSL at Tri-connect
1Gb/s PRBS NRZ Eye diagram for MM Oxide VCSEL: 1206bM5 5m-dia; Ith = 0.38mA; Ihi = 3mA
HP83487A head Il = 0 HP83487A head Il = Ith
Gbit Ethernet RX: Il = IthGbit Ethernet RX: Il = 0
Turn-on delay Td vs Ihi for IL = 0; Multi-Mode Oxide VCSEL
1206b-M5: d= 5m; Ith = 0.38mA; l = 844nm
0
100
200
300
400
500
600
700
800
900
0 1 2 3 4 5Ihi (mA)
td (
pS
)
calc (ps)
measured (ps)
Biased and Unbiased BER Characteristic for Multi-Mode Oxide VCSEL: 1206b-G5-M5 (5-m dia): 1Gbit/s; Ith = 0.38mA
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-27 -26 -25 -24 -23 -22 -21
Average Power (dBm)
log
(BE
R)
Ib=0.0v 6dB MSL at VCSEL
Ib=0.97v 6dB MSL at VCSEL
Ib=0.97v (Ith) Baseline
Ib=0.0v Baseline
Ib=0.97v (Ith) 6dB MSL at Tri-connectIb=0.0v 6dB MSL at Tri-connect
Ib=0.97v (Ith) 6dB MSL at VCSEL9-04
Pulse shape for Single-Mode oxide VCSEL: 2um-dia Ith = 0.24mA; Ihi = 3mA
1206b M2 (2um diameter
Low bia s tr(pS ) tf(pS )
< Ith 140 125
"Ith 141 140
> Ith 152 137
Il < IthI > Ith
Il =Ith
• Integrated MSM/MESFET Design– 6000 mV/mW– 120 m detector
• Hybrid CMOS TIA w/ GaAs PIN– 100 m diameter
– tr,f < 50 psec
– 0.64 A/W– <0.5 pF
Receiver ApproachesReceiver Approaches
400 Mb/s PRBS-7
12 channel receiver array
Transimpedance Amplifier Driving 50/2pF Load for High Signal Input
2
1
191N 193N 195N 197N 199N
WFM.1 VPOS vs. TIME in Secs
2.00
1.60
1.20
800M
400M
VP
OS
in
Vo
lts
2.00
1.60
1.20
800M
400M
VN
EG
in
Vo
lts
Integrated MSM photodetectorIntegrated MSM photodetector
Typical device characteristics:
• Low dark current: Less than 10 nA @ 5V
• Responsivity: 0.34 (A/W) @ 5V for 850 nm wavelength
• Bandwidth: > 3 GHz
MARKER ( 5.000 V 9.713 nA ) OEP 903 100 um 2,3,4
150.0 u
IF
20.0 u /div
-150.0 u
(A)
o
-10.0 VF (V) 2.00 /div 10.0
Typical MSM IV curves, Pin = 0.44 mW
• Clock sent on one fiber - • 3 fibers/Mercury port (2.112 Gb/s data on 2 fibers,
clk)• 12 fibers for 4 ports• MUX/DMUX, 8b/10b coding• Open fiber control for eye safety
I/O buffer specification
RACEway Router
RxB
RxB
RxB
RxB
OMNET I/O16
2 Data1 Clk
12 VCSEL/Rx array
12 channel optical output(input)
16 Bits @132 Mb/s (electrical)
8B/10B
1.32 Gb/s (optical)
IBM 6SF CMOS Foundry Standard Features
• 0.25 m lithography• 0.18 m L effective• 2.5 V• 4 level metal• 200 mm wafer• Epi on p bulk• Single level poly• Tungsten filled vias• Options: diffused resistors, polysilicon/diffusion
capacitor, metal to metal capacitors, polysilicon resistors, additional levels of metal
Architecture of the buffer
6 6 M h z C L K
8 B 1 0 BE n c o d e r
8 1 0
S e r i a l i z e rV D
2 X
2 0 X
V D
T X C L K
T X B
8 B 1 0 BE n c o d e r1 6
8 1 0
S e r i a l i z e rV D
T X A
I/O buffer cell
Encode/Decode
Mux/ Demux
VCSEL Drivers
PD Amplifiers
Loopback Test
OFC
Temperature comp.
TX(0..15)
RX(0..15)
66Mhz CLKCBGA Package substrate
OPTOCARD
Router ASICport
Router ASIC (RACEway)
3
3
To other ports
From other ports
VCSEL12ElementArray
MSMdetectors12ElementArray
Sync/Asyncselect
RX CLK
8B10BDecoder
8B10BDecoder
16
8
8 10
10
/10
RXCLK
RX
Deserializer
Deserializer
LB Test
Fromout of SERA
SERA
SERB
RXB
RXA
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