High Performance MOS Current Mode Logic Circuits

High Performance MOS Current Mode Logic Circuits

Saied Hemati

Ph.D. Candidate

Ottawa-Carleton Institute for Electrical & Computer Engineering (OCIECE)

Carleton University

Ottawa, Canada

Introduction

CML versus VML

Different types of CML

- ECL

- CSL

- MCML

- DyCML

- Feedback MCML

A 10-Gbps MUX/DeMUX

Conclusion

Outline

Motivations for new logic styles:

- Higher speed.

- Lower power consumption.

- Lower area consumption.

- Lower fabrication cost.

- Higher robustness (environment noise , fabrication fluctuations, …).

- Low noise operation.

- Lower complexity (design, optimization, test,…).

What is wrong with CMOS?What is wrong with CMOS?

1- It is not suitable for high speed applications.

- Turn off time and turn on time limit the maximum speed.

- Power consumption increases by frequency.

- Each input at least is connected to two gates.

- P-type devices play a key role in CMOS.

- Voltage swing is too large.

- Rate of charging and discharging is not constant.

2- High dynamic power dissipation.- Large swing voltage.

- Large supply voltage and threshold voltage.

3- CMOS produces lots of noise.- Sharp switching currents.

- Voltage variation.

4- CMOS suffers from low robustness.- Propagation delay varies with supply voltage.

- Propagation delay varies with threshold voltage (80%).

- Noise can degrade the performance.

5- CMOS consumes too much area.- Pull up network.

6- Low degree of freedom in optimization.

1963-

201X

CMOS

What is Wrong With CMOS?What is Wrong With CMOS?What is Wrong With CMOS?What is Wrong With CMOS?What is Wrong With CMOS?

R1 R2

Inputs

I

out out

Current Mode Logic

1- Transistors are always on (fully or partially).- Higher speed

- Low threshold devices can be used.

- Lower Vdd .

- Lower power dissipation.

- Static power dissipation.- Static power dissipation.

R1 R2

Inputs

I

out out

Current Mode Logic

2- Swing voltage is small.- Higher speed

- Lower dynamic power dissipation.

- Lower noise generation .

- Lower noise margin.Lower noise margin.

3- Gates are based on n-type differential pair.- Immunity to common mode noise (supply bounce).

- Smaller input capacitance.

- Transistors should be identical.Transistors should be identical.

R1 R2

Inputs

I

out out

Current Mode Logic

4- Gates draw a static amount of current from power supply.- Reduces the amount of spiking of the supply and substrate voltages (lower noise).

- Rate of charging and discharging is constant.

- Higher level of freedom.

- Static power consumption.Static power consumption.

IVVCEVCVpE

IVpPowerIVCdelay

dddd

dd

22,

,

R1 R2

Inputs

I

out out

Current Mode Logic

5- P-type devices are never used as switch.- Higher speed.

- Lower number of transistors.

6- Pull up resistors are expensive.6- Pull up resistors are expensive.

7- Suitable power down techniques 7- Suitable power down techniques should be found. should be found.

8- The matching of fall and rise delays is 8- The matching of fall and rise delays is not easy.not easy.

Emitter Coupled Logic (ECL)

ECL is the fastest known logic family for silicon integrated circuits.

ECL gates consists of :

- differential amplifier.

- temperature and voltage

compensated bias network.

- Emitter follower output.

A B Vref

Rl R2

A+BA+B

VEE

VEEVEE

VcsVref=-1.25V

ECL NOR/ ORVOH= -0.85V

VOL= -1.75V

Emitter Coupled Logic (ECL)

Chip Technology in top500 supercomputers

Current Steering Logic (CSL)

A simple current mode logic with shortened swing voltage.

VOH = VT + Veff

VOL Veff

B

C

D

A

Vref

Vout

A 4-input CSL NOR

Ibias

Vdd

RFP

RFN

A A

out out

MOS Current Mode Logic (MCML)

Buffer/ Inverter

Inputs and outputs are differential.

Buffer and Inverter gates are the same.

Nor/Or/And/Nand gates are the same.

Mux/Xor gates are similar.

RFP

RFN

A(A) A(A)

Out(out) Out(out)

And/ Nand (Or/Nor)

B(B) B (B)

RFP

RFN

A A

out out

Xor

B B

MOS Current Mode Logic (MCML)

B

0 500 1000 1500 2000 2500 300010

20

30

40

50

60

70

Energy-Delay vs. Delay for MCML and CMOS XOR3

Delay (ps)

Ener

gy-D

elay

(pJ*

ps)

0 200 400 600 800 10001

1.5

2

2.5

Energy-Delay vs. Delay for MCML and CMOS Inverters

Delay (ps)

Ener

gy-d

elay

(pJ*

ps)

CMOSMCML

MOS Current Mode Logic (MCML)

MCML XOR3CMOS XOR3

MOS Current Mode Logic (MCML)

RFP

RFN

Vdd- Vswing Vdd

out out

+

-

Dynamic Current Mode Logic (DyCML)

Current source and load resistors

have been redesigned.

This configuration is similar

to differential cascode voltage swing

logic (DCVSL).

CLK

out out

CLK

CLK

CLK

Vdd

MCML Circuit

Vdd

Inputs

Feedback MOS Current Mode Logic

Threshold voltage fluctuation in short channel devices degrade matching between transistors in CML circuits.

Vth fluctuation is due to fluctuation in fabrication process :

- gate-oxide thickness.

- channel length.

- Random placement of the channel dopants.

.

.

Negative feedback can be used to improve robustness.

Feedback MOS Current Mode Logic

RFN

A A

out out

Buffer/ Inverter

Feedback MOS Current Mode Logic

For a first order system, gain-bandwidth is constant and feedback decreases gain and consequently increases bandwidth.

Sensitivity of the circuit to transistor mismatch decreases too.

RFN

A A

out out

CLK CLK

D_Type

flip-flop

Feedback MOS Current Mode Logic

Feedback MOS Current Mode Logic

D Q

D Q

CLK CLK

D Q

D Q

CLK CLK

D Q

D Q

CLK CLK

D Q

D Q

CLK CLK

D Q

D Q

CLK CLKCLK

CLK

D

D

Q0

Q0

Q1

Q1

Master Slave Master

Slave Master

A 10 Gb/s1:2 DeMux

Feedback MOS Current Mode Logic

Power-delay product for different approaches

Conclusion:

Current mode logic is attractive because of:

- high speed.

- Energy-delay product can be optimized by designer.

- immunity against noise.

- quiet logic family.

- suitable for low voltage applications.

Optimization of CML circuits is challenging and need more research.

N. S. Pickles, M. C. Lefebvre,“ ECL I/O buffers for BiCMOS integrated systems: a tutorial overview,” IEEE Trans. Education, vol. 40, No. 4, pp.229-241, Nov. 1997.

H. Ng, D. Allost, “ CMOS current steering logic for low-voltage mixed-signal integrated circuits,” IEEE Trans. VLSI Systems, Vol. 5, No. 3, pp.301-308, Sept. 1997.

J. Musicer, An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic, M.Sc. Thesis, University of California, Berkeley, 2000.

M.W. Allam, M. I. Elmasry, “ Dynamic current mode logic (DyMCL): A new low-power high performance logic style,” IEEE J. Solid State Circuits, Vol. 36, No. 3, pp. 550-558, March. 2001.

A. Tanabe, et al ,“ 0.18u CMOS 10Gb/s Multiplexer/Demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation,” IEEE J. Solid State Circuits, Vol. 36, No. 6, pp. 988-996, June. 2001.

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