High-Level Synthesis-II

Virendra SinghIndian Institute of Science

Bangalorevirendra@computer.org

IEP on Digital System Synthesis @ IIT Kanpur

Dec 18,2007 HLS@iitk 2

Architectural SynthesisArchitectural Level Abstraction

Datapath

Controller

Architectural Synthesis

• Constructing the macroscopic structure of a digital circuit starting from behavioural models that can be captured from Data flow or Sequencing Graph

Objective

• Area

• Cycle time

• Latency

• Throughput

Worst case bound

Evaluation

Architectural Exploration

Architectural synthesis tool can select an appropriate design point according to some user specific criterion and construct corresponding user specific Datapath and Controller

Circuit Specification for Architectural Synthesis

• Behavioural circuit model

• Details about resources being used and constraints

•Capture by Sequencing Graph

Resources

• Functional Resources

• Primitive Resources

• Application Specific Resources

• Memory Resources

• Interface Resources

Circuit Specification

• Sequencing Graph

• A set of functional resources, fully characterized in terms of area and execution delay

• A set of constraints

Computation: Differential Equation Solver

xl = x + dx

ul = u – (3*x*u*dx) – (3*y*dx)

c = xl < a

Data Flow Graph (DFG): represent operation and data dependencies

Data Flow Graph

* * * +

u dx 3 yu

dxx dx

dx y a

Sequencing Graph

* * * +

Hierarchical Sequencing Graph

b.2b.1

Architectural Synthesis and optimization consistes of two stages

1. Placing the operation in time and in space, i.e., determining their time interval of execution and binding to resources

2. Determining detailed interconnection of the datapath and the logic-level specifications of the control unit

Temporal Domain: Scheduling

Delay D = {di; i = 0,1, 2, ….. n}

Start time T ={ti; i= 0, 1, …., n)

Scheduling: Task of determining the start timing, subject to preceding constraints specified by sequencing graph

Latency λ = tn – t0

A scheduled sequencing graph is a vertex-weighted sequencing graph, where each vertex is labeled by its start time

Operation Start time

V1,V2, v6,v8, v10 1

V3, v7, v9,v11 2

Chaining

* * * +

TIME 1

TIME 2

TIME 3

TIME 4

TIME 1

TIME 2

TIME 3

TIME 4

TIME 5

TIME 6

TIME 7

Spatial Domain: Binding

A fundamental concept that relates operation to resources is binding

• Resource types

• Resource sharing

Simple case of binding is a dedicated resources

β(v1) = (1,1)

β(v2) = (1,2)

β(v3) = (1,3)

β(v4) = (2,1)

β(v5) = (2,2)

* * * +

TIME 1

TIME 2

TIME 3

TIME 4

A necessary condition for resource binding to produce a valid circuit implementation is that operation corresponding to the shared resource do not execute concurrently

A resource binding can be represented by a labeled hyper-graph, where the vertex set V represents operations and the edge set Eβ represents the binding of the operation to the resources

* * * +

TIME 1

TIME 2

TIME 3

TIME 4

(1,1) (1,2) (1,3) (1,4)(2,2)

* * * +

TIME 1

TIME 2

TIME 3

TIME 4

Sequencing Graph

* * * +

Hierarchical Sequencing Graph

b.2b.1

Synchronization

Area/Performance Estimation

Accurate area and performance estimation is not an easy task

Schedule: provides latency

Binding: provides information about the area

Retiming

7 7 70

11 1 1

Retiming

7 7 70

1 11 1

Delay = 24

Retiming

7 7 70

11 0 1

ASAP Scheduling

* * * +

TIME 1

TIME 2

TIME 3

TIME 4

ASAP Scheduling

ASAP(Gs(V,E)){

Schedule v0 by setting t0s = 1;

repeat{

select vertex vi whose predecessors are all scheduled;

schedule vi by setting tis = max{tjs+ dj}

} untill (vn is scheduled)

return ts

ALAP Scheduling

TIME 1

TIME 2

TIME 3

TIME 4

Scheduling under Timing Constraints

Scheduling under latency constraints

Absolute constraints on start time

Relative constraints

Relative timing constraints are positive integers specified for some operation pair vi, vj

A minimum timing constraint lij ≥ 0 requires tj ≥ ti+lij

A maximum timing constraint uij ≤ 0 requires tj

≤ ti+uij

Constraint Graph

Constraint Graph0

222- 3

Relative SchedulingScheduling under unbounded delay

The anchors of a constraint graph G(V,E) consists of the source vertex v0and all vertices with unbounded delay

Redundant anchor

Sequencing Graph

Scheduling with Resource Constraint

Scheduling under resource constraints

• computing area/latency trade-off points

Problems

• Intractable problem

•Area-performance trade-off points are affected by the other factors - non-resource dominated circuits

Scheduling with Resource Constraint

ILP Formulation

Binary decision variable X = {xil}

1. Start time of each operation is unique

Σl xil = 1

2. Sequencing relations represented by Gs(V,E) must be satisfied

Σl xil ≥ Σl xjl + dj

3. Resource bound must be met at every schedule step

Σk Σm xim ≤ ak

ILP FormulationAll operation must start only once

x0,1 = 1

x1,1 = 1

x2,1 = 1

x3,2 = 1

x4,3 = 1

x5,4 = 1

x6,1 + x6,2 = 1

x7,2 + x7,3 = 1

x8,1 + x8,2+x8,3 = 1

x9,2 + x9,3+x9,4 = 1

x10,1 + x10,2+x10,3 = 1

x11,2 + x11,3+x11,4 = 1

xn,5 = 1

ILP FormulationConstraints – based on sequencing

(more than one starting time for at least one operation)

2 x7,2 + 3 x7,3 – x6,1 – 2 x6,2 – 1 ≥ 0

2 x9,2 + 3 x9,3 + 4 x9,4 – x8,1 – 2 x8,2 – 3 x8,3 – 1 ≥ 0

2 x11,2 + 3 x11,3 + 4 x11,4 – x10,1 – 2 x10,2 – 3 x10,3 – 1 ≥ 0

4 x5,4 – 2 x7,2 – 3 x7,3 – 1 ≥ 0

5 xn,5 – 2 x9,2 – 3 x9,3 – 4 x9,4 – 1 ≥ 0

5 xn,5 – 2 x11,2 – 3 x11,3 – 4 x11,4 – 1 ≥ 0

ILP FormulationResource Constraints

x1,1 + x2,2 + x6,1 + x8,1 ≤ 2

x3,2 + x6,2 + x7,2 + x8,2 ≤ 2

x7,3 + x8,3 ≤ 2

x10,1 ≤ 2

x9,2 + x10,2 + x11,2 ≤ 2

x4,3 + x9,3 + x10,3 + x11,3 ≤ 2

x5,4 + x9,4 +x11,4 ≤ 2

ILP Formulation

Optimize ΣiΣl l.xil

x6,1 + 2 x6,2 + 3 x7,2 + 3 x7,3 + x8,1 + 2 x8,2 + 3 x8,3

+ 2 x9,2 + 3 x9,3 + 4 x9,4 + x10,1 + 2 x10,2 + 3 x10,3

+ 2 x11,2 + 3 x11,3 + 4 x11,4

Resource SharingResource sharing: Assignment of resource to more than one operation

Goal: Reduce area

Resource binding: explicit definition of mapping between resources and operation

Binding may imply some resources are shared

Optimum Schedulingunder Resource Constraint

TIME 1

TIME 2

TIME 3

TIME 4

Scheduled Sequencing Graph

TIME 1

TIME 2

TIME 3

TIME 4

Compatibility Graph

Conflict Graph

Transitive orientation of Compatibility Graph

Resource Sharing in Non-Hierarchical Seq. Graph

Searching for binding compatible

Σr bir = a

Σbir Σ xim ≤ 1

Scheduled and Bound Sequencing Graph

TIME 1

TIME 2

TIME 3

TIME 4

High-Level Synthesis-II

sequencing graph hls

scheduled sequencing

iitktemporal domain

iitkspatial domain

sequencing graphlatency

sequencing graphhls

concurrentlya resource

set of functional resources

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