Heterostructure Silicon (including Lecture-Tutorial-Laboratory Modules) Dept. of Electronics & ECE Indian Institute of Technology-Kharagpur First R & D.

Heterostructure Silicon

(including Lecture-Tutorial-Laboratory Modules)

Dept. of Electronics & ECE Indian Institute of Technology-

Kharagpur First R & D Centre in

Information and Communication Technology (ICT) Development among IITs

and Universities in IndiaPI: Prof. C. K Maiti, Co-PI: Prof A. S Dhar, and Prof

A. Halder

Research & Development focus

1. To develop e-learning materials for Heterostructure Silicon Course (including tutorial and laboratory modules) for final year undergraduates and postgraduate students and implement online simulation laboratory — real time simulation laboratory accessed through the Internet which can expand the range of simulation experiments in Heterostructure Silicon, transmit online instructions and study materials for anyone, anywhere and anytime.

2. development of e-content for an integrated teaching environment which allows for the provision of online live lectures (a 40-lecture module with tutorials) and a laboratory (10-12 simulation experiments) session for geographically dispersed students.

Steps for Development of RealTIME

Measurement-based Internet Laboratory

Design of ExperimentRemote Operation of the

Instruments(via LabVIEW, IC/CV lite, Easy Expert, VEE etc)

Conversion to Web Application

Launching on the Internet

Total Budget Outlay(Rs. in lakhs)Years

Head 1st 2nd 3rd Total

Capital Equipment Rs. 30.00 - - 30.00FE Comp.

Consumable stores Rs. 10.00 10.00 10.00 30.00

Software/License FeeDuty on import (if any) Rs. nil nil nil

nil

Manpower (JPA/RS/Eqv.) Rs. 7.00 8.00 9.0024.00

Travel & Training Rs. 3.00 4.00 5.0012.00

Contingencies/Accessories Rs. 10.00 13.00 16.0039.00

Grand Total (FE Comp.) 60.00 35.00 40.00 135.00

Grand Total : Rs.

135.00 lakhs

Course Description

IntroductionStrain Engineering in MicroelectronicsStress Induced During ManufacturingSubstrate EngineeringUniaxial vs. Biaxial Strain EngineeringHeteroepitaxy and Strain ControlVirtual SubstratesHybrid Substrates

Text Book: C. K. Maiti, S. Chattopadhyay, and L. K. Bera,"Strained-Si Heterostructure Field-Effect Devices", CRC Press(Taylor and Francis), USA, 2007.

40-50 lectures including tutorial based on the following contents:

Substrate-Induced Strain EngineeringProcess-Induced Stress EngineeringGlobal vs. Local StrainSubstrate-Induced StrainCharacterization of Strained LayersGate Dielectrics on Engineered SubstratesKinetics: Oxidation of Si1-xGex LayersOxidation of Strained-Si LayersRapid Thermal OxidationPlasma Nitridation of Strained-SiHigh-k GateDielectrics on Strained-SiNonclassical CMOS StructuresElectronic Properties of Engineered SubstratesOrientation-Dependent Mobility EngineeringEnergy Gap and Band StructureElectron MobilityHole MobilityFieldDependence

Doping DependenceCarrier LifetimeHeterostructure Field-Effect DevicesSiGe/SiGeC:Material ParametersSiGe Hetero-FETs: Structures andOperationSiGe p-MOSFETs on SOISiGeC Hetero-FETsSiGe-based HEMTsDesign IssuesStrained-Si Technology: Process IntegrationUniaxial Stress: Process FlowBiaxial Strain: Process FlowStrain-Engineered Hetero-FETs: Modeling and SimulationSimulation of Hetero-FETsStrained-SiMaterial Parameters forModelingSimulation of Strained-Si n-MOSFETsCharacterization of Strained-Si Hetero-FETsSPICE Parameter Extraction

VLSI Engineering Laboratory Module will consist of the

following experiments1. Doping Profile Determination 2. Bipolar Device Characterization3. MOS Capacitor Characterization4. MOSFET Characterization5. High Frequency Characteristics of BJT6. MOSFET SPICE Parameter Extraction7. Bipolar Transistor SPICE Parameter

Extraction8. 1/f Noise Characterization in Transistors9. Low Temperature Characterization of

Transistors10.LNA Characterization11.Noise Modeling in MOSFETs12.Cutoff Frequency Determination

Why Heterostructure Silicon ?

March of Technology• MOORE’S LAW : Transistor density on

integrated circuits doubles about every

two years – Intel co-founder Gordon E. Moore (1965)

• Microelectronic silicon computer “chips” have grown from a single transistor in the 1950s to hundreds of millions of transistors per chip on today’s microprocessor and memory devices

March of Technology

• Geometric scaling of transistors : Making Moore’s prediction true

• 90-nm technology → 65-nm technology → 45-nm technology → 32-nm technology

HALT IN MARCH ?HALT IN MARCH ?

• Performance Degradation for smaller gate lengths • Physical limits in scaling

Nano-electronics

0.01

0.1

1

10

1970 1980 1990 2000 2010 2020

Feature size

Year

10

100

1000

10,000

Fe

atu

re s

ize

(n

m)

Fe

atu

re s

ize

(m)

3m

0.8m

1m1.5m

2m

0.5m

0.35m 0.25m

0.18m0.13m

90nm

Gate length

50nmNano-electronics

0.01

0.1

1

10

1970 1980 1990 2000 2010 2020

Feature size

Year

10

100

1000

10,000

Fe

atu

re s

ize

(n

m)

Fe

atu

re s

ize

(m)

3m

0.8m

1m1.5m

2m

0.5m

0.35m 0.25m

0.18m0.13m

90nm

Gate length

50nm

Gate length

50nm

March of TechnologyHeterostructure

Engineering• Heterostructure Engineering: Will

ensure Moore’s law continues to hold true

• Novel solution to enhance device performance by inherently increasing the mobility of the charge carriers by straining the MOSFET channel

Strained-Si Epitaxial Layers2-D lattice view of Tensile strained-Si film

Vegard’s law: aSiGe(x)=aSi(1-x)+aGe(x)

x= Ge fraction

aSi=5.43 Å & aGe=5.66 Å

Band Structure of Tensile Strained-Si

xEC 67.0

xEV 6.0

(a) Band structure of bulk Si

(b) Band structure of bulk Ge

(c)2

... 23.0766.0 xxEE SiGSiSG

Band gap:

What is Technology CAD (TCAD)

Rising Technological ComplexityGate insulator

•SiO2/HiK•Leakage•Trapping

Gate•Work function•Depletion

Channel•Mobility

Raised S/D•Material•Activation•Diffusion

S/D extension•Activation•Junction (USJ)

Device Scaling = More Simulation NeededApplication: Design, analyze and optimize

semiconductor technologies and devices

Compact multi-level technology/ transistor/subsystem TCAD

modeling flow

Block

Gate

Circuit

Device

Process

Materials

Analog/DigitalDesign

Subcircuit expansion

Compact Model (BSIM, PSP, PCM)

Parameter extraction

Process/structural variations

Transistor optimization

Technology development

System performance

Process variationsProcess effect

on device/circuit

Defect effect on device/circuit

Block

Gate

Circuit

Device

Process

Materials

Analog/DigitalDesign

Analog/DigitalDesign

Subcircuit expansionSubcircuit expansion

Compact Model (BSIM, PSP, PCM)

Parameter extraction

Process/structural variations

Transistor optimization

Technology development

System performance

Process variationsProcess effect

on device/circuit

Defect effect on device/circuit

Advanced TCAD Simulation

• Process Simulation Updates• Device Simulation Updates• BSIM4 Model Extraction• Process Optimization using

process compact model (PCM)• Sensitivity, uncertainty & yield

analysis (Yield Management)

TCAD Optimization and Manufacturability

Manufacturing

TCAD Simulations

Generate new data

PCM

Visual querying &Visual optimization

Sensitivity, uncertainty & yield analysisDetermine the most stable process condition

Marked process conditions indicate low sensitivity of the device characteristics to the variations in corresponding Set of process (RED marked)

Yield analysis Device spec limits

Some Strained-Engineered Devices

0 0.1-0.1

0

-0.1

0.1

0.2 Silicon substrate

SiGe

(a)

SiGe

X (um)

Y (

um)

0 0.1-0.1

0

-0.1

0.1

0.2 Silicon substrate

SiGe SiGe

X (um)

Y (

um)

0 0.1-0.1

0

-0.1

0.1

0.2 Silicon substrate

SiGe

(a)

SiGe

X (um)

Y (

um)

0 0.1-0.1

0

-0.1

0.1

0.2 Silicon substrate

SiGe SiGe

X (um)

Y (

um)

0 0.1-0.1

0

-0.1

0.1

0.2

X (um)

X (

um

)Silicon substrate

Cap layer(b)

0 0.1-0.1

0

-0.1

0.1

0.2

X (um)

X (

um

)Silicon substrate

Cap layer

0 0.1-0.1

0

-0.1

0.1

0.2

X (um)

X (

um

)Silicon substrate

Cap layer(b)

0 0.1-0.1

0

-0.1

0.1

0.2

X (um)

X (

um

)Silicon substrate

Cap layer

Some available facilities

Hardware facilities

ELVIS SetupNetLAB Server

Noise Figure AnalyzerNetwork Analyzer

Spectrum Analyzer DC Probe station

AFM Setup

Agilent Semiconductor Test Analyzer

Software facilities• Instrument Control software

LabVIEW, VEE, VSA, IC-CAP, IC/C-V light, EasyExpert, Microsoft Inst., etc.

• TCAD softwareSILVACO, Sentaurus, MEDICI, TSupreme, Taurus, Monte Carlo, HSPICE, Nanosim, PCM studio, PARAMOS, etc.

Requirements: List of Equipment

1. Four Probe Resistivity Meter (25 lakhs) 2. Mask Aligner (75 lakhs) 3. Clean Air station (20 lakhs) 4. Rapid Thermal Annealing System (45 lakhs) 5. Semiconductor Test System (35 lakhs) 6. Microwave/ECR Plasma System (55 lakhs) 7. DC/RF Sputtering System (45 lakhs) 8. Probe station (50 lakhs) 9. Programmable power supply (20 Lakhs) 10. Thickness Measurement system (30 lakhs) 11. AFM/STM (30 lakhs) 12. Spectrum analyzer (10 Lakhs) 13. LCR Meter (10 lakhs) 14. Semiconductor Parameter Analyzer (50 lakhs) 15. Noise Figure Analyzer (55 lakhs) 16. Network Analyzer up to 26 GHz with calibration kits (200

lakhs) 17. Parameter extraction and device/process modeling

software tools (45 lakhs)

Achievement in ICT Area

1. NetLAB based Measurement and Analysis2. First On Line Laboratory Demonstration at

Andhra University (AU)3. First short term course on Information

Communication Technology (ICT) on Hardware Laboratory at IIT-Kharagpur

4. Arranged several short term courses on Technology CAD (TCAD) at IIT-Kharagpur

5. Arranged several short term courses on Technology CAD (TCAD) outside IIT-Kharagpur

Book Published1. Applications of Silicon-Germanium

Heterostructure Devices, Institute of Physics Publishing (IOP), UK, 2001.

2. Silicon Heterostructures: Materials and Devices, Institute of Electrical Engineers (IEE), UK, 2001.

3. Selected Works of Professor Herbert Kroemer, Edited, World Scientific, Singapore 2008.

4. Strained-Si Heterostructure Field-Effect Devices, CRC Press, London, 2007.

5. TCAD for Si, SiGe and GaAs Integrated Circuits, IET, UK, 2008.

OUR Publications on INTERNET LABORATORY on

MICROELECTRONICS• A. Maiti and S. S. Mahato, Online Semiconductor Device

Characterization and Parameter Extraction Using World Wide Web, Proc. NCNTE, Feb. 29 – Mar. 01, pp.160-163, 2008.

• A. Maiti and S. S. Mahato, Web-based Semiconductor Technology CAD (TCAD) Laboratory, 50th Intl. Symp. ELMAR-2008, Zadar, CROATIA, 10-12 September 2008.

• A. Maiti and S. S. Mahato, Web-based Semiconductor Process and Device Simulation Laboratory, Proc. of ICEE2008, Intl. Conf. on Engineering Education, "New Challenges in Engineering Education and Research in the 21st Century", PÉCS-BUDAPEST, HUNGARY, JULY 27-31, 2008.

• S. C. Pandey, A. Maiti, T. K. Maiti and C. K. Maiti, Online MOS Capacitor Characterization in LabVIEW Environment, International Journal of Online Engineering (iJOE), vol.5, pp.57-60, 2009.

• A. Maiti, M. K. Hota, T. K. Maiti and C. K. Maiti, Online Microelectronics and VLSI Engineering Laboratory, International Workshop on Technology for Education, Bangalore, Aug 04-06, 2009.

Currently Available Experiments via INTERNET

from IIT-KHARAGPUR(RealTIME Online Measurement-based)

1. Gummel Plot of a BJT2. Output Characteristics of a BJT3. Threshold Voltage of a MOSFET4. Output Characteristics of a MOSFET5. MOSFET Parameter Extraction6. BJT SPICE Parameter Extraction7. Low Noise Amplifier

Characterization8. Surface Analysis using AFM/STM9. Circuit Analysis Using NI-Elvis

NetLAB Webpage

Partner/USER Institutions

Our Current Partners areVIT, Vellore

NIST, Berhampur

OUR ONLINE LABORATORY HAS BEEN USED and TESTED BY

More Than 50 ENGINEERING COLLEGES

and10 UNIVERSITIES

Short Term Course/Workshop

AICTE/MHRD sponsored SUMMER SCHOOL at IIT KHARAGPUR

May 17-23, 2009

Applications of ICT for

Hardware Laboratory

52 participants from 40 Engineering Colleges

List of Participating Institutions

VIT University, VelloreNIST, BerhampurWest Bengal University of Technology,

KolkataUniversity of Calcutta Inst. of Radiophysics and ElectronicsNorth Bengal University, SiliguriNIT, DurgapurBengal Engg. and Science University, ShibpurTezpur (Central) University, Tezpur

IMPS College of Engg. and Technology, MaldaGurgaon College of Engg., HaryanaHi-Tech Institute of Technology, KhurdaNational Institute of Technology, WarangalSSN College of Engg., TamilnaduSynergy Institute of Engg. and Technology, DhenkanalMedi-caps Institute of Technology Management, IndoreDr. BR Ambedkar National Institute of Technology, PunjabJaypee Univ. Of Information Tech., Solan, H.P.Dronacharya College of Engg., Gurgaon, HaryanaCVR College of Engg., Hyderabad, A.P.Sai Spurthi Institute of Technology, A.P.Lingaya's Institute of Mgt and Technology, Faridabad

Purushottam Institute of Engg. Tech., Rourkela, OrissaNational Institute of Science & Technology, OrissaHi-Tech Institute of Tech., OrissaGLAITM, Mathura, U.P.Dr. B. C. Roy Engg. College, DurgapurTradient Academy of Tech., OrissaModern Engg. & Management Studies, OrissaGLA Institute of Tech. & Management, MathuraSynergy Institute of Engg. & Tech., OrissaITER, BhubaneswarSynergy Institute of Engg. & Tech., OrissaDRIEMS, CuttackLingaya’s University, FaridabadBirla Institute of Technology, PatnaDr. Sivanthi Aditanar College of Engg., Tamilnadu

PSN Group of Institutions, TamilnaduOrissa Engg. College, BhubaneswarJIET, CuttackRaajdhani Eng. College, BhubaneswarWorld Institute of Technology, GurgaonDept. of Bio-Medical Engg., Andhra UniversityAndhra University College of Engg., VisakhapatnamGITAM University, VisakhapatnamChaitanya college of Engg., VisakhapatnamSRKR Engg. College, VisakhapatnamGovt. Polytechnic, BheemiliSanketika Vidya Parishad Engg. College, VisakhapatnamJNTU College of Engg., HyderabadNational Engg. College, TamilnaduInstitute of Technology and Management, Gurgaon

Thank You