Transcript
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HDL Coder Workshop10 th February 2016, Trond heim
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Why are we here today?
Learn more about HDL Coder – The why, how, and what…
Get some hands on experience
– It’s more fun than just looking…
Give you the possibility to talk with MathWorks representatives
– Share your thoughts, give us feedback – We are here for you!
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What to do?
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Agenda
09:00 1. Introduction to Model-Based Design
2. MATLAB to HDL workflow
3. MATLAB HDL Verification
4. Simulink to HDL workflow
16:00 5. Simulink HDL Verification
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Who is Who?
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Before we start …
c:\class\coursefiles\hdl03(…and the handouts on your desk)
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Things to remember ….
Enable collaboration by integrating workflows with Model-Based D
Reduce development time with Automatic HDL Code generation
Reduce verification time with HDL/FPGA Co-simulation
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Introduction to Model-Based DesignIntegrated HDL Work flow
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Introduction to Model-Based DesignIntegrated HDL Work flow
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Who is involved in the design
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FPGA Designer System Designer
Algorithm Design
Fixed-Point
Timing / Control Logic
Architecture Exploration
Algorithms / IP
System Test Bench
Environment Models
Algorithms / IP
Analog Models
Digital Models
RTL Design
IP Interfaces
HW Architecture
Implement Design
Map
Place & Route
SynthesisFPGA Requirements
Hardware Specification
Test Stimulus
Introduction to Model-Based Design
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FPGA Designer System Designer
Algorithm Design
Fixed-Point
Timing / Control Logic
Architecture Exploration
Algorithms / IP
System Test Bench
Environment Models
Algorithms / IP
Analog Models
Digital Models
RTL Design
IP Interfaces
HW Architecture
Implement Design
Map
Place & Route
SynthesisFPGA Requirements
Hardware Specification
Test Stimulus
Introduction to Model-Based Design
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Implement Design
Map
Place & Route
Synthesis
Verification
Static Timing Analysis
Timing Simulation
Functional Simulation
BackAnnotation
HDL Co -SimulationAutomatic HDLCode Generation
Behavioral Simulation
MATLAB ® and Simulink ® Algorithm and System DesignModel Refinement for Hardware
FPGA HardwareFPGA -in -the -Loop
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Implement Design
Map
Place & Route
Synthesis
Verification
Static Timing Analysis
Timing Simulation
Functional Simulation
BackAnnotation
HDL Co -SimulationAutomatic HDLCode Generation
Behavioral Simulation
MATLAB ® and Simulink ® Algorithm and System DesignModel Refinement for Hardware
FPGA HardwareFPGA -in -the -Loop
Model-Based Desig
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Example
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From model to implementationIntegrated HDL Workflow – Video Mo saick
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From model to implementationIntegrated HDL Workflow – Video Mo saick
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From model to implementationIntegrated HDL Workflow – Video Mo saick
Microcontrolle
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From model to implementationIntegrated HDL Workflow – Video Mo saick
Microcontrolle
FPGACorner
Detection
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From model to implementationIntegrated HDL Workflow – Corner Detect ion
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From model to implementationIntegrated HDL Workflow – Corner Detect ion
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From model to implementationIntegrated HDL Workflow – Corner Detect ion
Test Bench
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From model to implementationIntegrated HDL Workflow – Corner Detect ion
Test Bench
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From model to implementationIntegrated HDL Workflow – FIR Filter
Simulat ion
Behaviora l Simulat ion
FPGA in the loo p
Stand Alo nPro to typ
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Algorithms to HDL?
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Algorithm to HDL Workflows
1. MATLAB to HDL2. Simulink to HDL
(with MATLAB and Stateflow)
3. Hybrid workflow
3
VHDL & VerVHDL & Verilog
1
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Agenda
09:00 1. Introduction to Model-Based Design
2. MATLAB to HDL workflow
3. MATLAB HDL Verification
4. Simulink to HDL workflow
16:00 5. Simulink HDL Verification
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MATLAB at a glance
The leading environment
for technical computing
– Interactive development environment – Technical computing language – Data analysis and visualization – Algorithm development
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Exercise
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(3) When yowill appe
(1) Navigate to folde01_MATLAB_intro
(2) Type the following commands in theMATLAB command window
(4) Use domain specific visualizationmethods
MATLAB at a glance | Exercise Getting Started
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MATLAB HDL
Floating point Fixed-Point
Procedural Concurrent + optimized
Untimed Timed with rates
Loops Streaming, Unrolling
FunctionsSystem objects
Hardware-efficieimplementations
Algorithm Land
Matrices Block RAMs
Arch
MATLAB to HDLThe big chal lenges
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Map
Place & Route
Synthesis
HDL Simulation
HDL Code Generation
Conversion to Fixed Pointand Fixed -Point Verification
MATLAB ® Algorithm and System DesignModel Refinement for Hardware
IterativeRefinement
usingFixed-Point Advisor
Implement Design
MATLAB to HDLWorkf low
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How do I get goodresults on my FPGA?
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1. Author MATLAB for hardware
2. Leverage HDL Coder workflow
3. Use synthesis and implementation tools
MATLAB to HDLHow do I ge t good resul t s on m y FPGA?
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1. Author MATLAB for hardware
2. Leverage HDL Coder workflow
3. Use synthesis and implementation tools
MATLAB to HDLHow do I ge t good resul t s on m y FPGA?
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Hardware Algo
Test Benc
Example :
Hardware Algorithm
MATLAB to HDL | Au tho r MATLAB for h ardware (1/3) Think Hardw are! – Separate Test Bench fro m Algo ri thm
• Contains stimulus and visualization code
• Contains algorithmic function targeted forimplementation in FPGA or ASIC
+
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MATLAB to HDL | Au tho r MATLAB for h ardware (2/3) MATLAB A uthor ing Bes t Prac t ices
Use Persistence when modeling:
Behavioral registers (e.g. tap delay lines)
RAM or ROM
Constant arrays
State machines
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MATLAB to HDL | Au tho r MATLAB for h ardware (3/3) MATLAB A uthor ing Bes t Prac t ices
Think about h ow ar rays a re used in the des ign to ge t the bes t resu l t s
Arrays can be represented as:
Wires
Flip-Flops
RAM
ROM
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1. Author MATLAB for hardware
2. Leverage HDL Coder workflow
3. Use synthesis and implementation tools
MATLAB to HDLHow do I ge t good resul t s on m y FPGA?
MATLAB HDL |
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MATLAB to HDL | Leverage HDL Cod er Workflo w (1/3) Why use f ixed-po int?
Fixed-point designs are:
– Smaller in silicon – Use less power – Give good performance
FPGAs contain fixed-point arithmeticunits optimized for performance
Careful control of word length allowsdesigners to balance resources andsample rate against fixed-pointperformance
MATLAB HDL |
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MATLAB to HDL | Leverage HDL Cod er Workflo w (2/3) Fixed-poin t convers ion
Automated workflow to convert floating point MATLAB to fixed-pointMATLAB
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Exercise
MATLAB t HDL |
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MATLAB to HDL | Exercise Fixed-poin t con version (1/7)
Automated workflow to convert floating point MATLAB to fixed-pointMATLAB
MATLAB to HDL | E i
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(3) Select fir.m
(4) Select fir_tb.m
(5) Click here to start WorkflowAdvisor
(2) Type in command
(1) Navigate to folder 02_MATLAB_2hdl
MATLAB to HDL | Exercise Fixed-poin t con version (2/7)
MATLAB to HDL | E i
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Input types are defined based on configured testbenches
(1) click “R
MATLAB to HDL | Exercise Fixed-poin t con version (3/7)
MATLAB to HDL | E i
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Select options:(1) “Log histogram data”
(2) “Show code coverage”
(3) Click on the green play buttonstart simulation
(2) Select “Propose worand default fraction le
Based on Simulation min/max range fixed-pointtypes are proposed
Use the logged histogram d
MATLAB to HDL | Exercise Fixed-poin t con version (4/7)
MATLAB to HDL | Exercise
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The coverage analysis is visually shown in the MATLAB code, this is agood quality measure of your test bench
MATLAB to HDL | Exercise Fixed-poin t con version (5/7)
MATLAB to HDL | Exercise
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This step Automatically generates fixed-point MATLAB code
(1) Click on the validate types to generate fixed-point MATLAB code
MATLAB to HDL | Exercise Fixed-poin t con version (6/7)
MATLAB to HDL | Exercise
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(1) Enable Log inputs and outputs foplots
(2) Click on the green play bsimulatio
This step runs a simulation to test the accuracy, please note also the graphic
(3) Repeat all steps with a default fraction length of 10, howmuch is the difference now?
MATLAB to HDL | Exercise Fixed-poin t con version (7/7)
MATLAB to HDL | LeverageHDLCod erWorkflo w(3/3)
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Automatically generate optimized HDL code from MATLAB
MATLAB to HDL | Leverage HDL Cod er Workflo w (3/3) HDL Coder
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Exercise
MATLAB to HDL | Exercise
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(1) Choose Generic ASIC/FPG(2) No synthesis tool specifie
Please note the different workflows:1. Generic ASIC/FPGA2. FPGA Turnkey
3. IP Core Generation (Zynq)
MATLAB to HDL | Exercise HDL Co der (1/6)
MATLAB to HDL | Exercise
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MATLAB to HDL | Exercise HDL Co der (2/6)
(1) Set all options as shown in t
MATLAB to HDL | Exercise
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(1) Please note the options to integratewith Simulink and System Generator
to |HDL Co der (3/6)
MATLAB to HDL | Exercise
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(2) Click on this link to see thutilization repo
(1) Click on “Run” togenerate HDL code
|HDL Co der (4/6)
MATLAB to HDL | Exercise
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(1) Click on this link to open ogenerated HDL fil
|HDL Co der (5/6)
MATLAB to HDL | Exercise (2) Look at the resource
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(1) Enable Stream loops to saveresources and click “Run”
|HDL Co der (6/6)
( )utilization report to see the
result
Agenda
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g
09:00 1. Introduction to Model-Based Design
2. MATLAB to HDL workflow
3. MATLAB HDL Verification
4. Simulink to HDL workflow
16:00 5. Simulink HDL Verification
MATLAB to HDL | Leverage HDL Cod er Workflo w (4/3)
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Stimulus ReferenceResults
Automatically Generated HDL Test Bench
Stimulus ActualResults
HDL Design
MATLAB Test bench
MATLAB DesignTargeted to Hardware
HDL Verificatio n
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Exercise
MATLAB to HDL | Exercise
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(1) Select the options as shown inthis GUI
(3) Click on the greestart ver
(2) Check out the Test BenchOptions
HDL Verif ication (1/2) | St imu li driven sim ulat ion
MATLAB to HDL | Exercise
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HDL Verif ication (2/2) | St imu li driven sim ulat ion
(1) Click on this link to open thesimulation report
MATLAB to HDL | Leverage HDL Cod er Workflo w (5/3)
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HDL Verifier
Connects HDL simulation withthe MATLAB environment!
HDLEntity
I n O u t
HDL Simulator
MATLAB FunctionsStimulus Response
Inputstimuli
Outputresponse
Re-use system level test benchCombine analysis in HDL Simulator and MATLAB/Simulink
HDL Verif icat ion | Co -simulat ion
MATLAB to HDL | Exercise f ( ) | l
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(1) Select the options as shown inthis GUI
(3) Click on the green Rustart verificat
(2) Check out thOp
HDL Verificatio n (1/2) | Co-Simu lation
MATLAB to HDL | Exercise HDL V ifi i (2/2) |C Si l i
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Analyze output based on HDLand MATLAB analysis Proof absence of erro
HDL Verificatio n (2/2) | Co-Simu lation
MATLAB to HDL | Leverage HDL Cod er Workflo w (6/3) HDLV ifi ti |C i l t i fH dW itt C d
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Use the ‘ cosimWizard ’ to integratehand-written HDL code for verification with MATLAB
and Simulink
HDL Verif ication | Co-simu lat ion of Hand Writ ten Code
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Demo
MATLAB to HDL | Leverage HDL Cod er Workflo w (7/3) HDLVerificatio n |FPGA in the Lo op
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HDL Verifier
Connects FPGA HW with theMATLAB environment!
MATLAB Functions
Inputstimuli
Outputresponse
Re-use the MATLAB test bench Accelerate Verification with FPGA Hardware
ResponseStimulus
HDL Verificatio n | FPGA-in-the-Lo op
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Demo
MATLAB to HDL | DEMO HDLVerificatio n |FPGA-in-the-Lo op
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(1) Configure all options andchoose your FPGA board
(2) Download more FPGAboards or add your own
(3) Clickb
HDL Verificatio n | FPGA-in-the-Lo op
MATLAB to HDL | DEMO HDLVerificatio n |FPGA-in-the-Lo op
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Analyze the FPGAoutput based onMATLAB analysis
Proof absence of ethrough FPGA veri
HDL Verificatio n | FPGA in the Lo op
MATLAB to HDL | Leverage HDL Cod er Workflo w (7/3) HDLVerificatio n |FPGA-in-the-Lo opWizard
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Both MATLAB and Simulink based FPGAthe-loop
Custom board s
Use the ‘ filWizard ’ to integratehand-written HDL code for
FPGA verification
HDL Verificatio n | FPGA in the Lo op Wizard
MATLAB to HDLHow do I ge t good resul t s on m y FPGA?
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1. Author MATLAB for hardware
2. Leverage HDL Coder workflow
3. Use Synthesis and Implementation Tools
g g y ?
MATLAB to HDL | Use Synthes is and Implementa tion Tools (1 /1Au tom ated Workflow for FPGA Imp lementat ion
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Integration with Vivado, Xilinx ISE and AlteraQuartus II
Project creationSynthesisPlace and RouteReporting – Resource utilization – Timing analysis
Rapidly explore implementa t ion opt ions throug h q uick i tera t ion of t rade-offs such assamp le rate and reso urce u t i l izat ion
Use loop streaming to reduceresource utilization
p
MATLAB to HDL | User Story FLIR Accelerates Developm ent of Thermal Imaging
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Challenge
Accelerate the implementation of advanced thermal imaging filters and algorithmson FPGA hardware
SolutionUse MATLAB to develop, simulate, and evaluate algorithms, and use HDL Coderto implement the best algorithms on FPGAs
Results
Time from concept to field-testable prototypereduced by 60%Enhancements completed in hours, not weeksCode reuse increased from zero to 30%
“With MATLAB and HDL Coder we are muc
responsive to marketplace needs. We now embecause we can take a new idea to a real-time
hardware prototype in just a few weeks.
There is more joy in engineering, so we’ve in
satisfaction as well as customer satisfaction
—Nicholas Hogasten, FLIR Systems
Link to user story
p g g
MATLAB to HDLSummary
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#1: Integrate separated workflows – Connect MATLAB algorithm developer with FPGA engineer
– One language, better collaboration
#2: Automatic HDL cod e generation – Rapidly explore implementation options – Make the right trade-off choices
#3: HDL/FPGA Co-simulation – Combine MATLAB analysis methods with FPGA/HDL analysis – Use the best of both worlds
Agenda
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09:00 1. Introduction to Model-Based Design
2. MATLAB to HDL workflow
3. MATLAB HDL Verification
4. Simulink to HDL workflow
16:00 5. Simulink HDL Verification
Algorithm to HDL Workflows
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1. MATLAB to HDL2. Simulink to HDL
(with MATLAB and Stateflow)
3. Hybrid workflow
3
VHDL & VerVHDL & Verilog
1
Simulink at a glance | Flexible Design Env ironm ent Design and Simulat ion
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Simulink, MATLAB and StateflowIntegrate with MATLAB Filter Design
Simulink at a glance | Enable Col laborat ion w ith Simulink PrVersion Contro l
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Manage design-related filesefficiently within Simulink
Search , manage , and share related files ina Simulink project
Access version control functionalityPeer review of changes using XMLcomparison tools
Merge Simulink models from within XMLcomparison reportView revision informationImpact Analysis
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Exercise(Getting Started)
Simulink at a glance | Exercise Getting Started
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Simulink at a glance | Exercise Getting Started | Part 1 (1/2)
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(4Sim
(1) Navigate to folder06_Simulink_intro
(3) OpenSimulink Library Browser
(2) Define model parameters in theMATLAB workspace
(7) D
Simulink at a glance | Exercise Getting Started | Part 1 (2/2)
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(6) Double-click on blocks and parameterizethem:
• Sine Wave:• Amplitude: 0.7; Frequency: 2*pi*50
• Sine Wave1:• Frequency: 2*pi*120
• Random Number:• Variance: 2; Sample Time: T
(5) Drag & drop the blocks fromlibrary into model and connect
them:
• Simulink/Sources• Simulink/Math Operations• Simulink/Sinks
(8) H
( )r
Simulink at a glance | Exercise Gett ing Started | Part 2 (1/2)
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(3) DefineOutput buffer size: L
(4) TickScale result by FFT length
(5) SelectOutput: Magnitude
(1) Drag & drop the blocks from library into modeland connect them:
• Simulink/Discrete• Simulink/Math Operations• DSP System Toolbox/Transforms• DSP System Toolbox/Sinks
(7) Se
• Scope Properties:
• Input Domain: Frequenc• Axis Properties:
• Y-axis scaling: Magnitu
(2) DefineSample time: T
(9) Hit “Start” button
Simulink at a glance | Exercise Gett ing Started | Part 2 (2/2)
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(9) Hit Start button
(8) Select in Display menu:
• Signal & Ports:• Signal Dimensions• Port Data Types
• Sample Time• Colors
Simulink to HDLModel-Based Design fo r Imp lementat ion
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1. Design and Simulation
2. Fixed-Point Conversion
3. HDL Creation
Simulink to HDLModel-Based Design fo r Imp lementat ion
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1. Design and Simulation
2. Fixed-Point Conversion
3. HDL Creation
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Exercise(Design and Simulation)
(1) Navigate to folde07_Simulink_Design_Simu
Simulink to MATLAB | Exercise Design and Simulat ion (1/5)
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(4) Open model
my_equalizer.slx
(2) Load ‘ matla
(3) LaunchFilter Design & Analysis T
Simulink to MATLAB | Exercise Design and Simulat ion (2/5)
(1) Explore design hierarchies
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(2) Filter_Hd4 will be genusing f
(3) Left filter bank will be addedafterwards
Simulink to MATLAB | Exercise Design and Simulat ion (3/5)
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(1) Open sessionfdatool.fda
(2) Open“Filter Manager
(3) Select Hd4_df2sos
(4) Examine filtercharacteristics
Simulink to MATLAB | Exercise Design and Simulat ion (4/5)
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(6) Compare block content of oth
(5) Move automaticablock in its intende
(3) Select“Build model using basic
elements”(1) Select
“Realize Model”
(2) Define block name,e.g. Filter_Hd4
(4) Hit“Realize Model”
(1) Move one hierarchy level up(Equalizer Subsystem)
Simulink to MATLAB | Exercise Design and Simulat ion (5/5)
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(Equalizer_Subsystem)
(2) Duplicate filter_bank_
(3) Instantiate it at the intendedposition and rename instance name,
e.g. “filter_bank_left”
(4) Hit “Start” button
Simulink to HDLModel-Based Design fo r Imp lementat ion
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1. Design and Simulation
2. Fixed-Point Conversion
3. HDL Creation
Simulink to HDL | Fixed-Point Con versio n (1/2) Fixed-Point Designer
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Convert floating-point to optimized fixed-point models – Automatic tracking of signal range
for both Simulink blocks and MATLAB function block – Using simulation and/or static analysis – Word / Fraction lengths proposal
Simulink to HDL | Fixed-Point Con versio n (2/2) Fixed-Point Designer
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Automatically compare simulation results,e.g. Floating-Point vs. Fixed-Point
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Exercise(Fixed-Point Conversion)
Simulink to HDL | Exercise Fixed-Point Conversio n (1/12)
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(2) Open modelmy_equalizer_fixed_point.slx
(4) Examine Fixed-Pointdata types
(3) Update Diagram (Ctrl-
(1) Navigate to folder08_Simulink_FixedPoint
(1) Descend in modelhierarchy to
filter bank right
Simulink to HDL | Exercise Fixed-Point Conversio n (2/12)
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filter_bank_right
(2) Right-click on outputsignal of multiplier and
select “Properties”
(3) Select“Log signal data”
Simulink to HDL | Exercise Fixed-Point Conversio n (3/12)
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(2) Right-click onfilter_bank_rightand select
“Fixed-Point Tool”
(1) Go one level up in the modelhierarchy to
Equalizer_Subsystem
(1) Select “Model -wide nooverride and fulli i ”
Simulink to HDL | Exercise Fixed-Point Conversio n (4/12)
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(4) Examine quantized dynamicrange of simulation results,
e.g. gain11
(3) Start simulation
instrumentation”
(2) Pl
Simulink to HDL | Exercise Fixed-Point Conversio n (5/12)
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(1) Select gain11 in the “InspectSignals” tab
(1) Select “Range collectionusing double override”
Simulink to HDL | Exercise Fixed-Point Conversio n (6/12)
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(4) Examine floating point
dynamic range of simulationresults,e.g. gain11
(3) Start simulation
(2) Ples
“D
Simulink to HDL | Exercise Fixed-Point Conversio n (7/12)
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(1) Compare original fixed-pointscaling with floating-point
reference(Compare Signals tab)
(2) Difference due to limitedresolution in fraction part
(inherent to fixed-point scaling)
Simulink to HDL | Exercise Fixed-Point Conversio n (8/12)
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(2) Examine the ‘Derived’ dynamicrange based on input specification
ranges
(1) Clickvalues fo
Simulink to HDL | Exercise Fixed-Point Conversio n (9/12)
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(3) Hit auto-scaling button
(1) Con
(2) Select fractioautoscaling (Propo
(2) Select appropriate Column View
Simulink to HDL | Exercise Fixed-Poin t Con vers ion (10/12)
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(4) Apply nes
(3) Examine fixed-pointscaling proposal
(1) Select “ DoubleOverride ” run forauto-scaling reference
(1) Select “Model -wide no
Simulink to HDL | Exercise Fixed-Poin t Conv ersio n (11/12)
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(4) Examine newly quantizeddynamic range of simulation
results, e.g. gain11
(3) Start simulation
(2) Dsim“N
(1) Select Model wide nooverride and fullinstrumentation”
Simulink to HDL | Exercise Fixed-Poin t Con vers ion (12/12)
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(1) Compare original fixed-point scaling with optimized
fixed-point scaling
(2) No differences, i.e. sameprecision with less area
consumption
Simulink to HDLModel-Based Design fo r Imp lementat ion
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1. Design and Simulation
2. Fixed-Point Conversion
3. HDL Creation
Simulink to HDL | HDL Creatio n (1/7) Au tom atic HDL Code Generat ion
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Automatically generate baccurate HDL code from Sim
and State
Full bi-directionaltraceability!!
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Exercise(Automatic HDL Code Generation)
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Simulink to HDL | Exercise Au tom atic Code Generat ion (2/4)
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(1) Right-click onEqualizer_Subsystem
(2) Select“HDL Coder Properties”
Simulink to HDL | Exercise Au tom atic Code Generat ion (3/4)
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(1) Select “ Equ
(2) Select HDL of your choice(VHDL / Verilog)
(3) Select the traceability and resourceutilization reports “Run Compa
(5) Hit“Generate”
Simulink to HDL | Exercise Au tom atic Code Generat ion (4/4)
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(1) Examine automaticallygenerated, generic RTL HDL code
(2) Follow the link to thecorresponding block in the
Simulink model
(3) Right- Click and select “HDL Code” > “Navigate to Code” to follow lfrom model to HDL code
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What else is there?
~180 blocks supported
Simulink to HDL | HDL Creatio n (2/7) HDL Suppo r ted Blocks
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Core Simulink Blocks – Basic and Array Arithmetic, Look-Up Tables, Signal Routing
(Mux/Demux, Delays, Selectors), Logic & Bit Operations, Dualand single port RAMs, FIFOs, CORDICs, Busses
Signal Processing Blocks – NCOs, FFTs, Digital Filters (FIR, IIR, Multi-rate, Adaptive, Multi-
channel), Rate Changes (Up &Down Sample), Statistics(Min/Max)
Communications Blocks – Pseudo-random Sequence Generators, Modulators /
Demodulators, Interleavers / Deinterleavers, Viterbi Decoders,Reed Solomon Encoders / Decoders,CRC Generator / Detector
MATLAB
Simulink to HDL | HDL Creatio n (3/7) MATLA B & Statef low fo r HDL
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– Relevant subset of the MATLAB language for modeling andgenerating HDL implementations
– Useful MATLAB Function BlockDesign Patterns for HDL
Stateflow – Modeling FSMs (Mealy, Moore)
– Use different modeling paradigms (Graphical Methods,
State TransitionTables, Truth Tables)
– Integrate MATLAB
Partition larger designs into smaller models
Simulink to HDL | HDL Creatio n (4/7) Model Reference
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Incremental HDL code generation
Engi
Engi
Simulink to HDL | HDL Creatio n (5/7) Integrat ing Legacy Cod e
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Integrate legaSimulink usi
Configure the interface to legacyHDL code
HDL Coder provideworkflow to inte
Gen
Simulink to HDL | HDL Creatio n (6/7) Integrat ing System Generator Subsys tems
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Take advantage of specific SystemGenerator functionality
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d d
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How do I get goodresults on my FPGA?
(Optimization etc.)
Simulink to HDLHow do I ge t good resul t s on m y FPGA?
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1. Modeling Best Practices
2. Speed Optimization
3. Area Optimization
Simulink to HDL | Mod eling B est Practices (1/7) Efficient Mapping to FPGA Resources
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Pre-adder in Virtex-6 / Spart an-6
Advanced HDL Synthesis Report (Selected Device : 6vsx315tff1156-1):-------------------------------------------------------------------
Macro Statistics
Simulink to HDL | Mod eling B est Practices (2/7) Efficient Mapping to FPGA Resources
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Macro Statistics# MACs : 4
17x16-to-33-bit Mult with pre-adder : 1
17x16-to-35-bit MAC with pre-adder : 3# Registers : 224
Flip-Flops : 224
Advanced HDL Synthesis Report (Selected Device : 5vsx50tff1136-1):------------------------------------------------------------------
Macro Statistics# MACs : 2
17x16-to-34-bit MAC : 2
# Multipliers : 217x16-bit registered multiplier : 2
# Adders/Subtractors : 517-bit adder : 435-bit adder : 1
# Registers : 195Flip-Flops : 195
Reset type set to ‘none’
Simulink to HDL | Mod eling B est Practices (3/7) Loo kup Tables to ROM
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Reset needs to be synchronousNeed a registered output, reset type set to ‘none’
It is good practice to structure your table such that the spacing betweenbreakpoints is a power of twoInput datatype determines how much memory will be allocated, 12 bits2^12 = 4096
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Simulink to HDL | Mod eling B est Practices (5/7) Bloc k RAM Uti l izat ion
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Dual/Single Port RAM Integer Delay
d l
Simulink to HDLHow do I ge t good resul t s on m y FPGA?
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1. Modeling Best Practices
2. Speed Optimization
3. Area Optimization
Finding the critical path in our model
Simulink to HDL | Speed Op tim ization (1/2) Finding the Cri t ical Path
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Applying pipelining strategies to improve speed
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Demo
Simulink to HDL | Demo Find ing the Critic al Path (1/8)
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(1) Navigate to folder10_Simulink_SpeedOpt
(2) Open modelmy_equalizer_sim_optimization.slx
Simulink to HDL | Demo Find ing the Critic al Path (2/8)
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(1) Open HDL Workflow Advisoron subsystem EqualizerAlgorithm
(1) Select synthesis tool, e.g.Xilinx ISE
Simulink to HDL | Demo Find ing the Critic al Path (3/8)
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(2) Select target FPGA device,Virtex4
(3) Hit “Run Task”
Simulink to HDL | Demo Find ing the Critic al Path (4/8)
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(1) Model Preparation and HDLCode Generation
Simulink to HDL | Demo Find ing the Critic al Path (5/8)
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(1) Trial synthesis using specifiedsynthesis tool
(2) Result: Static Timing Analysis(STA) report
Simulink to HDL | Demo Find ing the Critic al Path (6/8)
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(1) Starting point of cripath
Simulink to HDL | Demo Find ing the Critic al Path (8/8)
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(2) End point o
Fixed-Point Conversion – Optimal Fixed-Point will save area and improve critical path
Simulink to HDL | Speed Op tim ization (2/2) Strategies for Speed Imp rovem ent
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Architectural choices, e.g. – Linear, tree, cascade – Factored-Canonical-Signed-Digit (FCSD) – Newton-Raphson Approximation CORDIC
Pipelining – Input / Output pipeling – (Hierarchical) Distributed pipelining – Delay Balancing
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Exercise(Pipelining)
Simulink to HDL | Exercise Speed Optim ization | Pipelinin g (1/7)
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(1) Navigate to folder
10_Simulink_SpeedOpt
(2) Open modelmy_equalizer_sim_optimization.slx
(3) Navigate to subsystemEqualizerAlgorithm/filter_subsystem/filter_bank_left
(1) Right- Click on “Sum of Elements” Block and“HDL Code” > “HDL Block Properties”
Simulink to HDL | Exercise Speed Optim ization | Pipelinin g (2/7)
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(2) Specify “ OutputPipeline ” to 3
(3) Move one hierarchy level up
(1) Right- Click on “ filter_bank_left“HDL Code” > “HDL Block Prop
(3) Open Code > HDL Code
Simulink to HDL | Exercise Speed Optim ization | Pipelinin g (3/7)
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(2) Turn “ DistributedPipelining ” on
(3) Open Code > HDL Codeand generate HDL code for
“Equalizer Algorithm”
(1) Chose “Distributed Pipelining” report
Simulink to HDL | Exercise Speed Optim ization | Pipelinin g (4/7)
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(2) Open generated mode
(1) Navigate to “ filter_bank_left ”(5) Close generate
Simulink to HDL | Exercise Speed Optim ization | Pipelinin g (5/7)
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(2) The 3 output pipeline stages godistributed
(3) Dependent paths got balanced
(4) Verify delay balancing also on upperhierarchy levels
(4) R t HDL d
(1) Open “ filter_bank_left ”subsystem again
Simulink to HDL | Exercise Speed Optim ization | Pipelinin g (6/7)
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(2) Open HDL Bmultip
(3) Specify ConstrainedOutputPipeline to 1
(4) Regenerate HDL code on
EqualizerAlgorithm level,open Distributed Pipelining report,open generated model
(5) Close genera
Simulink to HDL | Exercise Speed Optim ization | Pipelinin g (7/7)
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(2) Multiplier b(3) Output pipeline of Sum block got adjustedto match overall number of pipeline stages (3)
(4) Balanced delay got adjusted as constrained output pipeline is placed incombined path
(1) Navigate to filter_bank_left
1. Modeling Best Practices
Simulink to HDLHow do I ge t good resul t s on m y FPGA?
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2. Speed Optimization
3. Area Optimization
Goal – Area reduction
Means
Simulink to HDL | Area Op tim ization (1/1) Resource Fold ing Algor i thm s
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Means – Time-multiplexed re-use of
resources
Algorithms – Resource Sharing
Re-use of identical operatorsor atomic subsystems withinalgorithm
– Resource StreamingRe-use of vectorizedoperators or subsystems
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Exercise(Area Optimization)
(1) Navigate to folder11 Simulink AreaOpt
Simulink to HDL | Exercise Area Op timizat ion | Streaming (1/8)
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11_Simulink_AreaOpt
(2) Open modelmy_equalizer_sim_optimization.slx
(3) Navigate to subsystemEqualizerAlgorithm/filter_subsystem/filter_bank_left
(1) Note vectorized coefficients
Simulink to HDL | Exercise Area Op timizat ion | Streaming (2/8)
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(2) Note vectorized output
(3) Scalar input signal is therefore processed by channelfilter (operators are parallelized)
(4) Goal: Parallel filter channels shall beimplemented by single filter, but time-
multiplexed (resource streaming)
Simulink to HDL | Exercise Area Op timizat ion | Streaming (3/8)
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(1) Open HDL Block Properties ofsubsystem Filter
(2) Specify StreamingFactor of 10
(3) Regenerate HDL code onEqualizerAlgorithm level
(1) Open Streaming and Sharingreport
Simulink to HDL | Exercise Area Op timizat ion | Streaming (4/8)
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report
(2) Open generated
(2) E i filt hit t
Simulink to HDL | Exercise Area Op timizat ion | Streaming (5/8)
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(1) Navigate to EqualizerAlgorithm/filter_subsystem/filter_bank_left/Filter
(2) Examine filter architectu
(2) Scalar input signals get aligned toserialized sample rate
Simulink to HDL | Exercise Area Op timizat ion | Streaming (6/8)
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(1) Vectored input signals getserialized and stored in shift registers
(1) Intermediate results get stored inshift registers to separate results of the
different filter channels
Simulink to HDL | Exercise Area Op timizat ion | Streaming (7/8)
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(1) Output signal gets vectorized again
Simulink to HDL | Exercise Area Op timizat ion | Streaming (8/8)
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What else is there?
Simulink to HDL | Legacy Cod e Integrat ion Black Boxing – Integrat ion of an Aud io Decoder
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3 rd party IP coresIntegrating legacy codHandwritten HDL cod
Integrate with downstream implementations tools Automatically create build scriptsGenerate multicycle path constraint reports
Simulink to HDL | Integrat ion w ith Down stream Too ls EDA Scripts
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y p p
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What if you need bothDSP and FPGA?
System-on-Chip | HW/SW Co-DesignS o C Wo rk f lo w
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= +SoftwaHardwareSystem
System-on-Chip | HW/SW Co -Design S o C E xa m p le
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System-on-Chip | HW/SW Co -Design S o C E xa m p le
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FPGA
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System-on-Chip | HW/SW Co -Design Targeting the ARM and the FPGA?
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1. How to map algorithms to the FPGA on the Zynq?
2. How to map algorithms to the ARM on the Zynq?
System-on-Chip | HW/SW Co -Design S o C Wo rk f lo w
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System-on-Chip | HW/SW Co -Design Targeting the ARM and the FPGA?
Hardware generation(VHDL and Verilog)
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ZYNQ
A X I B u s
ARMProcessor
Software – HDL Coder™(VHDL and Verilog)
Embedded software generation – Embedded Coder™
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DEMO(SoC Workflow - Zynq)
ChallengeImprove performance: from 50 Frames Per Second (fps) to >400 fps
Customer developing Image Processingapplication on Zynq platform
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Timeframe: complete project by end of 2015Embedded software engineer heard about Zynq but never programmed FPGAs
SolutionMathworks Model-Based Design approach for ZynqXilinx ZC702 development board
ResultsCustomer plans to release a new product to market in H1 of 2014;a year ahead of scheduleSave costs – replacing 3 processors and 3 cameras with one Zynq deviceand one cameraExpects to sell > 100,000 units a year!
Agenda
09:00 1. Introduction to Model-Based Design
2. MATLAB to HDL workflow
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3. MATLAB HDL Verification
4. Simulink to HDL workflow
16:00 5. Simulink HDL Verification
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Automatically generate baccurate HDL code from Sim
Simulink HDL Verification |Requirem ent Traceabil i ty
Simulink Verif icat ion and Validat ion
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Requirements
and State
Full bi-directionaltraceability!!
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Exercise(Requirement Traceability)
Simulink HDL Verification |Exercise
Simulink Verif icat ion and Validat ion | Requirements Traceabil i ty (1/4)
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(1) Navigate to folder12_Simulink_requirements
(2) Open modelmy_equalizer_requirements.slx
-and-Open MS Word documentRequirements_start.docx
(1) Select the requirements text in theMS Word document
Simulink HDL Verification |Exercise
Simulink Verif icat ion and Validat ion | Requirements Traceabil i ty (2/4)
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(2) RM B > Requirements > A dd lin k to Word se lec tion
Simulink HDL Verification | Exercise Simulink Verif icat ion and Validat ion | Requirements Traceabil i ty (3/4)
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(1) Ctrl-LMB click to highlight thelinked block in Simulink
(2) RM B > Requirements >
1. “Filter banks IIR SOS”to highlight the linked requirement
(1) Generate HDL code from theEqualizer_Subsystem,
goto line 191 of Equalizer_Subsystem.vhdin the traceability report
Simulink HDL Verification | Exercise Simulink Verif icat ion and Validat ion | Requirements Traceabil i ty (4/4)
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(2) Please note the hyperlinked
requirement in the report, click on thislink
1. Requirement Traceability
2 S l T i
Simulink HDL VerificationModel-Based Design fo r Imp lementat ion
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2. Structural Testing
3. Regression Testing
4. Rapid Prototyping
Simulink HDL Verification | Structural Test ing Simulink Verif icat ion and Validat ion | Test Coverage (Model)
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Missedcoverage
100%coverage
Automatically collereport test cover
Simulink HDL Verification | Structural Test ing Design Verif ier | Test Generat ion for 100% Test Coverage (Model)
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Automatically generate tereach coverage objecti
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Exercise(100% Coverage Testing)
(1) Navigate to folder
13 Simulink coverage
Simulink HDL Verification | Exercise Design Verifier | Ach ieving 100% Test Cov erage (1/4)
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13_Simulink_coverage
(2) Hit the s imula te button
(2) Open the effect_selection FSMPlease note the color coding indicating uncovered tclick on a “red colored transition” to see why it is n
Simulink HDL Verification | Exercise Design Verifier | Ach ieving 100% Test Cov erage (2/4)
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(1) Analyze the generated coverage report
How much coverage do we have?
(2) 77 test objectives are needed for 100% teselect C re at e h ar n es s m
Simulink HDL Verification | Exercise Design Verifier | Ach ieving 100% Test Cov erage (3/4)
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(1) RM B > Design Ver i f ier > G en er at e Te st s f o r S u bs y s te m
(2) Click here to simulate all
What is the test coverage n
Simulink HDL Verification | Exercise Design Verifier | Ach ieving 100% Test Cov erage (4/4)
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(1) Double click to open S ig n al B u i ld er s t im u l i (ifnot already open)
How many test cases are generated?
Simulink Test Bench ResponseStimulus
Re-use system level test benchCombine analysis in HDL Simulator and MATLAB/Simulink
Simulink HDL Verification | Structural Test ing Design Verifier + HDL Verifier | Test Cov erage (HDL Code)
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Input stimuli Outputresponse
Input stimuli Outputresponse
E i
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Exercise(100% Code Coverage)
(2) Open and Analyzegm_my_equalizer_coverage_harness_mq.tcl
-and-Test_Unit_copied_from_EQ_Parameters0_compile.do
Simulink HDL Verification | Exercise Design Verifier + HDL Verifier | Ac hievin g 100% Test Coverage (1/2) - (HDL Cod e)
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(1) Open the model gm_my_equalizer_harness_mq.slx
Please note: this model is automatically generated byHDL Coder
(1) Double click here to start
(2) Run all test casesHint: open the Signal Builder GUI
(3) HDL Verifier block wSimulink w
ModelSim®/Que
Simulink HDL Verification | Exercise Design Verifier + HDL Verifier | Ac hievin g 100% Test Coverage (2/2) - (HDL Cod e)
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(1) Double click here to startModelSim®/QuestaSim® (4) How
cover
(5) Please note the Simulinkscopes, is there a difference?
1. Requirement Traceability
2. Structural Testing
Simulink HDL VerificationModel-Based Design fo r Imp lementat ion
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2. Structural Testing
3. Regression Testing
4. Rapid Prototyping
Re-use system level test bench Accelerate Verification with FPGA HardwareUse application specific analysis methods
Simulink HDL Verification | Regression Test ing HDL Verifier | FPGA-in-the-Loo p
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Simulink Test Bench ResponseStimulus
Input stimuli Outputresponse
DEMO
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DEMO(FPGA-in-the-Loop)
Integration with FPGAdevelopment boards
Add your own F
Simulink HDL Verification | Demo HDL Verifier | FPGA-in-the-Lo op
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Automatic creation of FPGA-in-the-Loop verification models
1. Requirement Traceability
2. Structural Testing
Simulink HDL VerificationModel-Based Design fo r Imp lementat ion
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g
3. Regression Testing
4. Rapid Prototyping
Music in Music out Integrate withFPGA Develo
Simulink HDL Verification | Rapid Pro to typing FPGA Turnkey Work flow
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Automated workflow from model toFPGA prototype
Stand alone testing of algorithms onFPGA hardware
DEMO
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DEMO(FPGA Turnkey)
#1: Integrate separated workflows – One model, one language, better collaboration – Easily make algorithm trade-offs which impact performance
#2: Automatic HDL cod
e generation
WorkshopSummary
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#2: Automatic HDL cod e generation – Rapidly explore implementation options – What-if analysis for Area / Speed / Power
#3: HDL/FPGA Co-simulation – Combine Simulink analysis methods with FPGA/HDL analysis – Use the best of both worlds flexible test bench creation
Other Resources: Tutorials
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Jumpstart
AdvisoryServices
ProcessDeployment /
Standardization
Other Resources: We are here to help you!Accelera t ing re turn on inves tment
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Department / Corporate-wide InitiativeTeam or Project Specific
Services
Pilot Programs
Developers of MATLAB & Simulink
$700M annual revenue from – 125+ Countries – 23,000+ Companies
– 7+ Major Industries
Other Resources: We are here to help you!Accelera t ing re turn on inves tment
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Headquarters in Natick, MA – World-wide footprint – 2,400 total staff world-wide – World-wide technical and customer support
Technology focus – 30% of revenue invested in R&D
“ Accelerate the pace of engineering and science”
Web-based Resources- MathWorks home page- MATLAB Central
General Services- Technical Support
Other Resources: We are here to help you!Accelera t ing re turn on inves tment
http://www.mathworks.com/consulting/jumpstart.shtmlhttp://www.mathworks.com/consulting/jumpstart.shtml
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Technical Support- Training- Seminars- Workshops
Focused Services- Evaluations- Pilot Projects- Professional Services
Contact us for more information:
– Per-Johan.Wiklund@mathworks.com
Wrap Up and Q & AMore information…
http://www.mathworks.com/consulting/jumpstart.shtmlhttp://www.mathworks.com/consulting/jumpstart.shtmlmailto:Niklas.Moberg@mathworks.commailto:Niklas.Moberg@mathworks.commailto:Niklas.Moberg@mathworks.com
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– Jonas.Rutstrom@mathworks.com
Were Your Expectations Met?
Please complete and return seminar survey forms
Y d f db k i
mailto:Jonas.Rutstrom@mathworks.commailto:Jonas.Rutstrom@mathworks.commailto:Jonas.Rutstrom@mathworks.com
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