Gated or Clocked SR latch

1

Gated or Clocked SR latch Outputs change only when Enable(C) is HIGH.

2

Master-Slave SR flip-flop

Edge-Triggered Flip-flops 3

Edge-Triggered Flip-flops

Flip-flops: synchronous bistable devices Output changes state at a specified point on a

triggering input called the clock. Change state either at the positive edge (rising edge)

or at the negative edge (falling edge) of the clock signal.

Positive edges Negative edges

Clock signal

Edge-Triggered Flip-flops 4

Edge-Triggered Flip-flops

S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the clock input.

S CR

Q

Q'

S CR

Q

Q'

D C

Q

Q'

D C

Q

Q'

J CK

Q

Q'

J CK

Q

Q'

Positive edge-triggered flip-flops

Negative edge-triggered flip-flops

SR Flip-flop 5

Positive Edge-Triggered Flip-flops

S-R flip-flop: on the triggering edge of the clock pulse, S=HIGH (and R=LOW) a SET state R=HIGH (and S=LOW) a RESET state both inputs LOW a no change both inputs HIGH a invalid

Characteristic table of positive edge-triggered S-R flip-flop:

X = irrelevant (“don’t care”) = clock transition LOW to HIGH

S R CLK Q(t+1) Comments

0 0 X Q(t) No change0 1 0 Reset1 0 1 Set1 1 ? Invalid

NEGATIVE EDGE TRIGGERED

R-S FLIP-FLOP

Truth Table:CLK R S

0Q

X X1

NO CHGX X

0

X

0

NO CHGX NO CHG

0 NO CHG1

1 01 1

SETRESETILLEGAL

S

RCLK

Q

Q

D Flip-flop 7

D Flip-flop D flip-flop: single input D (data)

D=HIGH a SET state D=LOW a RESET state

Q follows D at the clock edge. Convert S-R flip-flop into a D flip-flop: add an inverter.

A positive edge-triggered D flip-flop formed with an S-R flip-flop.

S CR

Q

Q'CLK

D D CLK Q(t+1) Comments

1 1 Set0 0 Reset

= clock transition LOW to HIGH

D Flip-flop 8CS1104-11

D Flip-flop

Application: Parallel data transfer.To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and Q3 for storage.

* After occurrence of negative-going transition

Q1 = X*D

CLK

Q

Q'

Q2 = Y*D

CLK

Q

Q'

Q3 = Z*D

CLK

Q

Q'

Combinational logic circuit

Transfer

X

Y

Z

9

Gated or Clocked D latch

10J-K Flip-Flop

J-K(Jack–Kilby) Flip-flop This simple JK flip-Flop is the most widely used of all

the flip-flop designs and is considered to be a universal flip-flop circuit.

The basic gated SR NAND flip-flop suffers from two basic problems: number one, the S = 0 and R = 0 condition or S = R = 0 must always be avoided, and number two, if S or R change state while the enable input is high the correct latching action may not occur.

Then to overcome these two fundamental design problems with the SR flip-flop, the JK flip-Flop was developed.

11J-K Flip-Flop

J-K(Jack–Kilby) Flip-flop The sequential operation of the JK flip-flop is exactly

the same as for the previous SR flip-flop with the same "Set" and "Reset" inputs.

The difference this time is that the JK flip-flop has no invalid or forbidden input states of the SR Latch (when S and R are both 1).

The JK flip-flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level "1".

Due to this additional clocked input, a JK flip-flop has four possible input combinations, "logic 1", "logic 0", "no change" and "toggle".

12J-K Flip-Flop

J-K Flip-flop

J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.

No invalid state. Include a toggle state.

J=HIGH (and K=LOW) a SET state K=HIGH (and J=LOW) a RESET state both inputs LOW a no change both inputs HIGH a toggle (Output changes state only once

for each pulse)

13J-K Flip-Flop

J-K(Jack–Kilby) Flip-flop Symbol and Circuit Diagram of JK Flip-flop:

J-K Flip-flop 14

J-K Flip-flop

Characteristic table.

J K CLK Q(t+1) Comments

0 0 Q(t) No change 0 1 0 Reset 1 0 1 Set 1 1 Q(t)' Toggle

A. Yaicharoen 151/50

Master-Slave JK flip-flop

T Flip-flop 16CS1104-11

T Flip-flop

T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together.

Characteristic table.

T CLK Q(t+1) Comments

0 Q(t) No change1 Q(t)' Toggle

Q T Q(t+1)

0 0 00 1 11 0 11 1 0

Q(t+1) = T.Q' + T'.Q

TQ

Q'CLK

Pulse transition detector

J CK

Q

Q'CLK

T