Transcript
EN 315 Euler Path Design/gbbarte 1
Complex Logic Gates LayoutEuler Path Method
EN 315 VLSI DesignDr. Gil B. Barte, Ph.D.
EN 315 Euler Path Design/gbbarte 2
Inverter layouts
EN 315 Euler Path Design/gbbarte 3
EN 315 Euler Path Design/gbbarte 4
EN 315 Euler Path Design/gbbarte 5
EN 315 Euler Path Design/gbbarte 6
EN 315 Euler Path Design/gbbarte 7
EN 315 Euler Path Design/gbbarte 8
EN 315 Euler Path Design/gbbarte 9
g = a. (b + c)
EN 315 Euler Path Design/gbbarte 10
EN 315 Euler Path Design/gbbarte 11
EULER PATH LAYOUT
• Design the layout of function F
• F = /(A.B.C)• Design the Static
CMOS transistor circuit of F
A B C
C
B
A
Gnd
F
Vdd
EN 315 Euler Path Design/gbbarte 12
Euler Paths
A B C
C
B
A
Gnd
F
Vdd
I1
I2
The P GraphA B C
Vdd
F
The N Graph F
I2
BI1
C
A
Gnd
Edge representing a transistor
Vertex / Node
EN 315 Euler Path Design/gbbarte 13
Dual Graphs
AB C
Vdd
F
F A I2 B I1 C Gnd
A B C
Vdd
F
F
AI2
BI1
CGnd
N-Graph
P-Graph
EN 315 Euler Path Design/gbbarte 14
Arrange n & p Euler paths with identical labelling
• The N-Euler Path
• The Identical P-Euler Path
F
B
C
AI2
I1
Gnd
F A I2 B I1 C Gnd
A B C
Vdd
F
F A Vdd B F C Vdd
EN 315 Euler Path Design/gbbarte 15
Implement in Layout
F A I2 B I1 C GndF A Vdd B F C Vdd
P-Euler Path N-Euler Path
A B C
F I2 I1 Gnd
F Vdd F Vdd
EN 315 Euler Path Design/gbbarte 16
Single Row Transistors
• Use of a single row of n-transistors and a single row of p-transistors
• The transistor rows are put in top of one another
Or
P-Trs
N-Trs
EN 315 Euler Path Design/gbbarte 17A B C
EN 315 Euler Path Design/gbbarte 18
Vdd
A B C
GND
Out=/(A.B.C)
EN 315 Euler Path Design/gbbarte 19
Metal Layout
A B C
F I2 I1 Gnd
F F VddVdd
EN 315 Euler Path Design/gbbarte 20
Euler Path (line of Diffusion Technique)
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Z = a + b + c.d
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EN 315 Euler Path Design/gbbarte 23
EN 315 Euler Path Design/gbbarte 24
EN 315 Euler Path Design/gbbarte 25
XNOR
EN 315 Euler Path Design/gbbarte 26
Exercise
)(. EDCBAF ++=
EN 315 Euler Path Design/gbbarte 27
XNOR Implementation Example
)()( baMbaabbaabf +=+=+=
Vdd
A B
B
A
Gnd
M
Vdd
M
M
A B
A
B
f
Gnd
EN 315 Euler Path Design/gbbarte 28
A B
B
A
Gnd
M
Vdd
Euler Path for P circuit
Vdd A M B Vdd
Euler Path for N circuit
M A B Gnd
M
Vss
Vdd
a b
EN 315 Euler Path Design/gbbarte 29
)( BAMf +=Vdd
M
M
A B
A
B
f
Gndf
Vss
Vdd
M A B
EN 315 Euler Path Design/gbbarte 30
XNOR Implementation Example
)()( baMbaabbaabf +=+=+=
A single row of n-and p-transistors
with break
a b
M
Vss
Vdd
f
Vss
Vdd
M A B
EN 315 Euler Path Design/gbbarte 31
XNOR Other Implementation
ab
M
Vss
Vdd
f
Vss
Vdd
MA
B
EN 315 Euler Path Design/gbbarte 32Turn 180 degrees to use one Vdd
M
Vss Vdd
ab
M
Vdd
f
Vss
Vdd
MA
B
EN 315 Euler Path Design/gbbarte 33
M
Vss Vdd
ab
M
Vdd
f
Vss
Vdd
MA
B
Remove one of the Vdd lines and connect a & b
gates
EN 315 Euler Path Design/gbbarte 34
M
Vss Vdd
a
b
f
Vss
M
A
B
N-Well
Can also be moved to n area to reduce size
EN 315 Euler Path Design/gbbarte 35
M
Vss Vdd
a
b
f
N-Well
Vss
M
A
B
f
EN 315 Euler Path Design/gbbarte 36
M
Vss Vdd
a
b
f
N-Well
M
f
EN 315 Euler Path Design/gbbarte 37
Additional Exercises
EN 315 Euler Path Design/gbbarte 38
Stick Diagrams
C
A B
X = C • (A + B)
B
AC
i
j
j
VDDX
X
i
GND
AB
C
PUN
PDNABC
Logic Graph
EN 315 Euler Path Design/gbbarte 39
Two Versions of C • (A + B)
X
CA B A B C
X
VDD
GND
VDD
GND
EN 315 Euler Path Design/gbbarte 40
Consistent Euler Path
j
VDDX
X
i
AB
C
GND A B C
EN 315 Euler Path Design/gbbarte 41
OAI22 Logic Graph
C
A B
X = (A+B)•(C+D)
B
A
D
VDDX
X
AB
GND
C
PUN
PDN
C
D
D
ABCD
EN 315 Euler Path Design/gbbarte 42
Example: x = ab+cd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}b
EN 315 Euler Path Design/gbbarte 43
Advantages
• Can be automated• Group transistors in strips allow maximum
source/drain connection by abutment • Manhattan (vertical & horizontal) metal
routing (eg a maze router) • Smaller size cell layout• Less complex masks/less cost
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