ECEN 248 –Introduction to Digital Systems Design …ece.tamu.edu/~xizhang/ECEN248/Chapter_7_8_Chapter_Part-I_Xi_Zhan… · Systems Design (Spring 2008) (Sections: 501, 502 ... Sequential
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ECEN 248 –Introduction to Digital Systems Design (Spring 2008)
(Sections: 501, 502, 503, 507)
Prof. Xi ZhangECE Dept, TAMU, 333N WERC
http://ece.tamu.edu/~xizhang/ECEN248
Chapter 7 (Conted.) A simple shift register
Figure 7.18. A simple shift register.
t 0
t 1
t 2
t 3
t 4
t 5
t 6
t 7
1
0
1
1
1
0
0
0
0
1
0
1
1
1
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0
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Q 1 Q 2 Q 3 Q 4 Out = In
(b) A sample sequence
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out
(a) Circuit
Q 1 Q 2 Q 3 Q 4
Shift register is composed by a number of D flip-flops.
Parallel-access shift register
Figure 7.19. Parallel-access shift register.
Q3 Q2 Q1 Q0
ClockParallel input
Parallel output
Shift/LoadSerialinput
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Break page between Ch 7 and 8
Chapter 8. Synchronous Sequential circuits
The definition of sequential circuitsA general class of circuits in which the outputs depend on the past behavior/state of the circuit, as well as on the present values of the inputs. There are two different types of sequential circuits:
1) Synchronous sequential circuitsControlled by a clock signal.2) Asynchronous sequential circuitsNo clock signal is used.
Synchronous sequential circuits
Figure 8.1. The general form of a sequential circuit.
Combinational circuit
Flip-flopsor Storage
circuits
Clock
Q W
Z Combinational
circuit
A synchronous sequential circuit consists of a number of combinational circuits and flip-flops.Flip-flops are used to store past behaviors. Flip-flops have to be the edge-trigged type.
Synchronous sequential circuits
Figure 8.1. The general form of a sequential circuit.
Combinational circuit
Flip-flopsor Storage circuits
Clock
Q W
Z Combinational
circuit
Input: WOutput: ZState: Q (the output of the flip-flops)States represents the past behaviors of the circuit.
Finite State Machine (FSM)
Sequential circuits are also called finite state machine (FSM), or simply machine.There are two types of synchronous sequential circuits:
Moore typeOutputs depend ONLY on current states.Mealy typeOutputs depend on BOTH current states and current inputs
General form of a Moore-type FSM
Combinational circuit
Flip-flops
Clock
Q W
Z Combinational
circuit
General form of a Mealy-type FSM
Combinational circuit
Flip-flops
Clock
Q W
Z Combinational
circuit
Steps to design a FSM (Moore & Mealy)
State diagramState table
State assignmentChoice of flip-flops and derivation of next-state and output expressions
Timing diagramFinal implementation of the circuit.
Example of designing “sequence detector” (Moore Type)
The circuit has one input, w, and one output, z.All changes in the circuit occur on the positive edge of a clock signal.The output z is equal to 1 if during two immediately preceding clock cycles the input w was equal to 1. Otherwise, the value of z is equal to 0. Thus, the circuit detects if two or more consecutive 1s occur on its input w.
Input and output signals of the sequence detector
Figure 8.2. Sequences of input and output signals.
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0
State diagram of sequence detector
A: starting state, also the state after an input w=0 is applied.B: The first occurrence of w=1 (after last time when w=0).C: w=1 in two most recent successive clock cycles.
Figure 8.3. State diagram of a simple sequential circuit.
C z 1 = ⁄
Reset
B z 0 = ⁄A z 0 = ⁄w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
State table for the sequence detector
Figure 8.4. State table for the sequential circuit in Figure 8.3.
C z 1 = ⁄
Reset
B z 0 = ⁄A z 0 = ⁄w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 = Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
Moore: Output is inside of state circle,not depends on inputs
A general sequential circuit implementation
Figure 8.5. A general sequential circuit with input w, output z, and two state flip-flops.
Combinationalcircuit
Combinationalcircuit
Clock
y2
z
wy1Y1
Y2
State-assigned table for the sequence detector
Figure 8.6. State-assigned table for the sequential circuit in Figure 8.4.
Present Next state
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 Y 2 Y 1 z
A 00 00 01 0 B 01 00 10 0 C 10 00 10 1
11 dd dd d
Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
Derivation of logic expressions (use D flip-flops) for sequence detector
Figure 8.7. Derivation of logic expressions for the sequential circuit in Figure 8.6.
w 00 01 11 10
0
1
0
1 0
y 2 y 1
Y1 wy 1 y 2 =
w 00 01 11 10
0
1
0 d
1 d
y 2 y 1
Y 2 wy 1 y 2 wy 1 y 2 + =
d
d
0
0
0
0
0
0
1
0 1
0
1
0
d
y 1
z y 1 y 2 = 0
1
y 2
Y1 wy 1 y 2 =
Y 2 wy 1 wy 2 + =
z y 2 =
w y 1 y 2 + ( ) =
Ignoring don't cares Using don't cares
Present Next state
state w = 0 w = 1 Output
y 2 y 1 Y 2Y 1 Y2 Y 1 z
A 00 00 01 0 B 01 00 10 0 C 10 00 10 1
11 dd dd d
Final implementation (use “don’t cares”) of the sequence detector
Figure 8.8. Final implementation of the sequential circuit derived in Figure 8.7.
D Q
Q
D Q
Q
Y 2
Y 1 w
Clock
z
y 1
y 2
Resetn
Timing diagram for the circuit
Figure 8.9. Timing diagram for the circuit in Figure 8.8.
t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 101 0
1
0
1
0
1
0
Clock
w
y 1
y 2
1
0 z
Summary of design stepsObtain the specification of the desired circuit.Draw the state diagram
Selecting a starting stateGiven the staring state
consider all valuations of inputs to the circuitcreate new states to respond to these inputsrecord the corresponding outputs and state transitions
Create a state tableState minimization (in section 8.6)State assignment
Decide the number of state variables needed to represent all statesperform the state assignment (not unique).
Choose the type of flip-flops for the circuit (D-type flop-flops so far)Derive logic expressions for
the next-state the output.
Figure 8.16. Improved state assignment for the sequential circuit in Figure 8.4.
Present Next state
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 Y 2 Y 1 z
A 00 00 01 0 B 01 00 11 0 C 11 00 11 1
10 dd dd d
Improved state assignment
Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
Comparison between different assignments
Figure 8.6. Original assignment for the sequence detector.
Present Next state
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 Y 2 Y 1 z
A 00 00 01 0 B 01 00 10 0 C 10 00 10 1
11 dd dd d
Figure 8.16. Improved state assignment for the sequence detector.
Present Next state
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 Y 2 Y 1 z
A 00 00 01 0 B 01 00 11 0 C 11 00 11 1
10 dd dd d
Figure 8.17. Final circuit for the improved state assignmentin Figure 8.16.
D Q
Q
D Q
Q
Y2
Y 1 w
Clock
z
y 1
y 2
Resetn
Final circuit for the improved state assignment
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