ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 7.

ECE 353Introduction to Microprocessor Systems

Michael G. Morrow, P.E.

Week 7

TopicsMicroprocessor support circuits Clock and reset generation Power control Microprocessor supervisors

I/O subsystems GPIO pin construction I/O port design I/O decoding I/O synchronization ADuC7026 GPIO

ADuC7026 Block Diagram

ClocksClock Generation Clock oscillators External clocks Phase-locked loops (PLLs)

Operation and design issues ADuC7026 clocking

PLLCON

Power Control ADuC7026 operating modes

POWCON ADuC7026pin-out

ResetThe reset signal is used to force the processor into a known state from which operation can reliably be started.On power up, the reset signal should be asserted long enough to ensure that the supply voltages are stable and the oscillator is running and stableReset Generation RC reset circuit operation Shortcomings

ADuC7026pin-out

Microprocessor Supervisors

Microprocessor supervisors provide reset functionality for a variety of circumstances Power-up Brown-out Glitches

They can also provide a number of other services MAX807

ADuC7026pin-out

Basic System Bus Operation

Address Unidirectional from CPU

Data Bidirectional

Control /RS or /RD – output from CPU

Indicates a read operation in progress /WS or /WR – output from CPU

Indicates a write operation in progress /WAIT or /READY – input to CPU

Used by external device to signal that it is not able to complete transfer yet

I/O Port BasicsI/O subsystems allow the CPU to interact with the outside worldBasic GPIO pin requirements Configurable as input or output Can set value driven out on the pin Can read the current value on the pin

Configurable vs. multiplexed pinsUnconditional I/O The I/O device can accept or return data

without delayADuC7026

pin-out

MSI I/O PortsMedium Scale Integration (MSI) circuits are available to construct portsSimple byte input ports can be constructed from… Octal buffers Octal registers

Simple byte output ports can be constructed from octal registers

P Compatible I/O DevicesComplex I/O devices typically require more sophisticated interface and control logicP compatible I/O devices have the necessary logic built in to the device itself Interface designed to be reasonably compatible

with many microprocessor buses Need to add decoding/selection logic Example

Device controllers An organizational model commonly used to

interface to complex I/O devices (serial ports, LCDs, disk drives, etc.)

Generic model Example – Hitachi HD44780U LCD Controller

I/O Address DecodingI/O address decoding determines the logical location of the I/O device Isolated I/O Memory-mapped I/O

Input vs. output ports Same address does not guarantee

same function!

Exhaustive address decodingPartial address decoding

I/O Address Decoding (cont.)

Linear selection decoding A single address line is used as the

selection criteria for each device Can have n input/output devices in a

system with an n-bit address bus Hazards and opportunities Note that this idea has a very limited

application space!

Conditional I/OConditional vs. unconditional transfers I/O synchronization

Hardware examplePolling Overhead Flags / semaphores Wait loops Timeouts

Software exercise

ADuC7026 GPIO Ports

The ADuC7026 has 40 pins organized as 5 ports that can be used as digital GPIO All pins have multiple

functions in addition being able to be used as GPIO

The configuration selection is set through the GPxCON MMR.

ADuC7026 GPIO MMRsGPxCON Determine which of a

pin’s functions are active

This is the configuration column selection on the previous slide

aduc7026.inc

ADuC7026 GPIO MMRs (cont)

GPxPAR PARameters Controls whether or not

the internal pull-ups are used.

Does not apply to ports 2 and 4

ADuC7026 GPIO MMRs (cont)

GPxDAT Control the pin direction Set the output state Read the pin value Read the pin values that

were present at reset

ADuC7026 GPIO MMRs (cont)

GPxSET Write 1s to set the output value 0s have no effect

ADuC7026 GPIO MMRs (cont)

GPxCLR Write 1s to clear the output

value 0s have no effect

Wrapping UpHomework #4 will be due on Wednesday, October 29th

Reading for next week ADUC 53-60, 71-73, 75-79

ADuC7026 Clock Generation

ADuC7026 PLLCON

ADuC7026 Operating Modes

ADuC7026 POWCON

ADuC7026 Functional Block Diagram

MAX807

74HC540/541

74HC573

74HC574

AD7865

Generic Device Controller

control registers

TIMING ANDCONTROL

I/ODEVICE

A(n-1):0

D7:0

/CS

/WE

/OE

data registers

status registersCPU

CLOCK

address

data

/RD

/WR

chip select

HitachiHD44780ULCDController

Conditional I/O ExerciseWrite a subroutine to read data from an input device like the hardware example. Assume that the flag is a READY signal (active high). If the device does not become ready after 1 trillion polling attempts, return with R0 = -1, otherwise, return with the data in R0.

Conditional I/O ExampleD7:0

INPUTDEVICE

Q1

Q2

Q3

Q4

D1

D2

D3

D4

74HC574

CLK <

OC

Q5

Q6

Q7

Q8

D5

D6

D7

D8

A14A15A16

V CC

A0

A1

A2

Y0

Y1

Y2

Y3

74HC138

E1

E2

E3

Y4

Y5

Y6

Y7

/RD

D7Q D

CLK <

PR

CL

74HC7474HC125

vcc

/MS0

/MS0 base address = 0x1000 0000

aduc7026.inc

;GPIOGPIO_MMR_BASE EQU 0xFFFFF400GP0CON EQU 0x00GP1CON EQU 0x04GP2CON EQU 0x08GP3CON EQU 0x0CGP4CON EQU 0x10GP0DAT EQU 0x20GP0SET EQU 0x24GP0CLR EQU 0x28GP0PAR EQU 0x2C