ECE 331 – Digital System Design Electrical Characteristics of Logic Gates, Circuit Design Considerations, and Programmable Logic Devices.
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ECE 331 – Digital System Design
Electrical Characteristics of Logic Gates,Circuit Design Considerations,
andProgrammable Logic Devices
Electrical Characteristics of Logic Gates
Representing Logic Values
Electrical Characteristics
ECE 331 - Digital System Design 4
Voltage
Representing Logic Values
Logic 1
Undefined
VDD
V1,min
V0,max
VSS
Logic 0
supply voltage
ground
ECE 331 - Digital System Design 5
Voltage
Noise Margin
NMH = V
OH - V
IH
NML = V
IL - V
OL
Undefined
VDD
VOH
VIH
VIL
VOL
VSS
supply voltage
ground
ECE 331 - Digital System Design 6
Voltage Levels
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
VOH
, VOL
, VIH
, and VIL
are specified in the data sheet for the associated logic gate.
ECE 331 - Digital System Design 7
Fan-out
Electrical Characteristics
ECE 331 - Digital System Design 8
Fan-out
Fan-out is the number of gate inputs that can be properly driven by a single gate output
Current must flow between logic gates Current is limited by logic gate technology Current limits fan-out
DC Fan-out is the fan-out when the output is at steady-state.
Both high (1) and low (0) output states must be considered when implementing logic circuit design
Select worst-case as limit
ECE 331 - Digital System Design 9
x f
(a) Inverter that drives n other inverters
To inputs ofn other inverters
N 1
Fan-out
Fanout is determined by taking the ratio of the output current (IOH
, IOL
)of the driving device to the input current (I
IH, I
IL) of the load device(s).
The input and output currents are specified in the data sheet of the associated logic gates.
ECE 331 - Digital System Design 10
Interfacing between Logic Devices
Electrical Characteristics
ECE 331 - Digital System Design 11
Interfacing between Logic Devices
Devices in the same logic family have the same electrical characteristics.
Devices in different logic families often have different electrical characteristics.
In order to interface between logic devices Must consider the voltage levels of the driving
and load devices. Must consider the current sourced and sunk
by the driving and load devices, respectively.
ECE 331 - Digital System Design 12
Interfacing between Logic Devices
Voltage
The VOH
of the driving device must be greater than the V
IH of the load device.
The VOL
of the driving device must be less than the V
IL of the load device.
Noise Margin
Current The driving device sources current for one or more
load devices. Must consider the fan-out limit for the driving
device.
ECE 331 - Digital System Design 13
Interfacing between Logic Devices
Noise Margin High (NMH)
NMH = V
OH – V
IH
Noise Margin Low (NML)
NML = V
IL – V
OL
ECE 331 - Digital System Design 14
Example:
Determine the high and low noise margins when a 74LS00 NAND gate drives another 74LS00 NAND
gate.
Electrical Characteristics
ECE 331 - Digital System Design 15
ECE 331 - Digital System Design 16
Example: Noise Margin
From the 74LS00 data sheet:
VOH_min
= 2.7 V VOL_max
= 0.4 V
VIH_min
= 2.0 V VIL_max
= 0.8 V
High Noise Margin
NMH = 2.7 V – 2.0 V = 0.7 V
Low Noise Margin
NML = 0.8 V – 0.4 V = 0.4 V
ECE 331 - Digital System Design 17
Interfacing between Logic Devices
Low-state Fanout =
Floor[ IOL_max
(driver) / IIL_max
(load) ]
High-state Fanout =
Floor[ IOH_max
(driver) / IIH_max
(load) ]
Design the logic circuit based on the minimum of the two fan-out limits.
ECE 331 - Digital System Design 18
Interfacing between Logic Devices
Exceeding fanout limits leads to Increase in output-low voltage (V
OL)
And possibly the wrong logic state
Decrease in output-high voltage (VOH
) And possibly the wrong logic state
Increase in temperature And possible destruction of the circuit / device
Increase in propagation delay
ECE 331 - Digital System Design 19
for n = 1 V f
for n = 4 V f
V DD
Gnd
Time0
(c) Propagation times for different values of n
Effect of Fan-out on Propagation Delay
ECE 331 - Digital System Design 20
Example:
Find the fan-out limit of a 74LS00 NAND gate when driving one or more NAND gates on the
same chip.
Electrical Characteristics
ECE 331 - Digital System Design 21
ECE 331 - Digital System Design 22
Example: Fanout Limit
From the 74LS00 data sheet:
IOH_max
= - 0.4 mA IOL_max
= 8.0 mA
IIH_max
= 20 A IIL_max
= - 0.4 mA
Low-state fanout = Floor[ 8.0 mA / 0.4 mA ] = 20
High-state fanout = Floor[ 0.4 mA / 20 A ] = 20
ECE 331 - Digital System Design 23
Example:
Determine the noise margins and fanout limit for a 74LS00 NAND gate when driving one or more
74HC00 NAND gates.
Electrical Characteristics
ECE 331 - Digital System Design 24
ECE 331 - Digital System Design 25
Example: Noise Margin From the 74LS00 data sheet:
VOH_min
= 2.7 V VOL_max
= 0.4 V
From the 74HC00 data sheet:
VIH_min
= 3.15 V VIL_max
= 1.35 V
High Noise Margin
NMH = 2.7 V – 3.15 V = - 0.45 V
Low Noise Margin
NML = 1.35 V – 0.4 V = 0.95 V
ECE 331 - Digital System Design 26
Example: Fanout Limit
From the 74LS00 data sheet:
IOH_max
= - 0.4 mA IOL_max
= 8.0 mA
From the 74HC00 data sheet:
IIH_max
= IIL_max
= +/- 1 A
Low-state fanout = Floor[ 8.0 mA / 1 A ] = 8000
High-state fanout = Floor[ 0.4 mA / 1 A ] = 400
ECE 331 - Digital System Design 27
Programmable Logic Devices
ECE 331 - Digital System Design 28
Programmable Logic Device
Programmable Logic Array (PLA) Consists of a set of AND gates that feeds a
set of OR gates. Realizes a Boolean expression using the
Sum-of-Products (SOP) form. Programmable Array Logic (PAL)
Similar to the PLA However, only the AND plane is
programmable. The OR plane is fixed.
ECE 331 - Digital System Design 29f1
P1
P2
f2
x1 x2 x3
OR plane
Programmable
AND plane
connections
P3
P4
Programmable Logic Array
ECE 331 - Digital System Design 30
f 1
P 1
P 2
f 2
x 1 x 2 x 3
OR plane
AND plane
P 3
P 4
Programmable Logic Array
ECE 331 - Digital System Design 31
f 1
P 1
P 2
f 2
x 1 x 2 x 3
AND plane
P 3
P 4
Programmable Array Logic
ECE 331 - Digital System Design 32
Programmable Logic Devices Complex Programmable Logic Device (CPLD)
Comprises multiple circuit blocks on a single chip, with internal wiring resources to connect the circuit blocks.
Each circuit block is similar to a PLA or PAL. Field Programmable Gate Array (FPGA)
Supports implementation of relatively large logic circuits.
Does not contain AND or OR planes. Provides logic blocks for the implementation
of the required functions.
ECE 331 - Digital System Design 33
PAL-likeblock
I/O
blo
ck PAL-like
block I/O
block
PAL-likeblock
I/O
blo
ck
PAL-likeblock
I/O block
Interconnection wires
CPLD
ECE 331 - Digital System Design 34
D Q
D Q
D Q
PAL-like block (details not shown)
PAL-like block
CPLD
ECE 331 - Digital System Design 35
FPGA
ECE 331 - Digital System Design 36
(a) Circuit for a two-input LUT
x 1
x 2
f
0/1
0/1
0/1
0/1
0
0
1
1
0
1
0
1
1
0
0
1
x 1 x 2
(b) f 1 x 1 x 2 x 1 x 2 + =
(c) Storage cell contents in the LUT
x 1
x 2
1
0
0
1
f 1
f 1
FPGA Logic Block
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