Dsd Lab Report
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DSD Lab Report
SUBMITTED BY AVINASH T(M130122EC) , JINESH K B(M130121EC)
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Table of Contents 1
MODULE I STRUCTURAL MODELING 2 1. HALF ADDER AND HALF SUBTRACTOR 3 2. FULL ADDER AND FULL SUBTRACTOR 8
3.4 BIT BINARY ADDER 15 4. SYNCHRONOUS COUNTER (UP, DOWN, UP/DOWN ) 18
MODULE II DATA FLOW MODELING 27 1. HALF ADDER 28 2. FULL ADDER 31
3. COMPARATOR (4 BIT) 34 4. SHIFT REGISTER 16 BIT AND 64 BIT) 37 5. MULTIPLEXER WITH TRISTATING 42 6. DECODER WITH TRISTATING) 45
MODULE III BEHAVIORAL MODELING 48 1. 4 BIT BINARY COUNTER 49 2. UP/DOWN DECADE COUNTER 52
3. BCD SUBTRACTOR AND ADDER 55 4. D FLIP FLOP 60
5. T FLIP FLOP 63 6. JK FLIP FLOP 66
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MODULE I :STRUCTURAL MODELING
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1.HALF ADDER AND HALF SUBTRACTER
AIM a) To design half adder in structural model. b) To design half subtractor in structural model.
THEORY a) Half adder is designed using one 2 input XOR gate and one 2 input AND gate. The design equation is
obtained by solving K-map and is given by
SUM = A B CARRY = AB
b) Half subtractor is designed using one 2 input XOR gate, one 2 input and gate and one NOT gate. The design equation is given by
DIFFERENCE = A B BORROW = A
TRUTH TABLE
HALF ADDER HALF SUBTRACTOR INPUT OUTPUT INPUT OUTPUT
A B SUM CARRY A B DIFFERENCE BORROW 0 0 0 0 0 0 0 0
0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 0
SCHEMATIC DIAGRAM
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PROGRAM
a. HALF ADDER
VHDL CODE :
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HALF_ADDER IS PORT ( A,B : IN STD_LOGIC; SUM,CARRY : OUT STD_LOGIC); END HALF_ADDER;
ARCHITECTURE BEHAVIORAL OF HALF_ADDER IS
COMPONENT AND_GATE IS PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT;
COMPONENT XOR_GATE IS PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT;
BEGIN
A0: XOR_GATE PORT MAP(A,B,SUM); A1: AND_GATE PORT MAP (A,B,CARRY);
END BEHAVIORAL;
TEST BENCH
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_HALF_ADDER IS END TB_HALF_ADDER;
ARCHITECTURE BEHAVIOR OF TB_HALF_ADDER IS
COMPONENT HALF_ADDER PORT(A : IN STD_LOGIC; B : IN STD_LOGIC; SUM : OUT STD_LOGIC; CARRY : OUT STD_LOGIC ); END COMPONENT;
SIGNAL A : STD_LOGIC := '0'; SIGNAL B : STD_LOGIC := '0';
SIGNAL SUM : STD_LOGIC; SIGNAL CARRY : STD_LOGIC;
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BEGIN
UUT: HALF_ADDER PORT MAP ( A => A, B => B, SUM => SUM, CARRY => CARRY );
STIM_PROC: PROCESS
BEGIN
A
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PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT;
COMPONENT XOR_GATE IS PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT;
SIGNAL BBAR : STD_LOGIC;
BEGIN
A0 : NOT_GATE PORT MAP(B,BBAR); A1 : AND_GATE PORT MAP(A,BBAR,BORROW); A2 : XOR_GATE PORT MAP(A,B,DIFFERENCE);
END BEHAVIORAL;
TEST BENCH
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_HALF_SUBTRACTOR IS END TB_HALF_SUBTRACTOR;
ARCHITECTURE BEHAVIOR OF TB_HALF_SUBTRACTOR IS COMPONENT HALF_SUBTRACTOR PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; DIFFERENCE : OUT STD_LOGIC; BORROW : OUT STD_LOGIC ); END COMPONENT;
SIGNAL A : STD_LOGIC := '0'; SIGNAL B : STD_LOGIC := '0';
SIGNAL DIFFERENCE : STD_LOGIC; SIGNAL BORROW : STD_LOGIC;
BEGIN
UUT: HALF_SUBTRACTOR PORT MAP ( A => A, B => B, DIFFERENCE => DIFFERENCE, BORROW => BORROW );
STIM_PROC: PROCESS BEGIN A
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OUTPUT
COMPNENTS USED
XOR_GATE AND_GATE NOTGATE LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XOR_GATE IS PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END AND_GATE;
ARCHITECTURE BEHAVIORAL OF XOR_GATE IS
BEGIN
Y
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2.FULL ADDER AND FULL SUBTRACTOR
AIM a. To design full adder using structural model. b. To design full subtractor using structural model
THEORY
a. A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a SUM and a CARRY output.
SUM= A B Cin CARRY= A B +Cin B+Cin A
Here full adder is realised using two half adders and an OR gate.
b. A full subtractor circuit is an arithmetic circuit block that can be used to subtract three bits to produce a DIFFERENCE and a BORROW output
DIFFERENCE= A B Bin BORROW = + +
Here full subtractor is realised using two half ubtractors and an OR gate.
TRUTH TABLE
FULL ADDER FULL SUBTRACTOR INPUT OUTPUT
INPUT OUTPUT A B Cin Sum Carry A B Bin Diff. Borrow 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1
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SCHEMATIC DIAGRAM
a. Full adder
b. Full subtractor
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PROGRAM
a. FULL ADDER
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FULLADDER IS
PORT ( A,B,CIN : IN STD_LOGIC; SUM,CARRY : OUT STD_LOGIC);
END FULLADDER;
ARCHITECTURE BEHAVIORAL OF FULLADDER IS
COMPONENT HALF_ADDER IS
PORT ( A,B : IN STD_LOGIC; SUM,CARRY : OUT STD_LOGIC);
END COMPONENT;
COMPONENT ORGATE IS
PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC);
END COMPONENT;
SIGNAL S1,S2,S3 :STD_LOGIC;
BEGIN
HA0 : COMPONENT HALF_ADDER PORT MAP(A,B,S1,S2); HA1 : COMPONENT HALF_ADDER PORT MAP (S1,CIN,SUM,S3); OR0 : COMPONENT ORGATE PORT MAP(S2,S3,CARRY);
END BEHAVIORAL;
TEST BENCH
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_FULLADDER IS END TB_FULLADDER;
ARCHITECTURE BEHAVIOR OF TB_FULLADDER IS
COMPONENT FULLADDER
PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; CIN : IN STD_LOGIC; SUM : OUT STD_LOGIC; CARRY : OUT STD_LOGIC );
END COMPONENT;
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SIGNAL A : STD_LOGIC := '0'; SIGNAL B : STD_LOGIC := '0'; SIGNAL CIN : STD_LOGIC := '0';
SIGNAL SUM : STD_LOGIC; SIGNAL CARRY : STD_LOGIC;
BEGIN
UUT: FULLADDER PORT MAP ( A => A, B => B, CIN => CIN, SUM => SUM, CARRY => CARRY );
STIM_PROC: PROCESS
BEGIN
A
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COMPONENT HALF_SUBTRACTOR IS PORT ( A,B : IN STD_LOGIC; DIFFERENCE,BORROW : OUT STD_LOGIC); END COMPONENT;
COMPONENT ORGATE IS PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT;
SIGNAL S1,S2,S3 :STD_LOGIC;
BEGIN HS0 : COMPONENT HALF_SUBTRACTOR PORT MAP(A,B,S1,S2); HS1 : COMPONENT HALF_SUBTRACTOR PORT MAP (S1,BIN,DIFFERENCE,S3); OR0 : COMPONENT ORGATE PORT MAP(S2,S3,BORROW);
END BEHAVIORAL;
TEST BENCH
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_FULLSUBTRACTOR IS END TB_FULLSUBTRACTOR;
ARCHITECTURE BEHAVIOR OF TB_FULLSUBTRACTOR IS
COMPONENT FULLSUBTRACTOR PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; BIN : IN STD_LOGIC; DIFFERENCE : OUT STD_LOGIC; BORROW : OUT STD_LOGIC ); END COMPONENT;
SIGNAL A : STD_LOGIC := '0'; SIGNAL B : STD_LOGIC := '0'; SIGNAL BIN : STD_LOGIC := '0';
SIGNAL DIFFERENCE : STD_LOGIC; SIGNAL BORROW : STD_LOGIC;
BEGIN
UUT: FULLSUBTRACTOR PORT MAP ( A => A,
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B => B, BIN => BIN, DIFFERENCE => DIFFERENCE, BORROW => BORROW );
STIM_PROC: PROCESS BEGIN A
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RESULT
Implemented full adder and full subtractor in structural model and verified the outputs.
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3. 4 BIT BINARY ADDER
AIM To design a 4 bit binary adder in structural model.
THEORY
A four bit binary adder is implemented using four full adders cascaded in parallel such that carry out of each full adder is the carry in of succeeding full adder.Thus each full adder will add one bit of both input along with the carry of previous bit to give a four bit sum and one bit carry out.
SCHEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FOUR_BIT_BINARY_ADDER IS PORT ( A,B : IN STD_LOGIC_VECTOR (3 DOWNTO 0); CIN : IN STD_LOGIC; SUM : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); COUT : OUT STD_LOGIC); END FOUR_BIT_BINARY_ADDER;
ARCHITECTURE BEHAVIORAL OF FOUR_BIT_BINARY_ADDER IS
COMPONENT FULLADDER IS PORT ( A,B,CIN : IN STD_LOGIC; SUM,CARRY : OUT STD_LOGIC);
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END COMPONENT;
SIGNAL S:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN FA0 : COMPONENT FULLADDER PORT MAP(A(0),B(0),CIN,SUM(0),S(0)); FA1 : COMPONENT FULLADDER PORT MAP (A(1),B(1),S(0),SUM(1),S(1)); FA2 : COMPONENT FULLADDER PORT MAP(A(2),B(2),S(1),SUM(2),S(2)); FA3 : COMPONENT FULLADDER PORT MAP (A(3),B(3),S(2),SUM(3),S(3)); COUT '0'); SIGNAL B : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL CIN : STD_LOGIC := '0';
SIGNAL SUM : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL COUT : STD_LOGIC;
BEGIN UUT: FOUR_BIT_BINARY_ADDER PORT MAP ( A => A, B => B, CIN => CIN, SUM => SUM, COUT => COUT );
STIM_PROC: PROCESS BEGIN
A
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OUTPUT
RESULT Implemented 4 bit binary adder in structural model and verified the output.
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4. SYNCHRONOUS COUNTER(UP,DOWN,UP/DOWN)
AIM i. To design synchronous up counter using structural model.
ii. To design synchronous down counter using structural model. iii. To design synchronous up/down counter using structural model.
THEORY
A 4 bit synchronous counter is designed using 4 T flip flops .the design equation for up and down counters are given by
i. SYNCHRONOUS UP COUNTER
T0 = 1 T1 = Q0 T2=Q0Q1 T3=Q0Q1Q2
Where
T0 T1 T2 T3 are the inputs of stage 0 to 3 and Q0 Q1 Q2 are the outputs of respective stages .
To implement this in structural mode it requires 4 T flipflops and 2 AND gates.
ii. SYNCHRONOUS DOWN COUNTER
T0 = 1 T1 = 0 T2=01 T3=012
Where
T0 T1 T2 T3 are the inputs of stage 0 to 3 and Q0 Q1 Q2 are the outputs of respective stages .
To implement this in structural mode it requires 4 T flipflops and 2 AND gates.
iii. SYNCHRONOUS UP/DOWN COUNTER
This circuit consist of an additional input mode to select whether up or down counter.design equation is given by
T0 = 1 T1 =Q0.MODE +0. T2= Q0Q1.MODE+ 01 T3= Q0Q1Q2.MODE+ 012 .
When mode=1,it works as up counter. Mode=0,it works as down counter.
To implement this in structural mode it requires 4 T flipflops , 5 AND gates,3 OR gates and 1 NOT gate.
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SCHEMATIC DIAGRAM
VHDL CODE LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SYN_UP IS PORT ( CLK : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END SYN_UP;
ARCHITECTURE BEHAVIORAL OF SYN_UP IS
COMPONENT TFF PORT(T,CLK :IN STD_LOGIC; Q,QBAR: OUT STD_LOGIC); END COMPONENT;
COMPONENT AND_GATE IS PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT;
SIGNAL S,N,M:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
T0 : TFF PORT MAP('1',CLK,S(0),M(0)); T1 : TFF PORT MAP(N(0),CLK,S(1),M(1)); T2 : TFF PORT MAP(N(1),CLK,S(2),M(2)); T3 : TFF PORT MAP(N(2),CLK,S(3),M(3));
N(0)
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TEST BENCH
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_UP_COUNTER IS END TB_UP_COUNTER;
ARCHITECTURE BEHAVIOR OF TB_UP_COUNTER IS
COMPONENT SYN_UP PORT( CLK : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN UUT: SYN_UP PORT MAP ( CLK => CLK, Q => Q );
CLK_PROCESS :PROCESS BEGIN CLK
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SYNCHRONOUS DOWN COUNTER
SCHEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SYN_DOWN IS PORT ( CLK : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END SYN_DOWN;
ARCHITECTURE BEHAVIORAL OF SYN_DOWN IS
COMPONENT TFF PORT(T,CLK :IN STD_LOGIC; Q,QBAR: OUT STD_LOGIC); END COMPONENT;
COMPONENT AND_GATE IS PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT;
SIGNAL S,N,M:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
T0 : TFF PORT MAP('1',CLK,S(0),M(0)); T1 : TFF PORT MAP(N(0),CLK,S(1),M(1)); T2 : TFF PORT MAP(N(1),CLK,S(2),M(2)); T3 : TFF PORT MAP(N(2),CLK,S(3),M(3));
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N(0) Q );
CLK_PROCESS :PROCESS BEGIN CLK
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OUTPUT
iii. SYNCHRONOUS UP/DOWN COUNTER
SCHEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SYN_UP_DOWN IS PORT ( MODE,CLK : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END SYN_UP_DOWN;
ARCHITECTURE BEHAVIORAL OF SYN_UP_DOWN IS
COMPONENT TFF PORT(T,CLK :IN STD_LOGIC; Q,QBAR: OUT STD_LOGIC); END COMPONENT;
COMPONENT NOTGATE IS PORT ( A : IN STD_LOGIC; Y : OUT STD_LOGIC);
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END COMPONENT;
COMPONENT AND_GATE IS PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT;
COMPONENT OR_GATE IS PORT ( A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT;
SIGNAL MODEBAR : STD_LOGIC; SIGNAL S,N,M,U,D:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
N0 : NOTGATE PORT MAP(MODE,MODEBAR);
T0 : TFF PORT MAP('1',CLK,S(0),M(0)); T1 : TFF PORT MAP(N(0),CLK,S(1),M(1)); T2 : TFF PORT MAP(N(1),CLK,S(2),M(2)); T3 : TFF PORT MAP(N(2),CLK,S(3),M(3));
A0: AND_GATE PORT MAP(S(0),MODE,U(0)); A1: AND_GATE PORT MAP(U(0),S(1),U(1)); A2: AND_GATE PORT MAP (S(2),U(1),U(2));
A3: AND_GATE PORT MAP(MODEBAR,M(0),D(0)); A4: AND_GATE PORT MAP(D(0),M(1),D(1)); A5: AND_GATE PORT MAP (M(2),D(1),D(2));
O0:OR_GATE PORT MAP(D(0),U(0),N(0)); O1:OR_GATE PORT MAP(D(1),U(1),N(1)); O2:OR_GATE PORT MAP(D(2),U(2),N(2));
Q
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SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
UUT: SYN_UP_DOWN PORT MAP ( MODE => MODE, CLK => CLK, Q => Q );
CLK_PROCESS :PROCESS BEGIN CLK
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PROCESS(CLK)
BEGIN IF RISING_EDGE(CLK) THEN IF(T='1') THEN S
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MODULE II :DATA FLOW MODELING
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1.HALF ADDER
AIM To simulate a half adder in data flow model
THEORY Half adder adds 2 bits and produce a sum and carry. The design equation is obtained by solving K-map and
is given by
SUM = A B CARRY = AB
TRUTH TABLE
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
SCHEMATIC DIAGRAM
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VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HALF_ADDER IS PORT ( A,B : IN STD_LOGIC; SUM,CARRY : OUT STD_LOGIC); END HALF_ADDER;
ARCHITECTURE DATAFLOW OF HALF_ADDER IS BEGIN SUM B, SUM => SUM, CARRY => CARRY );
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STIM_PROC: PROCESS BEGIN A
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2.FULL ADDER
AIM To simulate a full adder in data flow model
THEORY A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a SUM and a CARRY output.
SUM= A B Cin CARRY= A B +Cin B+Cin A
TRUTH TABLE
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SCEMATIC DIAGRAM
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VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FULL_ADDER IS PORT ( A,B,CIN : IN STD_LOGIC; SUM,COUT : OUT STD_LOGIC); END FULL_ADDER;
ARCHITECTUR DATAFLOW OF FULL_ADDER IS
BEGIN SUM B, CIN => CIN, SUM => SUM, COUT => COUT );
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STIM_PROC: PROCESS
BEGIN
A
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3.COMPARATOR (4 BIT) AIM
To simulate a comparator in data flow model.
THEORY A comparator circuit compares two numbers and if they are equal the output EQUAL is made to one and
GREATER and LESS set to 0.If the first number is greater than second number then GREATER is set to one and rest to 0.Similerly if first number is less than second number LESS is set to1.
SCEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COMPARATOR_4BIT IS PORT ( A,B : IN STD_LOGIC_VECTOR (3 DOWNTO 0); EQUAL,LESS,GREATER : OUT STD_LOGIC); END COMPARATOR_4BIT;
ARCHITECTURE DATAFLOW OF COMPARATOR_4BIT IS BEGIN EQUAL
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LESS '0');
SIGNAL EQUAL : STD_LOGIC; SIGNAL LESS : STD_LOGIC; SIGNAL GREATER : STD_LOGIC;
BEGIN
UUT: COMPARATOR_4BIT PORT MAP ( A => A, B => B, EQUAL => EQUAL, LESS => LESS, GREATER => GREATER );
STIM_PROC: PROCESS BEGIN A
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OUTPUT
RESULT Implemented 4 bit comparator in data flow model and verified the output.
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4. SHIFT REGISTER 16 BIT AND 64 BIT
AIM To implement 16 bit and 64 bit shift registers in dataflow model
THEORY
A shift register shifts the bits after every clock pulse. They are mainly of 4 types SISO (Serial In Serial Out) , SIPO(Serial In Parallel Out), PISO(Parallel In Serial Out), PIPO(Parallel In Parallel Out). In SISO there will be one bit input and one bit output the applied input will be available at the output after certain number of clock cycle (size of register).
a)16 BIT SHIFT REGISTER (SISO)
SCHEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHIFT_REGISTER_SISO IS PORT ( A, CLK : IN STD_LOGIC; Y : OUT STD_LOGIC); END SHIFT_REGISTER_SISO;
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ARCHITECTURE DATAFLOW OF SHIFT_REGISTER_SISO IS SIGNAL N : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN N
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STIM_PROC: PROCESS BEGIN
A
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VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHIFT_REGISTER_SISO IS PORT ( A,CLK : IN STD_LOGIC; Y : OUT STD_LOGIC); END SHIFT_REGISTER_SISO;
ARCHITECTURE DATAFLOW OF SHIFT_REGISTER_SISO IS SIGNAL N : STD_LOGIC_VECTOR(64 DOWNTO 0); BEGIN
N
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CLK_PROCESS :PROCESS BEGIN CLK
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5. MULTIPLEXER WITH TRISTATING
AIM To simulate a multiplexer(4X1) in dataflow model.
THEORY A mux selects one of the inputs and route to the output according to the select line values.The truth table below
describes its operation.
ENABLE
INPUT SELECT LINE
S(1) S(0)
OUTPUT
1
A3-A0
00 A(0) 1 01 A(1) 1 10 A(2) 1 11 A(3) 0 XX Z
SCHEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX_TRISTATE IS PORT ( A : IN STD_LOGIC_VECTOR (3 DOWNTO 0); S : IN STD_LOGIC_VECTOR (1 DOWNTO 0); ENABLE : IN STD_LOGIC; O : OUT STD_LOGIC); END MUX_TRISTATE;
ARCHITECTURE DATAFLOW OF MUX_TRISTATE IS BEGIN
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O '0'); SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL ENABLE : STD_LOGIC := '0';
SIGNAL O : STD_LOGIC;
BEGIN UUT: MUX_TRISTATE PORT MAP ( A => A, S => S, ENABLE => ENABLE, O => O );
STIM_PROC: PROCESS BEGIN
A
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OUTPUT
RESULT Implemented 4X1 mux with tri-state in data flow model and varified the output.
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6. DECODER WITH TRISTATING(2:4 DECODER)
AIM To design a 2X4 decoder in data flow model with High Impedance state
THEORY
A decoder decodes the input. Generally according to the input one of the output goes high and all other outputs are zeros. The truth table below describes its operation.
ENABLE
INPUT A(1) A(0)
OUTPUT
1 00 0001 1 01 0010 1 10 0100 1 11 1000 0 XX Z
SCHEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODER2_4 IS PORT ( A : IN STD_LOGIC_VECTOR (1 DOWNTO 0); ENABLE : IN STD_LOGIC;
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Y : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END DECODER2_4;
ARCHITECTURE DATAFLOW OF DECODER2_4 IS BEGIN Y '0'); SIGNAL ENABLE : STD_LOGIC := '0';
SIGNAL Y : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN UUT: DECODER2_4 PORT MAP ( A => A, ENABLE => ENABLE, Y => Y );
STIM_PROC: PROCESS BEGIN A
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OUTPUT
RESULT Implemented 2X4 decoder with tri-state in data flow model and verified the output.
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MODULE III: BEHAVIORAL MODELING
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1.FOUR BIT BINARY COUNTER
AIM To implement 4 bit binary adder in behavioral model.
THEORY A 4 bit up counter counts from 0000 to 1111(total 16 states) .When the preset input is high then it sets all the
output bits high (1111) and when clear input is high it clears all the output bits (0000).
SCHEMATIC DIAGRAM
VHDL CODE LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FOUR_BIT_UP_COUNTER IS PORT ( CLK,CLR,PR : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END FOUR_BIT_UP_COUNTER;
ARCHITECTURE BEHAVIORAL OF FOUR_BIT_UP_COUNTER IS
SIGNAL S:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
Q
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BEGIN IF(CLK='1' AND CLK'EVENT) THEN IF(CLR='1' AND PR='0') THEN S PR, Q => Q );
CLK_PROCESS :PROCESS BEGIN CLK
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CLR
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2. UP/DOWN DECADE COUNTER
AIM To simulate a UP/DOWN decade in behavioral model.
THEORY
An up/down decade counter is a mod-10 counter which counts from 0 to 9 (up) or 9 to 0(down) on each clock pulse.when mode input is high then it will work as a up counter and a down counter when mode is logic low.
SCHEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECADE_COUNTER IS
PORT ( CLK,MODE: IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END DECADE_COUNTER;
ARCHITECTURE BEHAVIORAL OF DECADE_COUNTER IS
BEGIN PROCESS(CLK)
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VARIABLE S:STD_LOGIC_VECTOR(3 DOWNTO 0):="1111"; VARIABLE W:STD_LOGIC_VECTOR(3 DOWNTO 0):="1010";
BEGIN
IF(CLK='1' AND CLK'EVENT) THEN IF (MODE='1') THEN S:=S+'1'; IF(S="1010") THEN S:="0000"; END IF;
Q
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CONSTANT CLK_PERIOD : TIME := 5 NS;
BEGIN
UUT: DECADE_COUNTER PORT MAP ( CLK => CLK, MODE => MODE, Q => Q );
CLK_PROCESS :PROCESS BEGIN
CLK
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3. BCD ADDER AND SUBTRACTOR
AIM To implement a BCD adder subtractor and in behavioural model.
THEORY BCD adder is used to add two BCD numbers.The valid BCD numbers are from 0(0000) to 9(1001).The result should be converted to a valid format if it exceeds 9. Same for subtractor there is an additional output borrow If borrow=1 then the result is a negative number If borrow=0 then the result is a positive number .
a. BCD ADDER
SCHEMATIC
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BCD_ADDER IS PORT ( A,B : IN STD_LOGIC_VECTOR (3 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END BCD_ADDER;
ARCHITECTURE BEHAVIORAL OF BCD_ADDER IS BEGIN PROCESS(A,B)
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VARIABLE TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN TEMP := ("0000" & A) +("0000" & B);
IF(TEMP >"00001001") THEN TEMP(3 DOWNTO 0):= TEMP(3 DOWNTO 0)-"1010"; TEMP(7 DOWNTO 4):="0001"; END IF; Y '0'); SIGNAL B : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL Y : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
UUT: BCD_ADDER PORT MAP ( A => A, B => B, Y => Y );
STIM_PROC: PROCESS BEGIN
A
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WAVE FORM
b. BCD SUBTRACTOR
SCHEMATIC DIAGRAM
If borrow=1 then the result is a negative number
If borrow=0 then the result is a positive number
VHDL CODE:
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BCD_SUBTRACTOR IS PORT ( A,B : IN STD_LOGIC_VECTOR (3 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); BORROW:OUT STD_LOGIC);
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END BCD_SUBTRACTOR ;
ARCHITECTURE BEHAVIORAL OF BCD_SUBTRACTOR IS BEGIN PROCESS(A,B) VARIABLE TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF (A>=B) THEN TEMP := A-B; BORROWA) THEN TEMP := B-A; BORROW '0');
SIGNAL Y : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BORROW : STD_LOGIC;
BEGIN UUT: BCD_SUBTRACTOR PORT MAP ( A => A, B => B, Y => Y, BORROW => BORROW );
STIM_PROC: PROCESS BEGIN
A
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WAIT; END PROCESS;
END;
WAVE FORM
RESULT
Implemented BCD adder and subtractor in behavioral model and verified the output
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4 D-FLIP FLOP
AIM To implement a D- FLIPFLOP in behavioural model.
THEORY A D flip flop is one in which the output follows the input.If the clear signal is high the output goes low
irrespective of the input and also if the preset is high output goes to logic high.
TRUTH TABLE
CLR PR D Q 0 0 0 0
0 0 1 1
1 0 X 0
0 1 X 1
SCHEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY D_FF IS PORT ( D,CLK,PR,CLR : IN STD_LOGIC; Q ,QBAR: OUT STD_LOGIC); END D_FF;
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ARCHITECTURE BEHAVIORAL OF D_FF IS SIGNAL S: STD_LOGIC :='0'; BEGIN Q
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-- CLOCK PERIOD DEFINITIONS CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
-- INSTANTIATE THE UNIT UNDER TEST (UUT) UUT: D_FF PORT MAP ( D => D, CLK => CLK, PR => PR, CLR => CLR, Q => Q, QBAR => QBAR );
-- CLOCK PROCESS DEFINITIONS CLK_PROCESS :PROCESS BEGIN CLK
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5 T-FLIP FLOP
AIM To implement a T- FLIPFLOP in behavioural model.
THEORY A T flip flop is one in which the output toggles if input is logic 1.output remains the same if
input is logic 0.
TRUTH TABLE
T Qn Qn+1 0 0 0
0 1 1
1 0 1
1 1 0
SCHEMATIC DIAGRAM
VHDL CODE
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY T_FF IS PORT ( T,CLK,PR,CLR : IN STD_LOGIC; Q : OUT STD_LOGIC; QBAR: OUT STD_LOGIC ); END T_FF;
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ARCHITECTURE BEHAVIORAL OF T_FF IS SIGNAL S: STD_LOGIC:='0';
BEGIN Q
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BEGIN
UUT: T_FF PORT MAP ( T => T, CLK => CLK, PR => PR, CLR => CLR, Q => Q, QBAR => QBAR );
CLK_PROCESS :PROCESS BEGIN CLK
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6 . JK FLIP FLOP
AIM To implement a JK- FLIPFLOP in behavioural model.
THEORY The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1
condition as a "flip" or toggle command.The characteristic equation of the JK flip-flop is
TRUTH TABLE
SCHEMATIC DIAGRAM
J K Qn+1 0 0 Qn 0 1 0
1 0 1
1 1
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VHDL CODE
ENTITY JK_FF IS
PORT ( J,K,CLK,CLR,PR : IN STD_LOGIC; Q,QBAR : OUT STD_LOGIC);
END JK_FF;
ARCHITECTURE BEHAVIORAL OF JK_FF IS
SIGNAL S:STD_LOGIC:='0'; SIGNAL A:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
Q
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TEST BENCH:
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_JK_FF IS END TB_JK_FF;
ARCHITECTURE BEHAVIOR OF TB_JK_FF IS
COMPONENT JK_FF
PORT( J : IN STD_LOGIC; K : IN STD_LOGIC; CLK : IN STD_LOGIC; CLR : IN STD_LOGIC; PR : IN STD_LOGIC; Q : OUT STD_LOGIC; QBAR : OUT STD_LOGIC );
END COMPONENT;
SIGNAL J : STD_LOGIC := '0'; SIGNAL K : STD_LOGIC := '0'; SIGNAL CLK : STD_LOGIC := '0'; SIGNAL CLR : STD_LOGIC := '0'; SIGNAL PR : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC; SIGNAL QBAR : STD_LOGIC;
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
UUT: JK_FF PORT MAP ( J => J, K => K, CLK => CLK, CLR => CLR, PR => PR, Q => Q, QBAR => QBAR );
CLK_PROCESS :PROCESS
BEGIN
CLK
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WAIT FOR CLK_PERIOD/2; CLK
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