Dayle Kotturi Lehman Review dayle@slac.stanford.edu May 10-12, 2005 LCLS Timing Outline Scope SLC Master Pattern Generator Introducing the PNET VME receiver.
Post on 02-Jan-2016
214 Views
Preview:
Transcript
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
LCLS TimingOutline
Scope SLC Master Pattern GeneratorIntroducing the PNET VME receiver Status of the PNET VME receiverSystem diagramTiming pulse to pulseLCLS MPGEvent Generator and Event ReceiverCostsConclusions
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
Scope
LCLS timing system is used to transmit a fiducial 360 Hz signal to all triggered devices in LCLSSystem requirements (speed and content) are known: receive 128 bit PNET data at 360 Hz; append add’l info; operate at 120 HzThe component parts are known: PNET VME receiver, EVG-200 and EVR-200The interfaces are being defined
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
SLC Master Pattern Generator
The one and only SLC Master Pattern Generator (MPG)
Takes as input: 360 Hz fiducial from SLC PDU is the signal to create a new PNET buffer Performs tasks:
creates PNET buffersresponds to faults
Outputs PNET buffers to all micros and PNET VME receiver on the next 1/360 s fiducial
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
Introducing the PNET VME receiver
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
Status of the VME PNET receiver
Hardware prototype is finished (1 instance)
Board is 3 slots wide to accommodate on board cable modem interface to PNET
Engineering Design Specification doc written
Driver and device support (bi, mbbiDirect to access each variable in PNETbuffer) written. Compiled only for Synergy PPC running RTEMS 4.6.2
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
System Diagram
LCLS MPS(new)
MKSU MPS
MPG
SCP
EVG
EVR
PNET
Arrives within 2.7 ms(1-360 Hz beam pulse)
eg rate limit
PNET
Arrives within 24.9 ms(3-120 Hz beam pulses)
EVR
Bit pattern of instructions for current beam pulse + fault indicators
CPU
CPU
LCLS MPG “LE20”
SLC-AWARE IOCSLC-AWARE IOC
CPU
Slow control (eg setup commands)
Mode of running (eg rate limit)
LCLS beam loss
monitor(new)
PEP beam loss
monitor(existing)
LINAC vacuum interlock (existing)
Within 1/360 s
LCLS vacuum (new)
LCLS power
supplies (new)
Orbit tolerances
Turn on (to drive beam to dump)/clear Kicker
Turn off/clear
Laser
Kicker status
Laser status
RF 119 MHz clock with
360 Hz fiducial(existing)
Gated data acquisition application (eg. BPM)
Gated data acquisition application (eg. BPM)
BPM
hw
BPM
hw
Needs to be added so that LCLS vacuum leak detection shuts off klystron
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
Micro timing pulse to pulse
Time in milliseconds (the 360 Hz fiducial)
0.00 2.78
SLC PDU
MPG ISR
Each micro
4 "one second’s worth” of PNET buffers are kept in 4 separate arrays
128 µs + several µs for speed of light travel
BGRP: PEPII
sends intr3 to MPG
saves PB2 to current full sec buffer
receives intr3
reads fault bits from camac
if BCS fault bit asserted, ISR sets BCSFAULT modifier bit in PB2 (created last intr)
finds which BGRP to execute
sends (modified) PB2
based on fault bits and BGRP var (from operator),find MGRP
execute MGRP which creates PB3
is interrupted by the arrival of PB2
xlate 5-bit base beamcode + modifier bits in PB2 into 8 bit beamcode and set up camac FC F19A10 so that “2/360s early” cmds in PB2 will happen next fiducial
set up camac FC F19A9 so that “1/360s early” cmds from PB1 will happen next fiducial
set up camac FC F19A8 so that “on time” cmds from PB0 will execute next fiducial
looks for YY=243. If found, mark current full sec buffer not to be overwritten OR if full, mark next
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
Micro timing pulse to pulse (cont’d)
Time in milliseconds (the 360 Hz fiducial)
2.78 5.56
120 Hz signal
SLC PDU
MPG ISR
Each micro
BGRP: CRYO
128 µs + several µs for speed of light travel
sends intr4 to MPG
saves PB3 to current full sec buffer
receives intr4
reads fault bits from camac
if BCS fault bit asserted, ISR sets BCSFAULT modifier bit in PB3 (created last intr)
finds which BGRP to execute
sends (modified) PB3
based on fault bits and BGRP var (from operator),find MGRP
execute MGRP which creates PB4
is interrupted by the arrival of PB3
xlate 5-bit base beamcode + modifier bits in PB3 into 8 bit beamcode and set up camac FC F19A10 so that “2/360s early” cmds in PB3 will happen next fiducial
set up camac FC F19A9 so that “1/360s early” cmds from PB2 will happen next fiducial
set up camac FC F19A8 so that “on time” cmds from PB1 will execute next fiducial
looks for YY=243. If found, mark current full sec buffer not to be overwritten OR if full, mark next
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
LCLS timing pulse to pulse
Time in milliseconds (the 360 Hz fiducial)
0.00 2.78
SLC PDU
MPG ISR
128 µs + several µs for speed of light travel
BGRP: PEPII
sends intr3 to MPG
adds additional cmds for new apps ext to SCP
receives intr 3
reads fault bits from camac
if BCS fault bit asserted, ISR sets BCSFAULT modifier bit in PB2 (created last intr)
finds which BGRP to execute
sends (modified) PB2
based on fault bits and BGRP var (from operator),find MGRP
execute MGRP which creates PB3
is interrupted by the arrival of PB2
does checksum(s) and if error, appends flag
appends epicsTimeStamp
sets flag that data2 ready
receives flag that data2 ready
PNET VME Receiver
LCLS MPG
appends faults that occurred since PB2 created
Writes EB2 into EVG’s memory PBx = PNETbuffer 'x' is 16 bytes (128 bits);
4 "one second"s worth of PNET buffers is kept in 4 separate arraysEVG Sends EB2 to all EVRs
EBx = EVG buffer 'x' is ~24 bytes (192 bits)
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
LCLS timing pulse to pulse (cont’d)
Time in milliseconds (the 360 Hz fiducial)
SLC PDU
MPG ISR
128 µs + several µs for speed of light travel
sends intr4 to MPG
adds additional cmds for new apps ext to SCP
receives intr4
reads fault bits from camac
if BCS fault bit asserted, ISR sets BCSFAULT modifier bit in PB3 (created last intr)
finds which BGRP to execute
sends (modified) PB3
based on fault bits and BGRP var (from operator),find MGRP
execute MGRP which creates PB3
is interrupted by the arrival of PB3
does checksum(s) and if error, appends flag
appends epicsTimeStamp
sets flag that data3 ready
receives flag that data3 ready
PNET VME Receiver
LCLS MPG
appends faults that occurred since PB3 created
Writes EB3 into EVG’s memory PBx = PNETbuffer 'x' is 16 bytes (128 bits);
4 "one second"s worth of PNET buffers is kept in 4 separate arraysEVG Sends EB3 to all EVRs
EBx = EVG buffer 'x' is ~24 bytes (192 bits)
120 Hz signal
5.562.78 BGRP: CRYO
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
360 Hz fiducial; 120 Hz operation
Time in milliseconds (the 360 Hz fiducial) 120 Hz signal
5.562.78 8.33 11.11 13.89
BGRP=PEPII
BGRP=LCLS
BGRP=NLCTA
0.00
BGRP=PEPII
BGRP=LCLS
BGRP=NLCTA
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
LCLS MPG
Takes the PNETbuffer with appended epicsTimeStamp and checksum fault indicators
Adds on LCLS application commands
Adds on any newly detected faults
Writes modified buffer into EVG’s memory, setting flag when done
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
Event Generator (EVG)
On board FPGA packages/chunks 24 byte LCLS MPG data and sends 2 byte packets to EVR at 125 MHz
Data arrives in EVR in 0.6 microseconds + fiber travel time (which depends on distance)
Driver and device support exists (for sending smaller-sized packets). Conversion to RTEMS (from VxWorks) in progress
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
Event Receiver (EVR)
Resides in SLC-aware IOC
Receives EventBuffer (EB) from EVG
Contents of EB determine actions taken by SLC-aware IOC during current beam pulse
Driver and device support exists (for receiving smaller-sized packets). Conversion to RTEMS (from VxWorks) needed
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
Costs
Event Generator EVG-200: 5687 €Need one (only) in operation and 2 for testing and spare
Event Receiver EVR-200: 2932 €Need one per chassis where triggers required
Transition Modules:EVR-OTB-200 (14 triggers): 829 €
EVR-NTB-200 (32 triggers): 1434 €
Dayle Kotturi
Lehman Review dayle@slac.stanford.edu
May 10-12, 2005
Conclusions
Progress made with PNET VME receiver
LCLS MPG needs to be designed and implemented
EVR/SLC-aware IOC interface needs defining
Performance and reliability from PNET through to EVG must be measured
top related