Curtis A. Nelson 1 Technology Mapping of Timed Circuits Curtis A. Nelson University of Utah September 23, 2002.

Curtis A. Nelson 1

Technology Mapping of Timed Circuits

Curtis A. NelsonUniversity of Utah

September 23, 2002

Curtis A. Nelson 2

Advisors

Academic: Dr. Chris Myers, University of Utah Industry: Dr. Ken Stevens, Intel Corporation Unofficial: Other graduate students

Curtis A. Nelson 3

The Big Picture

Research area: Computer Aided Design Specialty: Timed Asynchronous Circuits Specifically: Technology Mapping

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Overview

Synchronous circuits depend on a central clock. Clock routing and skew are serious design challenges. Asynchronous circuits alleviate clocking problems. Asynchronous advantages can be reduced by overhead. Timed circuits can potentially remove this overhead.

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What are Timed Circuits?

Timed circuits use explicit timing information. Timing assumptions can reduce the state space. Reduced state space may simplify synthesis. Correct operation relies on two-sided timing

constraints <Minimum : Maximum>. Constraints enable performance. Timing violations can cause failure.

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What is Technology Mapping?

Process of choosing gates for circuit implementation. Matches synthesized equations to library elements. Considers cost factors: area, delay, power, etc. Combines the steps of:

Decomposition. Partitioning. Matching / Covering.

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Synchronous Design Flow

Decomposition

Partitioning

Matching/Covering

Physical Design

Cost Factors

Layout

Library

Specifications

MappingTechnology Logic Synthesis

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Timed Design Flow

Matching/Covering

Physical Design

Partitioning

Decomposition

Logic Synthesis

Specifications

Layout

Cost Factors

Library

CheckHazard

Timing Verification

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Hazards and Glitches

Hazards are combinations of delays or timing specifications that may produce glitches.

Glitches are transient, but incorrect logic levels on circuit outputs that likely result in failure.

A

AF

F = A&'A

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Decomposition

Reduces the synthesized circuit into base functions. Typically Inverters, 2-NAND, Storage element

Newly created nodes may introduce hazards. Challenge for timed circuits:

Decompose without creating hazards OR Show that hazards do not produce glitches on outputs.

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Decomposition Example

A

B

C

D

B

C

A E

A

C

B

E

D

D

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Timing Helps Detect Hazards

A<0,0>

B<1,2>

C<2,4>

D

A<0,0>

B<1,2>

C<2,4> D

D

0 2 4 6 8

A

B

C

E

B

A

0 2 4 6 8

D

C

E

E<2,4>

<2,4>

E<2,4>

<2,4>

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How is Hazard Checking Done?

Decomposition creates new nodes that must be checked for hazards. Adds variables to the state graph. Added variables must be checked for consistency. Inconsistent variables hazardous node. Hazardous nodes must be flagged for covering.

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Hazard Checking - Coloring

A

B

C

D

RR00

110R

11R1

111F

0F10

01R0

B-

B+

C+D-

A-

C+

A+

F110

C-

B+

D+

00F01R00 R

R

R

R

F

F

F

R

R

R

R

F

F

F

F

F

F F

ABCDState =

A

C

B

DE

D

C

A

BE

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Hazard Checking - Propagation

A

B

C

D

ABCDState =

A

C

B

DE

D

C

A

BE

RR00

110R

11R1

111F

0F10

01R0

B-

B+

C+D-

A-

C+

A+

F110

C-

B+

D+

00F01R00 R

R

R

R

F

F

F

R

R

R

R

F

F

F

F

F

1

11 1

0

0

0

F F0

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Hazard Checking - Done

A

B

C

D

ABCDState =

RR00

110R

11R1

111F

0F10

01R0

B-

B+

C+D-

A-

C+

A+

F110

C-

B+

D+

00F01R00 R

RF

F

F

R

R

F

F

1

1

1 10

0

0

0

0

A

C

B

DE

D

C

A

BE

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Where Timing Helps

A

B

C

D

ABCDState =

RR00

110R

11R1

111F

0F10

01R0

B-

B+

C+D-

A-

C+

A+

F110

C-

B+

D+

00F01R00 R

RF

F

F

R

R

F

F

1

1

1 10

0

0

0

0

A

C

B

DE

D

C

A

BE

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Matching / Covering

Matches decomposed logic to library cells. Results depend on decomposition structure. Nodes determined to be hazardous must be

encapsulated within library elements.

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Structural Library Representation

All elements represented using base functions.

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Matching / Covering Example

A

B

C

2

3

1D4

C

A

B

3

4 D

41

C

B

A

D

2

3C

A

BD

INV NAND2 AND2 OR2 NAND3

A

B

C

D

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Conclusions

Timed circuits must be synthesized and mapped. Hazards must be detected and eliminated. Result: Hazard-free net-list of library components. Timed circuits are becoming a viable alternative to

synchronous design.

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Contributions

Using explicit timing to eliminate hazards. Library matching with the intent to remove hazards. Provide a complete timed circuit design flow. Increase awareness of timed circuit design.

CAD Tools for Timed Circuit Design Industry