Computer Architecture

Structured Computer Organizationby A. Tanenbaum, Prentice Hall, 2005

B. W. WahECE 290Fall 2006

Introductions

Languages, Levels, Virtual Machines

A multilevel machine

Contemporary Multilevel Machines

A six-level computer. The support method for each level is indicated below it .

Computer Generations• Zero’th Generation

Mechanical Computers (1642 – 1945)

• First GenerationVacuum Tubes (1945 – 1955)

• Second GenerationTransistors (1955 – 1965)

• Third GenerationIntegrated Circuits (1965 – 1980)

• Fourth GenerationVery Large Scale Integration (1980 – ?)

Von Neumann Machine

The original Von Neumann machine.

PDP-8 Innovation – Single Bus

The PDP-8 omnibus

Technological and Economic Forces

Moore’s law predicts a 60-percent annual increase in thenumber of transistors that can be put on a chip. The data points given in this figure are memory sizes, in bits.

Personal Computer

A printed circuit board is at the heart of every personal computer. This figure is a photograph of the Intel D875PBZ board. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission.

1. Pentium 4 socket2. 875P Support chip3. Memory sockets4. AGP connector5. Disk interface6. Gigabit Ethernet7. Five PCI slots8. USB 2.0 ports9. Cooling technology10. BIOS

Example Computer Families

• Pentium 4 by Intel• UltraSPARC III by Sun Microsystems• The 8051 chip by Intel, used for embedded systems

Intel Computer Family (1)

The Intel CPU family. Clock speeds are measured in MHz (megahertz) where 1 MHZ is 1 million cycles/sec.

The Pentium 4 chip. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission.

Moore’s law for (Intel) CPU chips.

Computer Systems Organization

Central Processing Unit

The organization of a simple computer with one CPU and two I/O devices

CPU Organization

The data path of a typical Von Neumann machine.

Instruction Execution Steps

1. Fetch next instruction from memory into instr. register2. Change program counter to point to next instruction3. Determine type of instruction just fetched4. If instructions uses word in memory, determine where

Fetch word, if needed, into CPU register5. Execute the instruction6. Go to step 1 to begin executing following instruction

RISC versus CISC• 1980: RISC has simple instructions that can be executed in

one cycle of a simple data path• Execute frequently used instructions efficiently and less frequently

used instructions less efficiently• Wins over CISC that takes multiple and longer cycles to execute a

complex instruction• May take 4-5 instructions to accomplish a complex operation

• CISC is still predominant in today’s market• Backward compatibility to early CISC computers• Starting with 486, Intel CPUs contain a RISC core that executes the

simplest (and typically most common) instructions in a single data path cycle, while interpreting the more complicated instructions in the usual CISC way

Design Principles for Modern Computers

• All instructions directly executed by hardware• Maximize rate at which instructions are issued• Instructions should be easy to decode• Only loads, stores should reference memory• Provide plenty of registers

Instruction-Level Parallelism

a) A five-stage pipelineb) The state of each stage as a function of time. Nine clock

cycles are illustrated

Superscalar Architectures (1)

Dual five-stage pipelines with a common instruction fetch unit.

Superscalar Architectures (2)

A superscalar processor with five functional units.

Processor-Level Parallelism (1)

An array of processor of the ILLIAC IV type.(ILLIAC I in Sept. 1952)

Processor-Level Parallelism (2)

a) A single-bus multiprocessor.b) A multicomputer with local memories.

Cache Memory

The cache is logically between the CPU and main memory. Physically, there are several possible places it could be located.

Memory Hierarchies

A five-level memory hierarchy.

Magnetic Disks (1)

A portion of a disk track. Two sectors are illustrated.

Magnetic Disks (2)

A disk with four platters.

Magnetic Disks (3)

A disk with five zones. Each zone has many tracksand has uneven number of tracks across zones.

RAID (1) Redundant Array of Inexpensive Disks (1988)

RAID levels 0 through 2. Backup and parity disks are shown shaded.

4 bit with errorcorrection in CM2

RAID (1) Redundant Array of Inexpensive Disks

RAID levels 3 through 5. Backup and parity disks are shown shaded.

The Processor Level

CPU Chips

The logical pinout of a generic CPU. The arrows indicate input signals and output signals. The short diagonal lines indicate that multiple pins are used. For a specific CPU, a number will be given to tell how many.

Computer Buses (1)

A computer system with multiple buses.

Computer Buses (2)

Examples of bus masters and slaves.

Bus Width

Growth of an Address bus over time.

Bus Clocking

Read timing on a synchronous bus.

Asynchronous Buses

Operation of an asynchronous bus.

Bus Arbitration (1)

(a) A centralized one-level bus arbiter using daisy chaining.(b) The same arbiter, but with two levels.

Bus Arbitration (2)

Decentralized bus arbitration.

Bus Operations (1)

A block transfer.

Bus Operations (2)

Use of the 8259A interrupt controller.

The Pentium 4

The Pentium 4 physical pinout.

The Pentium 4’s Logical Pinout

Logical pinout of the Pentium 4. Names in upper case are the office are the official Intel names for individual signals. Names in mixed case are groups of related signals or signal descriptions.

Pipelining on the Pentium 4’s Memory Bus

Pipelining requests on the Pentium 4’s memory bus.

The UltraSPARC III (1)

The UltraSPARC III CPU chip.

The UltraSPARC III (2)

The main features of the core of an UltraSPARC III system.

The PCI Bus (1)

Architecture of an early Pentium system. The thicker buses have more bandwidth than the thinner ones but the figure is not to scale.

The PCI Bus (2)

The bus structure of a modern Pentium 4.

PCI Bus Arbitration

The PCI bus uses a centralized bus arbiter.

PCI Express

A typical PCI Express system.

PCI Express Protocol Stack

(a) The PCI Express protocol stack.(b) The format of a packet.

The Microarchitecture Level

Speed Versus Cost

1. Reduce the number of clock cycles needed to execute an instruction.

2. Simplify the organization so that the clock cycle can be shorter.

3. Overlap the execution of instructions.

Merging the Interpreter Loop with the Microcode (1)

Original microprogram sequence for executing POP.

Merging the Interpreter Loop with the Microcode (2)

Enhanced microprogram sequence for executing POP.

Pipelining

Graphical illustration of

how a pipeline works.

A Seven-Stage Pipeline

The Mic-4 pipeline.

Cache Memory

A system with three levels of cache.

Direct-Mapped Caches

(a) A direct-mapped cache. (b) A 32-bit virtual address.

Set-Associative Caches

A four-way set-associative cache.

Branch Prediction

(a) A program fragment. (b) Its translation to a generic assembly language.

Dynamic Branch Prediction (1)

(a) A 1-bit branch history. (b) A 2-bit branch history. (c) A mappingbetween branch instruction address and target address.

Dynamic Branch Prediction (2)

A 2-bit finite-state machine for branch prediction.

Speculative Execution

a) A program fragment. b) The corresponding basic block graph.

Overview of the NetBurst Microarchitecture

The block diagram of the Pentium 4.

The NetBurst Pipeline

A simplified view of the Pentium 4 data path.

The Operating SystemMachine Level

Operating System Machine

Positioning of the operating system machine level.

Paging

A mapping in which virtual addresses 4096 to 8191 are mappedonto main memory addresses 0 to 4095.

Implementation of Paging (1)

The first 64 KB of virtual address space divided into 16 pages, with each page being 4K.

A 32 KB main memory divided up into eight page frames of 4 KB each.

Formation of a main memory address from a virtual

address.

Demand Paging and the Working Set Model

A possible mapping of the first 16 virtual pages

onto a main memory with eight page frames.

Page Replacement Policy

Failure of the LRU algorithm.

Segmentation (1)

In a one-dimensional address space with growing tables, one table may bump into another.

Segmentation (2)

A segmented memory allows each table to grow or shrink independently of the other tables.

Segmentation (3)

Comparison of paging and segmentation.

Implementation of Segmentation (1)

(a)-(d) Development of external fragmentation. (e) Removal of the external fragmentation by compaction.

Implementation of Segmentation (2)

Conversion of a two-part MULTICS address into a main memory address.

Parallel Computer Architectures

(a) On-chip parallelism. (b) A coprocessor. (c) A multiprocessor.(d) A multicomputer. (e) A grid.

Instruction-Level Parallelism

(a) A CPU pipeline. (b) A sequence of VLIW instructions. (c) An instruction stream with bundles marked.

The TriMedia VLIW CPU

A typical TriMedia instruction, showing five possible operations.

On-Chip Multithreading (1)

(a) – (c) Three threads. The empty boxes indicated that the threadhas stalled waiting for memory. (d) Fine-grained multithreading.

(e) Coarse-grained multithreading.

On-Chip Multithreading (2)

Multithreading with a dual-issue superscalar CPU. (a) Fine-grained multithreading.

(b) Coarse-grained multithreading. (c) Simultaneous multithreading.

Hyperthreading on the Pentium 4

Resource sharing between threads in the Pentium 4 NetBurst microarchitecture.

Homogeneous Multiprocessors on a Chip

Single-chip multiprocessors. (a) A dual-pipeline chip. (b) A chip with two cores.

Heterogeneous Multiprocessors on a Chip (1)

The logical structure of a simple DVD player contains a heterogeneousmultiprocessor containing multiple cores for different functions.

Heterogeneous Multiprocessors on a Chip (2)

An example of the IBM CoreConnect architecture.

Introduction to Network Processors

A typical network processor board and chip.

The Nexperia Media Processor

The Nexperia heterogeneous multiprocessor on a chip.

Multiprocessors

(a) A multiprocessor with 16 CPUs sharing a common memory.(b) An image partitioned into 16 sections, each being analyzed

by a different CPU.

Multicomputers (1)

(a) A multicomputer with 16 CPUs, each with its own private memory.(b) The bit-map image of Fig. 8-17 split up among the 16 memories.

Multicomputers (2)

Various layers where shared memory can be implemented. (a) Thehardware. (b) The operating system. (c) The language runtime system.

Taxonomy of Parallel Computers (1)

Flynn’s taxonomy of parallel computers.

Taxonomy of Parallel Computers (2)

A taxonomy of parallel computers.

UMA Symmetric Multiprocessor Architectures

Three bus-based multiprocessors. (a) Without caching. (b) Withcaching. (c) With caching and private memories.

UMA Multiprocessors Using Crossbar Switches

(a) An 8 × 8 crossbar switch. (b) An open crosspoint. (c) A closed crosspoint.

UMA Multiprocessors Using Multistage Switching Networks

An omega switching network.

NUMA Multiprocessors

A NUMA machine based on two levels of buses. The Cm* wasthe first multiprocessor to use this design.

Cache Coherent NUMA Multiprocessors

(a) A 256-node directory-based multiprocessor. (b) Division of a 32-bit memory address into fields. (c) The directory at node 36.

The Sun Fire E25K NUMA Multiprocessor (1)

The Sun Microsystems E25K multiprocessor.

BlueGene (1)

The BlueGene/L custom processor chip.

BlueGene (2)

The BlueGene/L. (a) Chip. (b) Card. (c) Board. (d) Cabinet. (e) System.

Red Storm (1)

Packaging of the Red Storm components.

Red Storm (2)

The Red Storm system as viewed from above.

A Comparison of BlueGene/L and Red Storm

A comparison of BlueGene/L and Red Storm.

Google (1)

Processing of a Google query.

Google (2)

A typical Googlecluster.

Grid Computing

The grid layers.

Computer Architecture - HCMUT - hcmut.edu.vndttin/Computer architecture/General 5 th Edition...1 Computer Architecture Structured Computer Organization by A. Tanenbaum, Prentice Hall,

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