Transcript
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Digital Electronics_Jean-Paul NGOUNE 1
Courses In
Electrical
Engineering
Volume II
DIGITAL ELECTRONICS
CHAPTER SIX: COMBINATORY LOGIC
By
J-P. NGOUNE
DIPET I (Electrotechnics), DIPET II (Electrotechnics)
DEA (Electrical Engineering)
Teacher in the Electrical Department, GTHS KUMBO, Cameroon.
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The full adder has three inputs:
- A: bit from number A;
- B: Bit from number B;
- Cin: Carry out coming from the previous rank.
And two outputs:
- S: the bit of sum;
- Cout: The carry out (to be added to the bits of the next rank).
Truth table:
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Equations of the outputs :
We can either use Boolean algebra or k-map to determine the equations of
the outputs.
- Using Boolean algebra:
iiiiABCCBACBACBAS +++= ..
( ) ( )( ) ( )iin
iiii
CBACBA
BCCBACBCBA
+=
+++= .
Let X = ( )iCB
XAXAS +=
iCBA
XA
=
=
iCBAS =
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iiii ABCCABCBABCACo +++= .
The expression will not change if one of the elements of the sum of products is
duplicated (After the Boolean additive identity according to which A + A = A, A being
a Boolean variable). So we will duplicate the product iABC three times in order to
simplify the expression easily.
iiiiiiABCABCABCCABCBABCACo +++++= .
( ) ( ) ( )ABACBC
CCABBBACAABC
ii
iiii
++=
+++++=
- Using k-map:
iiii ABCCBACBACBAS +++= ..
ABACBCCoii++=
00 01 11 10
0 0 1 0 1
1 1 0 1 0
S
A
BCi
iCBAS =
00 01 11 10
0 0 0 1 0
1 0 1 1 1
Co
A
BCi
ABACBCCoii++=
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Logic diagram
A B Ri
S
Ro
6.4 The half adder:
The half adder has two inputs A and B which are the two bits to be added, and
two outputs which are the sum output S and the carry output Co. The principle
diagram of the half adder is given by the following diagram.
Figure 6.3: Principle diagram of a half adder
Truth table:
A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Ci
Co
HA
A
B
S
Co
BAC
BAS
BABAS
o .
..
=
=
+=
Equations of the outputs
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Exercise 6.1:
Consider the following digital system made up of two half adders and an OR
gate. Establish the truth table of the system and draw a conclusion.
6.4 The Subtractor:
As we have seen in the previous chapter, the subtraction of a number B from a
number A can be treated as the addition of the number A with the twos complement
of the number B.
)1()()( 2 ++=+=+= BABCABABA
6.4.1 The half subtractor:
The half Subtractor performs the subtraction of a number having one bit from
another number having one bit. It has two inputs which are the two numbers A and B
to be added, and two outputs Diand Cowhich are respectively the difference and the
carry out.
Truth table
A B Di Co
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Co
S
DA
So
CoDA
A
B
Ci
Remark 6.1:
0 1 = -1 = 11(Twos complement notation)
1 and carry out of 1
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Equations of the outputs:
Logic diagram:
A
B
Ro
Di
6.4.2 The full subtractor :
The structure above can be modified to achieve subtractions involving
numbers having more than one bit. In fact, such operation is performed by a full
subtractor. It has then an additional input Ciwhich is the Carry in (from the previous
rank).
Truth table:
A B Ci Di Co
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 01 1 1 1 1
Remark 6.2:
0 1 1 = 1102 (-210 in twos complement notation) 0 and carry out of 1.
BABABADi
=+= .. BACo =
Co
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6.5 The comparator
A comparator is a combinatory logic circuit which is intended to detect among
two binary numbers the one which is the greater (or the smaller). It detects also the
equality of the two numbers. The numbers to be compared should have the same
number of bits. Let us design a comparator for two numbers having one bit each.
Truth table:
Logic diagram
A B
S1
S2
S3
Exercise 6.2:
Design a logic circuit which is able to compare two numbers having two bits each.
6.6 The decoder:
The decoder is a combinatory logic circuit which functions in such a way that
for a given input address, only one of its outputs is activated. The principle diagram
of the decoder is presented by the following figure:
A B
S1
(A>B)
S2
(A=B)
S3
(A
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Figure 6.4: Principle diagram of a decoder.
The Input address is a binary code of N bits. For N bits, there are 2N possible
input addresses. So, the decoder has M = 2N outputs such that, for each input
address, only one output can be activated among the 2N available.
Let us design a decoder having three inputs (And therefore 2N = 8 outputs).
Such a decoder is also called a 3 to 8 decoder.
Truth table:
A B C O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Equations of the outputs:
.
.
.
.
.
.
I0 O0
OM-1IN-1
Decoder
N to M
N inputsM outputs,
only one is
activated
CBAO
CBAO
CBAO
CBAO
..
..
..
..
3
2
1
0
=
=
=
=
CBAO
CBAO
CBAO
CBAO
..
..
..
..
7
6
5
4
=
=
=
=
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Logic diagram:
A B C
.
.
.
O0
O1
O7
Applications of decoders
The applications of decoders are found in many digital systems. Here are
some of them.
a) Addressing of a memory:
A memory is made up of registers which contain memory words. Addressing a
memory consist of allocate to each register a particular code which permits to identify
it and also to get access to the data stored within it.
Let us consider a memory having 16 registers, each register storing a memory
word of 8 bits (1 byte). We want to address that memory so that, for each address
code sent to the memory, only one register will be accessible.
To solve this problem, we can use a decoder having 4 inputs and 24
= 16
outputs. Each output will be connected to one of the 16 registers such that, for each
of the 16 possible input addresses, only one register can be selected. The following
figure presents the synoptic diagram of the system.
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Figure 6.5: Addressing of a memory having a capacity of 16 bytes
b) DCB seven segments decoder:
In many systems, seven segments displays are used to represent numbers
from 0 to 9 and sometimes alphabetical characters.
Figure 6.6: Seven segment display.
The DCB - seven segments decoder accepts at its inputs a DCB code of four
bits, and activate its outputs which will permit to enlighten the LEDs representing the
corresponding cipher (corresponding to the DCB code).
Address
Chip select
Decoder
4 to 16
Ligne 0
Ligne 15
1 0 1 0 0 1 1 0
.
.
.
Register storing one byte
4
Each segment ismade up of one
or two LED
g
c
b
a
DCB 7
Segments
decoder
DCD
input
codes.
.
.
Protective resistor
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Let us design a DCB Seven segment segments decoder which will permit us
to represent digital numbers from 0 to 9 on a 7 segments display.
- Truth table:
D C B A a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 1 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
a
b
c
d
e
f
g
Exercise 6.3:
Determine the Boolean expressions for the others outputs.
Exercise 6.4:
The following system uses a 3 bits segments decoder to represent the letters
ABCDEFGH on a seven segments display. Design that decoder after filling its truth
table.
Equations of the outputs :
ACBDABCDa ...... +=
( )( )ABCDABCDa ++++++= .
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a
b
c
d
e
f
g
3 to seven
segmentdecoder
A
B
C
A B C a b c d e f g Display
0 0 0 1 1 1 0 1 1 1 A
0 0 1 B
0 1 0 C
0 1 1 D
1 0 0 E
1 0 1 F1 1 0 G
1 1 1 H
a) Fill the truth table;
b) Determine the Boolean expressions of the output a,b,c,d,e,f,g;
c) Draw the logic diagram of the circuit.
Exercise 6.5:
Design a DCB Decimal decoder. It is a decoder whose inputs are the four bits of
the DCB code and who has ten outputs.
6.7 The encoder:
The encoder is a combinatory logic circuit which outputs an exclusive binary
code when each of its inputs is activated. When one of its inputs is activated, a binary
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code corresponding to that input is sent to the output. The encoder does the reverse
of the decoder. Encoder circuits are used in the conception of keyboards.
Figure 6.7: Principle diagram of an encoder
Let us realise an 8 to 3 encoder. It is a combinatory logic circuit having 8
inputs an 3 outputs which functions in such a way that, when an input is activated, a
corresponding binary number coded in three bits is sent to the output.
Truth table:
Only one among the eight inputs should be activated at once.
I0 I1 I2 I3 I4 I5 I6 I7 O2 O1 O0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
M inputs, only
one amongthem is high
Binary code at
the output
IM-1
I
.
.
.
Encoder
ON-1
O0
.
.
.
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Equations of the outputs:
The equation of each output is simply the Boolean addition of all the inputs for
which that outputs is at the high logic level. Hence,
75310
76321
76542
IIIIO
IIIIO
IIIIO
+++=
+++=
+++=
Logic diagram:
I0
I1
I2
I3
I4
I5
I6
I7
O0
O1
O2
When no input is activated, the circuit outputs automatically 000. That is why
the input I0 is not connected.
Exercise 6.6:
Design a decimal DCB encoder. It is an encoder having 10 inputs
representing the 10 digits of the decimal system of numeration, and 4 outputs
intended to produce DCB codes corresponding to each input when it is activated.
Remark 6.2: encoder with priority
The encoder designed above would produce a wrong result if two inputs were
activated at the same time. There are encoders with priority circuits which functions
in such a way that, if two or more inputs are activated at once, the binary code sent to
the output is that of the input having the highest value. For instance, if the inputs I2,
I5 and I6 are activated the same time, the encoder will output the binary code 110
corresponding to the input I6.
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Exercise 6.7:
Design a digital system which permits to display the 10 symbols of the decimal
system of numeration on a 7 segments display using a 10 buttons keyboard.
6.8 The transcoder:
The transcoder is a combinatory logic circuit which converts a given binary
code into another binary code. For instance, let us design binary to Gray encoder. It
is a circuit which receives at its inputs binary numbers and outputs corresponding
Gray codes.
Figure 6.8: Principle diagram of a binary to Gray transcoder
Truth table:
Binary code Gray code
A B C X Y Z
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
Gray
Code
Binary
system
Binary to
Gray
transcoder
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Equations of the outputs:
00 01 11 10
0 0 0 0 0
1 1 1 1 1
00 01 11 10
0 0 0 1 1
1 1 1 0 0
00 01 11 10
0 0 1 0 1
1 0 1 0 1
Logic diagram:
A
B
C
X
Y
Z
6.9 : The multiplexer:
A multiplexer also called data selector is a combinatory logic circuit which
permits to direct towards single output information coming from many inputs.
According to the address received by the multiplexer, only one among the information
available at its inputs is selected and directed toward the output. A multiplexer can be
X
A
BC
Y
A
BC
Z
A
BC
X = A
BAY
BABAY
=
+= ..
CBZ
CBCBZ
=
+= ..
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considered as a commutator having multiple poles which are switched according to
the address sent to the multiplexer.
Figure 6.9: Principle diagram of a multiplexer
E is the enable input. It enable the multiplexer to function when the right logic
signal level is sent to it (For the principle diagram above, the right signal level is
slow).
For an address bus having nlines, up to 2n data can be addressed such that
for each of these addresses, one among the 2n data is selected and directed towards
the output.
Let us design an elementary multiplexer. It is a multiplexer having two data
inputs I0 and I1 and one address input A.
The address can be either 0 or 1. When the address is 0, the datum I0 is
selected and sent to the output. When the address is 1, I1 is selected and directed
towards the output.
E
Output
2n
data inputs
n address
inputs
MUX
Address A Mux
Output
I0 I1
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Truth table:
A S
0 I0
1 I1
When A = 0, we have:0
10 0.0.
IS
IIS
=
+=
The information I0 is therefore directed to the output. That information can be a
logic state or even a set of data coded in many bits.
When A = 1, we have:1
10 1.1.IS
IIS=
+=
Logic diagram:
1
23
A
I1
I0
S
Let us design now a more complex multiplexer; it is a multiplexer having four
data inputs. For 4 data, we need 2 address lines to address all the information.
Truth table:
A B S
0 0 I0
0 1 I1
1 0 I2
1 1 I3
AIAIS 10 +=
3210 ........ IBAIBAIBAIBAS +++=
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Logic diagram:
I0
I1
I2
I3
A B
S
Exercise 6.8:
Design a multiplexer having 8 data inputs
Application of multiplexer:
The applications of multiplexers are found in many digital systems. These are
some of those applications:
- Parallel to series conversion:
In many digital systems, the treatment of information is done in parallel;
however, when those information are to be transferred on a long distance, this
cannot be done in parallel. In fact, parallel transfer of information is not effective
because it requires a large number of lines trough which data will flow; on the other
hand, its causes a lot of errors in data transfer. The parallel to series conversion
permits to make in such a way that the information treated in parallel can betransferred in series trough a single line. A parallel to series converter can be realised
using a multiplexer as shown by the following figure:
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I0
I1
I2
I3
I4
I5
I6
I7
Figure 6.10: Parallel to series converter
- Realisation of logic functions:
Logic functions can be realised using multiplexers. Let us consider a logic
function described by the following truth table:
A B C S
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
This function can be realised without using logic gates. We can use a single
multiplexer integrated circuit having 8 data inputs. The principle consist in connecting
the outputs having low logic level to the earth and those having high logic level to the
positive probe of the supply Vcc, as shown by the following figure:
Series
output
Multiplexerwith 8 data
inputs
Modulo 8
counter
Register containing data
in parallel
The modulo 8 counter
generate successively addresses
from 000 to 111. Each of those
addresses permits to direct
towards the series output one of
the 8 bits stored in the register.
I0
I1
I2
I3
I4
I5
I6
I7
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Figure 6.11: Realisation of a logic function using a multiplexer.
Exercise 6.9:
Consider a combinatory logic circuit described the following truth table:
A B C S
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
a. Design the circuit and draw its logic diagram using logic gates.
b. Realise the same logic function using a multiplexer.
Exercise 6.10:
Realise a multiplexer having 4 data inputs using a 2 to 4 decoder and logic
gates of your choice.
E
S
I0 I1 I2 I3 I4 I5 I6 I7
MUXABC
Vcc
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6.10 The demult iplexer:
The demultiplexer is a combinatory logic circuit which permits to direct towards
many outputs information coming from a single input. The demultiplexer has n
address inputs and 2n outputs such that, when an address is sent to it, the
information is directed towards the corresponding output (the information is sent to
only one among the 2n available outputs).
Figure 6.12: Principle diagram of a multiplexer.
Let us realise a multiplexer having four outputs (and therefore 2 address
inputs).
Truth table:
A B O0 O1 O2 O3
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I
n addressinputs DEMUX
One data input
2n Outputs
IBAOIBAO
IBAO
IBAO
....
..
..
3
2
1
0
=
=
=
=
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Logic diagram:
O0
O1
O2
O3
A B
I
Exercise 6.11:
Design a demultiplexer having 8 outputs.
6.11 Conclusion:
The present chapter has permitted us to study many of the most common
combinatory circuits. The particularity of those type of circuits was that the logic state
of their outputs at a given instant depends only on the combination of the logic states
of their inputs. The next chapter will deal with sequential logic. The output of a
sequential logic circuit depends not only on the combination of its inputs logic states,
but also on the memory of the circuit. The chapter will start with the study of
multivibrators (latches and flip-flops) which are tools used in the conception of
sequential logic circuits.
REVIEW QUESTIONS
1. (From Probatoire F3, 2009 session). Full adder.
The figure 6.13 below represents the circuit of a full adder, where A1 and B1
are the variable inputs. R1 is the carry while So and Ro are the sum and the reminder
respectively.
Figure 6.13: Full adder.
SoRo
A1
B1
R1Full adder
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Figure 6.14: Multiplicator circuit.
a. What do you understand by the statements Least Significant Bit and Most
Significant Bit?
b. Establish the truth table of the system.
c. Write the expression of each of the outputs Z3, Z2, Z1 and Z0 as function of X1,
X0, Y1 and Y0.
d. Using k-maps, simplify the output equations obtained from above.
e. Draw the logic diagram of the electronic multiplicator circuit using the
simplified output equations from the k-maps:
- Using AND gates only
- Using NAND and NOR gates only.
4. (From Probatoire 2007). Multiplexer circuit.
Consider the diagram of the figure 6.14 bellow. It is a multiplexer connected as a
function generator.
A1
A2
A3
E0 E1 E2 E3 E4 E5 E6 E7
Vcc (1)
GND (0)
A B C D
SV
Figure 6.14: Multiplexer as function generator.
Z3
Z2
Z1
Z0
X1
X0
Y1
Y0
Multiplicator circuit
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a. Identify the inputs of this multiplexer and give their roles.
b. Give the output equation of the function S.
c. Simplify that equation using k-map
d. Realise the simplified function using two-inputs NAND gates exclusively.
5. (From GCE A Level, 2000 session).
A factory crane operator is to control red and green safety lights by four
switches A, B, C and D. Design a simple logic system which will operate under the
following conditions:
Red light ON for:
- Switch A ON and switch B OFF or
- Switch C ON.
Green light ON for:
- Switches A and B ON and
- Switches C and D OFF.
NB: In designing you should respect the following steps:
a. Establish the truth table.
b. Write the equations of the outputs.
c. Simplify the equations if possible.
d. Draw the logic circuit.
References:
1. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition,
Prentice-Hall inc., Englewood Cliffs, New Jersey , USA,1985.
2. Lessons In Electric Circuits Volume IV Digital, Tony R. Kuphaldt, Fourth
Edition, 2007, www.allaboutcircuits.com . www.ibiblio.org/obp/electricCircuits.
3. Cours de systmes logiques, Notes de cours, Premire anne du gnie
lectrique, ENSET de Douala, J.C Tsokezo, 2004-2005.
http://www.allaboutcircuits.com/http://www.ibiblio.org/obp/electricCircuitshttp://www.ibiblio.org/obp/electricCircuitshttp://www.allaboutcircuits.com/
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