Combinational Circuit Design and Simulation Using Gates
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Unit 8 1
Unit 8
Combinational Circuit Design andSimulation Using Gates
Unit 8 2
Outline․Review of combinational circuit design․Design of circuits with limited gate fan-in ․Gate delay and timing diagrams ․Hazards in combinational logic ․Simulation and testing of logic circuits
Unit 8 3
Review of Combinational Circuit Design
․Design of a combinational switching circuit Setup a truth table which specifies the output(s)
as a function of the input variables Derive simplified algebraic expressions for the output functions using
K-Maps, the Q-M method, or other similar procedures.
․Multi-level & Multi-output circuit․Minimum SOP’s starting point
Minimum two-level AND-OR、NAND-NAND、OR-NAND、NOR-OR
․Minimum POS’s starting point Minimum two-level OR-AND、NOR-NOR、AND-NOR、NAND-
AND
Unit 8 4
Circuit with Limited Gate Fan-In (1/3)․Ex 1
Realizeusing 3-input NOR gates
( , , , ) (0, 3, 4, 5, 8, 9, 10, 14, 15)f a b c d m
')'(')''(' '''''''''
abcdbcaaccadbcdabcaabccdabdcbaf
1 1 0 1
0 1 0 1
1 0 1 0
0 0 1 1
00
10
11 1000
01
11
01ab
cd
fa’b’c
c’a
bd’
ac
c’a’
bd’
․Ex 2Only using 2-input NAND gates and inverters
Unit 8 5
Circuit with Limited Gate Fan-In (2/3)
3 ' ' 'f a b c ab bc 2 ' ' 'f b c bc a b 1 ' ' ' 'f b c ab a b
1 1
1
1
1
)5,4,3,2,0(1 mf
0 1
00
01
11
10
abc
1 1
1 1
1
)7,4,3,2,0(2 mf
0 1
00
01
11
10
abc
1
1
1 1
)7,6,2,1(3 mf
0 1
00
01
11
10
abc
Unit 8 6
)c'b(a ''' )')('(or '' )'(
' )'('
3
22
1
cbafbacbcbfcbcabf
bacabf
Circuit with Limited Gate Fan-In (3/3)
f1
f2
f3
b’
a’b
a’
b’c
b
b
ac’
b’c
c’
(a)
f1
f2
f3
b’
a’b
a’
b’c
b
b’
a’c
bc’
c
(b)
Unit 8 7
Gate Delay and Timing Diagrams (1/2)
Unit 8 8
Gate Delay and Timing Diagrams (2/2)
AND = 2ns NOR = 3ns
V
V
W
Y
X
Z
W
X
Y
Z
0 2 6 12 18 28nsIf x signal is complemented, what happen to z ?
Unit 8 9
Hazard in Combinational Logic (1/5)․What is hazard?
Unwanted switching transients appearing in the output while the input to a combinational circuit changes
․Types of hazards
․In K-Map, If any two adjacent 1’s are not covered by the same loop,
a 1-hazard exists for the transition between the two 1’s.
(a) Static 1-hazard (b) Static 0-hazard (c) Dynamic hazards
Unit 8 10
․Let A=1 and C=1 (Static 1-hazard)
Hazard in Combinational Logic (2/5)
BA
C
D
E
F
BCABF '
BDEF
00
01
10
11
1-hazard
Unit 8 11
Hazard in Combinational Logic (3/5)
0
0
1
0 0
1
1
1
ABC
00
01
11
10
0 1
Circuit with hazard removed
AB
C
A
F
Unit 8 12
Static 0-hazard
․Let A=0, B=1, and D=0 (Static 0-hazard)
Hazard in Combinational Logic (4/5)
C
W
X
Y
Z
0 5 8 10 13 15 18 20(c) Timing diagram illustrating 0-hazard of (a)
0 0
00 0 0
00
00
00
01
11
10
00 01 11 10AB
CD
(b) Karnaugh map for circuit of (a)
(a) Circuit with a static 0-hazard
W1
2
3
4
Y
Z
B
D
A
C
X
at 5ns, 0→1 at 10ns, 0→1
at 13ns, 1→0 at 8ns, 1→0 AND/OR: 5ns
INV: 3ns
at 15ns, 0→1 at 18ns, 1→0
Unit 8 13
Circuit with hazard removed
)'C'B'A)(D'BA)('DC)(D'C'B)('D'A)(CA(F
)'')('')(( DCBDACAF
Hazard in Combinational Logic (5/5)
000
01
11
10
AB
CD
0
00 0 0
00
00
00 01 11 10
Unit 8 14
Simulation and Testing of Logic Circuits (1/4)
․For simulating logic circuits Specify the circuit components and connections Determine the circuit inputs Observe the circuit outputs
․4-valued logic simulator 0 (low)、1 (high)、X (unknown)、Z (high impedance)
(a) Simulation screen showing switches (b) Simulation screen with missing gate input
1
1
1
1
1
1
10
0
0
0
0
0
1
1
10
010
1
0
1
Z
01
X
XProbe
Unit 8 15
Simulation and Testing of Logic Circuits (2/4)
00
10100000
10
ZX
ZX
X X
X X X
X X X 11
1111110010
ZX
ZX
X X
X
XX
XX
X
AND & OR function for 4-valued simulation
Unit 8 16
․In the logic circuit, a wrong output may be due to
Verification Incorrect design Gates connected wrong Wrong input signals to the circuit
Testing Defective gates Defective connecting wires
Simulation and Testing of Logic Circuits (3/4)
Unit 8 17
․Logic circuit with incorrect output A = B = C = D = 1, F=0
Simulation and Testing of Logic Circuits (4/4)
1
2
3
4
5
6
7
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