Chapter 7ocw.nctu.edu.tw/course/digital design/Logic DesignCh07.pdf · 7-5 Microoperations 7-7 Register Cell Design ... D. Ripple counter (§7-6) E. Synchronous binary counters ...
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J.J. Shann
Chapter 7
Registers &
Register TransfersJ. J. Shann
J.J. Shann 7-2
Chapter Overview7-1 Registers and Load Enable7-2 Register Transfers7-3 Register Transfer Operations7-4 A Note for VHDL and Verilog Users Only7-5 Microoperations7-6 Microoperatrions on a Single Register7-7 Register Cell Design7-8 Multiplexer and Bus-Based Transfer for Multiple
Registers7-9 Serial Transfer and Microoperations7-10 HDL Representation for Shift Registes and Counters
VHDL7-11 HDL Representation for Shift Registes and Counters
Verilog7-12 Chapter Summary
J.J. Shann 7-3
Part I: Registers and Counters7-1 Registers and Load Enable7-6 Microoperatrions on a Single Register
(Shift registers, Ripple counter, Synchronous binary counters, other counters)
Part II: Register Transfers7-2 Register Transfers7-3 Register Transfer Operations7-5 Microoperations7-7 Register Cell Design7-6 Microoperatrions on a Single Register
(Multiplexer-Based Transfers)7-8 Multiplexer and Bus-Based Transfer for Multiple Registers7-9 Serial Transfer and Microoperations
7-12 Chapter Summary
J.J. Shann
Part I
Registers and Counters
J.J. Shann 7-5
Clocked seq ckt: sync seq ckt consists of a group of flip-flops and combinational gates
connected to form a feedback path.Flip-flops + Combinational gates(essential) (optional)
Register: consists of a group of flip-flops capable of storing binary
information and gates that determine how the information is transferred into the register.
Counter: is essentially a register that goes through a predetermined
sequence of states.
J.J. Shann 7-6
Lecture Contents
A. Simplest register (7-1)B. Register with parallel load (7-1)C. Shift registers (7-6)
D. Ripple counter (7-6)E. Synchronous binary counters (7-6)F. Other counters (7-6)
J.J. Shann 7-7
A. Simplest Register (7-1)
Simplest register: consists of only flip-flops
w/o any gates. E.g.: a 4-bit register with
asynchronous clear input
J.J. Shann 7-8
B. Register w/ Parallel Load (7-1)
Approach 1: Load control input through the C inputs of the f-fs clock gating
Approach 2: Load control input through the D inputs of the f-fs
Load
J.J. Shann 7-9
Approach 1: Load control input through the C inputs of the f-fs clock gating
prevent the clock from reaching the clock input to the cktif the contents of the reg are to be left unchanged
ClockLoadinputsC +=
* Inserting gates in the clock pulse path produces different propagation delays b/t clock and the inputs of f-fs w/ and w/o clock gating. clock skew
J.J. Shann 7-10
Approach 2: Load control input through the Dinputs of the f-fs
E.g.: 4-bit register w/ parallel load
iii QLoadILoadD +=
(Load)
J.J. Shann 7-11
C. Shift Registers (7-6)
Shift register: a register capable of shifting its binary information in one
or both direction
Simplest shift register: unidirectional
J.J. Shann 7-12
Shift Register w/ Parallel Load
Shift register w/ parallel load: Functional table:
1++= iiii QShiftILoadShiftQLoadShiftD
Clock
J.J. Shann 7-13
E.g.: 4-bit shift register w/ parallel load
1
++
=
i
i
ii
QShiftILoadShift
QLoadShiftD
J.J. Shann 7-14
Bidirectional Shift Register
Bidirectional shift registerdirection = 0 shl
= 1 shr
i i 1i + 1
Di = direction Ai+1 + direction Ai1
SI of shrSO of shl
SO of shrSI of shl
CLK
direction
J.J. Shann 7-15
Bidirectional Shift Reg w/ Parallel Load
Bidirectional shift register w/ parallel load:
Mode control RegisterS1 S0 operation
0 0 No change0 1 Shift down1 0 Shift up1 1 Parallel load
J.J. Shann 7-16
D. Ripple Counters (7-6)
Counter: a register that goes through a prescribed sequence of states
upon the application of input pulses:Input pulses:
may be clock pulses or originate from some external source
Timing: may occur at regular or
irregular intervals of timeThe sequence of states:
may follow the binary number sequence ( Binary counter) orany other sequence of states
J.J. Shann 7-17
Categories of counters:1. Ripple counters:
The flip-flop output transition serves as a source for triggering other flip-flops.
The C input of some or all flip-flops are triggered not by the common clock pulses. (not synchronous)
2. Synchronous counters: (E)The C inputs of all flip-flops receive the common clock.
* T or JK flip-flops
J.J. Shann 7-18
Binary Ripple Counter
Binary count-up counter: E.g.: 4-bit binary count-up ripple counter
0 0 0 0
J.J. Shann 7-19
Observations:FF0: C0 = Clock pulse
D0 = Q0
FF1: C1 = Q0 () Q0 ()D1 = Q1
FF2: C2 = Q1 () Q1 ()D2 = Q2
FF3: C3 = Q2 () Q2 ()D3 = Q3
0 0 0 0
Q0
Q1
Q2
Q3
J.J. Shann 7-20
0 0 0 0
Q0
Q1
Q2
Q3
J.J. Shann 7-21
* Problem of ripple counter:Accumulation of propagation delay
E.g.: 2-bit binary count-up ripple counter
Q0
Q1
Q2
Q3
CP
Q1
Q0
0 1 2 3 0 1
J.J. Shann 7-22
Binary count-down counter: E.g.: 4-bit binary count-down ripple counter
Downward Counting Sequence
1 1 1 1
* Modify the figure in p.7-19:Connect the true output of each f-f to the C input of the next f-f.
J.J. Shann 7-23
Summary: are asynchronous ckts Adv.:
simple hardware
Disadv.: become ckt w/ delay dependence and unreliable oplarge ripple counters can be slow ckts the length of time required for the ripple to finish
J.J. Shann 7-24
E. Synchronous Counters (7-6)
Sync counter: A common clock triggers all flip-flops simultaneously. Symbol:
Design procedure: We can apply the same procedure of sync seq ckts. Sync counter is simpler than general sync seq ckts.
No need to go through a sync seq logic design process.
J.J. Shann 7-25
Example
E.g.: 4-bit sync count-up binary counter w/ count enable line
Approach 1: design procedure of sync seq ckt (Ch6)
CO: is used to extend the counter to more stages
0 0 0 0
ENQQNEQD
=
+=
0
000
EN
)( 011 ENQQD =)( 0122 ENQQQD =
)( 01233 ENQQQQD =
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
0000000000000001
0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 10 0 0 0
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
Presentstate
Nest stateEN = 0 EN = 1
OutputCO
0123 QQQQCO =
J.J. Shann 7-26
Approach 2: observation
0 0 0 0
)( 011 ENQQD =)( 0122 ENQQQD =
)( 01233 ENQQQQD =
0123 QQQQCO =
ENQQNEQD
=
+=
0
000
EN
J.J. Shann 7-27
Approach 3: an incrementer (Ch5) + D f-fs
0 0 0 0
Incrementer
ENQD = 00)( 011 ENQQD =
)( 0122 ENQQQD =
)( 01233 ENQQQQD =
0123 QQQQCO =
D3 D2 D1 D0 = Q3 Q2 Q1 Q0 + EN
J.J. Shann 7-28
Alternative Designs for Binary Counters
Two alternative designs for binary counters: Serial counter: serial gating (p.7-27) Parallel counter: parallel gating
* analogous to the carry lookaheadadder
* analogous to the ripple carry adder
ripple
lookahead
C1
C2
C3
J.J. Shann 7-29
Binary Counter by Using JK Flip-Flops
E.g.: 4-bit count-up binary counter w/ JK f-fsBinary count sequence: 3-bit
A2 A1 A00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 0
J.J. Shann 7-30
A2 A1 A00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 0
J0 = K0 = ENJ1 = K1 = EN A0J2 = K2 = EN A1A0
J3 = K3 = EN A2A1A0
J.J. Shann 7-31
Up-Down Binary Counter
Up-down binary counter: E.g.: 4-bit up-down binary counter
J.J. Shann 7-32
0 0 0 0
ENQD = 00)( 011 ENQQD =
)( 1022 ENQQQD =
)( 21033 ENQQQQD =
1 1 1 1
ENQD = 00)( 011 ENQQD =
)( 1022 ENQQQD =
)( 21033 ENQQQQD =
Up-ward counting: (p.7-24) Down-ward counting:
J.J. Shann 7-33
ENQD = 00))(( 0011 ENSQSQQD +=
))(( 101022 ENSQQSQQQD +=
))(( 21021033 ENSQQQSQQQQD +=
S = 0 up-counting1 down-counting
ENQD = 00)( 011 ENQQD =
)( 1022 ENQQQD =
)( 21033 ENQQQQD =
ENQD = 00)( 011 ENQQD =
)( 1022 ENQQQD =
)( 21033 ENQQQQD =
Up-ward counting:
Down-ward counting:
Up-down counter:
J.J. Shann 7-34
E.g.: 4-bit count-up binary counter w/ parallel load Function table:
Binary Counter w/ Parallel Load
Q3 Q2 Q1 Q0Q3 Q2 Q1 Q0 + 1I3 I2 I1 I0
0 00 11
Q3+ Q2+ Q1+ Q0+Load Count
J.J. Shann 7-35
E.g.: 4-bit count-up binary counter w/ parallel load
w/o parallel load
001
0
ENQD = 00)( 011 ENQQD =
)( 1022 ENQQQD =
)( 21033 ENQQQQD =
J.J. Shann 7-36
E.g.: 4-bit count-up binary counter w/ parallel load
110 D0
Q0
()
w/o parallel
load
J.J. Shann 7-37
Generating Other Count Sequences
Generate any count sequence: E.g.: design a BCD counter by using a counter w/ parallel
load & async clear
J.J. Shann 7-38
J.J. Shann 7-39
F. Other Counters (7-6)
Counters: can be designed to generate any desired sequence of states
Binary counter (D, E)BCD counterDivide-by-N counter: modulo-N counter
a counter that goes through a repeated sequence of Nstates
The sequence may follow the binary count or may be any other arbitrary sequence.
J.J. Shann 7-40
BCD Counter
State diagram & Count sequence: Q8 Q4 Q2 Q10 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 10 0 0 0
J.J. Shann 7-41
BCD ripple counter (p.7-37~7-38)
Q8 Q4 Q2 Q10 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 10 0 0 0
Observations:Q1: C1 = Count
J1 = K1 = 1
Q2: C2 = Q1 ()Q8 = 0, J2 = 1, K2 = 1 (Toggle)Q8 = 1, J2 = 0, K2 = 1 (Reset) J2 = Q8, K2 = 1
Q4: C4 = Q2 ()J1 = K1 = 1
Q8: C8 = Q1 ()Q4Q2 = 1, J2 = 1, K2 = 1 (Toggle)Q4Q2 = 0, J2 = 0, K2 = 1 (Reset) J2 = Q4Q2, K2 = 1
J.J. Shann 7-42
Q8
Q2Q4Q1
Observations:Q1: C1 = Count
J1 = K1 = 1
Q2: C2 = Q1 ()Q8 = 0, J2 = 1, K2 = 1 (Toggle)Q8 = 1, J2 = 0, K2 = 1 (Reset) J2 = Q8, K2 = 1
Q4: C4 = Q2 ()J1 = K1 = 1
Q8: C8 = Q1 ()Q4Q2 = 1, J2 = 1, K2 = 1 (Toggle)Q4Q2 = 0, J2 = 0, K2 = 1 (Reset) J2 = Q4Q2, K2 = 1
J.J. Shann 7-43
Synchronous BCD Counter
Synchronous BCD counter: E.g.: 4-bit sync BCD counter w/ D-type f-f
11 QD =
8122 QQQD =
2144 QQQD =
)( 4218188 QQQQQQD +=
81QQY =
J.J. Shann 7-44
E.g.: 4-bit sync BCD counter w/ T-type f-f
TQ1 = 1, TQ2 = Q8Q1, TQ4 = Q2Q1, TQ8 = Q8Q1 + Q4Q2Q1, y = Q8Q1
J.J. Shann 7-45
Three-decade BCD counter:
J.J. Shann 7-46
Counter w/ Unused States
n flip-flops 2n binary statesUnused states:
states that are not used in specifying the sequential ckt may be treated as dont-care conditions or
may be assigned specific next states
Self-correcting counter: Ensure that when a ckt enter one of its unused states, it
eventually goes into one of the valid states after one or more clock pulses so it can resume normal operation. Analyze the ckt to determine the next state from an
unused state after it is designed.
J.J. Shann 7-47
Example:
Two unused states: 011 & 111
BADA =
CDB =
CBDC =
The simplified f-f input eqs:
J.J. Shann 7-48
The logic diagram & state diagram of the ckt:
* Self-correcting!
AnalysisUnused states
J.J. Shann 7-49
Ring Counter
Ring counter: a circular shift register w/ only one flip-flop being set at
any particular time, all others are cleared(initial value = 1 0 0 0 )
The single bit is shifted from one flip-flop to the next to produce the sequence of timing signals.
E.g.: 4-bit ring counterT0 T1 T2 T31 0 0 00 1 0 00 0 1 00 0 0 11 0 0 0
J.J. Shann 7-50
Application of counters: Counters may be used to generate timing signals to
control the sequence of operations in a digital system.
Approaches for generation of 2n timing signals:1. a shift register (ring-counter) w/ 2n flip-flops2. an n-bit binary counter + an n-to-2n-line decoder
J.J. Shann 7-51
J.J. Shann 7-52
Johnson Counter
Ring counter vs. Switch-tail ring counter: Ring counter:
a k-bit ring counter circulates a single bit among the flip-flops to provide k distinguishable states.
Switch-tail ring counter:is a circular shift register w/ the complement output of the last flip-flop connected to the input of the first flip-flopa k-bit switch-tail ring counterwill go through a sequence of 2k distinguishable states. (initial value = 0 0 0)
J.J. Shann 7-53
E.g.: 4-bit switch-tail ring counter
T210T4T5T311
T601T7T8T100
10110100ABCE
AE
CE
T1...
T8
J.J. Shann 7-54
Johnson counter: a k-bit switch-tail ring counter + 2k 2-input decoding gates provide outputs for 2k timing signals
E.g.: 4-bit Johnson counter
The decoding follows a regular pattern: 2 inputs per decoding gate
4-bit switch-tailring counter
A B C E
8 2-input decoding gates
T8 T7 T6 T5 T4 T3 T2 T1
J.J. Shann 7-55
Disadv. of the switch-tail ring counter: If it finds itself in an unused state, it will persist to
circulate in the invalid states and never find its way to a valid state. Not self-correcting!
Unused states: 800100100010101101001101010111101
J.J. Shann 7-56
Analysis of the ckt:
A+ = DA = E B+ = DB = A C+ = DC = B E+ = DE = C
Binary-coded state tableState diagram
J.J. Shann 7-57
110101110010010010110100
ABCE
110111110010000010110100CE
010111111010000010110100CE
0101101110110000
10110100CE
AB
AB AB
A+ = E B+ = A
C+ = B E+ = C
0000
1000
1100
1110
1111
0111
0011
0001
0010
1001
0100
1010
1101
0110
1011
0101
(Unused states)
J.J. Shann 7-58
110101110010010010110100
ABCE
110111110010000010110100CE
010111111010000010110100CE
0101101110110000
10110100CE
AB
AB AB
A+ = E B+ = A
C+ = (A + C)B E+ = C
0000
1000
1100
1110
1111
0111
0011
0001
0010
1001
0100
1010
1101
0110
1011
0101
* Self-correcting!
J.J. Shann 7-59
Summary: Johnson counters can be constructed for any # of timing
sequences:# of flip-flops = 1/2 (the # of timing signals)# of decoding gates = # of timing signals2-input per gate
J.J. Shann 7-60
7-12 Chapter Summary
Registers Simplest register (7-1) Register with parallel load (7-1) Shift registers (7-6)
Counters Ripple counter (7-6) Synchronous binary counters (7-6) Other counters (7-6)
J.J. Shann 7-61
Homework
Homework: 12, 15Homework: 9, 14, 18, 20, 22
7 ~ 227-6
ExercisesSections
7-1 1 ~ 2
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