Chapter 1 - Binghamton Universityvlsicad.cs.binghamton.edu/~pmadden/courses/cs120/Slides/DDCA_… · Hex Digit Decimal Equivalent Binary Equivalent 0 0 0000 1 1 0001 2 2 0010 3 3

Chapter1<1>

DigitalDesignandComputerArchitecture,2nd Edition

Chapter1

DavidMoneyHarrisandSarahL.Harris

Chapter1<2>

• Background• TheGamePlan• TheArtofManagingComplexity• TheDigitalAbstraction• NumberSystems• LogicGates• LogicLevels• CMOSTransistors• PowerConsumption

Chapter1::Topics

Chapter1<3>

• Microprocessorshaverevolutionizedourworld– Cellphones,Internet,rapidadvancesinmedicine,etc.

• Thesemiconductorindustryhasgrownfrom$21billionin1985to$300billionin2011

Background

Chapter1<4>

• Purposeofcourse:– Understandwhat’sunderthehoodofacomputer– Learntheprinciplesofdigitaldesign– Learntosystematicallydebugincreasinglycomplexdesigns

– Designandbuildamicroprocessor

TheGamePlan

Chapter1<5>

• Abstraction• Discipline• TheThree–y’s

– Hierarchy– Modularity– Regularity

TheArtofManagingComplexity

Chapter1<6>

• Hiding details when they aren’t important

focu

s of

this

cou

rse

programs

device drivers

instructionsregisters

datapathscontrollers

addersmemories

AND gatesNOT gates

amplifiersfilters

transistorsdiodes

electrons

Abstraction

Chapter1<7>

• Intentionally restrict design choices • Example: Digital discipline

– Discrete voltages instead of continuous– Simpler to design than analog circuits – can build more sophisticated

systems– Digital systems replacing analog predecessors:

• i.e., digital cameras, digital television, cell phones, CDs

Discipline

Chapter1<8>

• Hierarchy

• Modularity

• Regularity

TheThree-y’s

Chapter1<9>

• Hierarchy– A system divided into modules and submodules

• Modularity– Having well-defined functions and interfaces

• Regularity– Encouraging uniformity, so modules can be easily reused

TheThree-y’s

Chapter1<10>

• Hierarchy– Three main modules:

lock, stock, and barrel– Submodules of lock:

hammer, flint, frizzen, etc.

Example:TheFlintlockRifle

Chapter1<11>

• Modularity– Function of stock: mount

barrel and lock– Interface of stock: length

and location of mounting pins

• Regularity– Interchangeable parts

Example:TheFlintlockRifle

Chapter1<12>

• Mostphysicalvariablesarecontinuous– Voltageonawire– Frequencyofanoscillation– Positionofamass

• Digitalabstractionconsidersdiscretesubset ofvalues

TheDigitalAbstraction

Chapter1<13>

• DesignedbyCharlesBabbagefrom1834–1871

• Consideredtobethefirstdigitalcomputer

• Builtfrommechanicalgears,whereeachgearrepresentedadiscretevalue(0-9)

• Babbagediedbeforeitwasfinished

TheAnalyticalEngine

Chapter1<14>

• Twodiscretevalues:– 1’sand0’s– 1,TRUE,HIGH– 0,FALSE,LOW

• 1and0:voltagelevels,rotatinggears,fluidlevels,etc.

• Digitalcircuitsusevoltage levelstorepresent1and0

• Bit: Binarydigit

DigitalDiscipline:BinaryValues

Chapter1<15>

• Born to working class parents• Taught himself mathematics and

joined the faculty of Queen’sCollege in Ireland

• Wrote An Investigation of the Lawsof Thought (1854)

• Introduced binary variables• Introduced the three fundamental

logic operations: AND, OR, andNOT

GeorgeBoole,1815-1864

Chapter1<16>

537410 =

10's column

100's column

1000's column

1's column

11012 =

2's column

4's column

8's column

1's column

• Decimal numbers

• Binary numbers

NumberSystems

Chapter1<17>

537410 = 5 × 103 + 3 × 102 + 7 × 101 + 4 × 100five

thousands

10's column

100's column

1000's column

threehundreds

seventens

fourones

1's column

11012 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 = 1310oneeight

2's column

4's column

8's column

onefour

notwo

oneone

1's column

• Decimal numbers

• Binary numbers

NumberSystems

Chapter1<18>

• 20 =• 21 = • 22 =• 23 =• 24 = • 25 = • 26 =• 27 =

• 28 =• 29 = • 210 =• 211 =• 212 = • 213 = • 214 =• 215 =

PowersofTwo

Chapter1<19>

• 20 = 1• 21 = 2• 22 = 4• 23 = 8• 24 = 16• 25 = 32• 26 = 64• 27 = 128• Handy to memorize up to 29

• 28 = 256• 29 = 512• 210 = 1024• 211 = 2048• 212 = 4096• 213 = 8192• 214 = 16384• 215 = 32768

PowersofTwo

Chapter1<20>

• Decimal to binary conversion:– Convert 100112 to decimal

• Decimal to binary conversion:– Convert 4710 to binary

NumberConversion

Chapter1<21>

• Decimal to binary conversion:– Convert 100112 to decimal– 16×1 + 8×0 + 4×0 + 2×1 + 1×1 = 1910

• Decimal to binary conversion:– Convert 4710 to binary– 32×1 + 16×0 + 8×1 + 4×1 + 2×1 + 1×1 = 1011112

NumberConversion

Chapter1<22>

• N-digitdecimalnumber– Howmanyvalues?– Range?– Example:3-digitdecimalnumber:

• N-bitbinarynumber– Howmanyvalues?– Range:– Example:3-digitbinarynumber:

BinaryValuesandRange

Chapter1<23>

• N-digitdecimalnumber– Howmanyvalues?10N– Range?[0,10N - 1]– Example:3-digitdecimalnumber:

• 103 =1000possiblevalues• Range:[0,999]

• N-bitbinarynumber– Howmanyvalues?2N– Range:[0,2N - 1]– Example:3-digitbinarynumber:

• 23 =8possiblevalues• Range:[0,7]=[0002 to1112]

BinaryValuesandRange

Chapter1<24>

Hex Digit Decimal Equivalent Binary Equivalent

0 0

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

9 9

A 10

B 11

C 12

D 13

E 14

F 15

HexadecimalNumbers

Chapter1<25>

Hex Digit Decimal Equivalent Binary Equivalent

0 0 0000

1 1 0001

2 2 0010

3 3 0011

4 4 0100

5 5 0101

6 6 0110

7 7 0111

8 8 1000

9 9 1001

A 10 1010

B 11 1011

C 12 1100

D 13 1101

E 14 1110

F 15 1111

HexadecimalNumbers

Chapter1<26>

• Base 16• Shorthand for binary

HexadecimalNumbers

Chapter1<27>

• Hexadecimal to binary conversion:– Convert 4AF16 (also written 0x4AF) to binary

• Hexadecimal to decimal conversion:– Convert 0x4AF to decimal

HexadecimaltoBinaryConversion

Chapter1<28>

• Hexadecimal to binary conversion:– Convert 4AF16 (also written 0x4AF) to binary– 0100 1010 11112

• Hexadecimal to decimal conversion:– Convert 4AF16 to decimal– 162×4 + 161×10 + 160×15 = 119910

HexadecimaltoBinaryConversion

Chapter1<29>

• Bits

• Bytes&Nibbles

• Bytes

10010110nibble

byte

CEBF9AD7least

significantbyte

mostsignificantbyte

10010110least

significantbit

mostsignificant

bit

Bits,Bytes,Nibbles…

Chapter1<30>

• 210 =1kilo ≈ 1000(1024)• 220 =1mega ≈ 1million(1,048,576)• 230 =1giga ≈ 1billion(1,073,741,824)

LargePowersofTwo

Chapter1<31>

• Whatisthevalueof224?

• Howmanyvaluescana32-bitvariablerepresent?

EstimatingPowersofTwo

Chapter1<32>

• Whatisthevalueof224?24 × 220 ≈16million

• Howmanyvaluescana32-bitvariablerepresent?22 × 230 ≈4billion

EstimatingPowersofTwo

Chapter1<33>

37345168+

10110011+

• Decimal

• Binary

Addition

Chapter1<34>

37345168+8902

carries 11

10110011+1110

11 carries

• Decimal

• Binary

Addition

Chapter1<35>

10010101+

10110110+

• Add the following 4-bit binary numbers

• Add the following 4-bit binary numbers

BinaryAdditionExamples

Chapter1<36>

10010101+1110

1

10110110+10001

111

• Add the following 4-bit binary numbers

• Add the following 4-bit binary numbers

Overflow!

BinaryAdditionExamples

Chapter1<37>

• Digital systems operate on a fixed number of bits

• Overflow: when result is too big to fit in the available number of bits

• See previous example of 11 + 6

Overflow

Chapter1<38>

• Sign/Magnitude Numbers• Two’s Complement Numbers

SignedBinaryNumbers

Chapter1<39>

• 1 sign bit, N-1 magnitude bits• Sign bit is the most significant (left-most) bit

– Positive number: sign bit = 0– Negative number: sign bit = 1

• Example, 4-bit sign/mag representations of ± 6:+6 =- 6 =

• Range of an N-bit sign/magnitude number:

{ }1

1 2 2 1 0

2

0

: , , , ,

( 1) 2n

N N

na i

ii

A a a a a a

A a=

=

L

Sign/MagnitudeNumbers

Chapter1<40>

• 1 sign bit, N-1 magnitude bits• Sign bit is the most significant (left-most) bit

– Positive number: sign bit = 0– Negative number: sign bit = 1

• Example, 4-bit sign/mag representations of ± 6:+6 = 0110- 6 = 1110

• Range of an N-bit sign/magnitude number:[-(2N-1-1), 2N-1-1]

{ }1

1 2 2 1 0

2

0

: , , , ,

( 1) 2n

N N

na i

ii

A a a a a a

A a=

=

L

Sign/MagnitudeNumbers

Chapter1<41>

• Problems:– Addition doesn’t work, for example -6 + 6:

1110 + 011010100 (wrong!)

– Two representations of 0 (± 0):1000 0000

Sign/MagnitudeNumbers

Chapter1<42>

• Don’t have same problems as sign/magnitude numbers:– Addition works– Single representation for 0

Two’sComplementNumbers

Chapter1<43>

( )2

11

0

2 2n

n in i

iA a a

=

= +

• Msb has value of -2N-1

• Most positive 4-bit number:• Most negative 4-bit number:• The most significant bit still indicates the sign

(1 = negative, 0 = positive)• Range of an N-bit two’s comp number:

Two’sComplementNumbers

Chapter1<44>

( )2

11

0

2 2n

n in i

iA a a

=

= +

• Msb has value of -2N-1

• Most positive 4-bit number: 0111• Most negative 4-bit number: 1000• The most significant bit still indicates the sign

(1 = negative, 0 = positive)• Range of an N-bit two’s comp number:

[-(2N-1), 2N-1-1]

Two’sComplementNumbers

Chapter1<45>

• Flip the sign of a two’s complement number• Method:

1. Invert the bits2. Add 1

• Example: Flip the sign of 310 = 00112

“TakingtheTwo’sComplement”

Chapter1<46>

• Flip the sign of a two’s complement number• Method:

1. Invert the bits2. Add 1

• Example: Flip the sign of 310 = 001121. 11002. + 1

1101 = -310

“TakingtheTwo’sComplement”

Chapter1<47>

• Take the two’s complement of 610 = 01102

• What is the decimal value of 10012?

Two’sComplementExamples

Chapter1<48>

• Take the two’s complement of 610 = 011021. 10012. + 1

10102 = -610

• What is the decimal value of the two’s complement number 10012?

1. 01102. + 1

01112 = 710, so 10012 = -710

Two’sComplementExamples

Chapter1<49>

+01101010

+11100011

• Add 6 + (-6) using two’s complement numbers

• Add -2 + 3 using two’s complement numbers

Two’sComplementAddition

Chapter1<50>

+0110101010000

111

+1110001110001

111

• Add 6 + (-6) using two’s complement numbers

• Add -2 + 3 using two’s complement numbers

Two’sComplementAddition

Chapter1<51>Copyright © 2012 Elsevier

• Extend number from N toM bits (M > N) :– Sign-extension– Zero-extension

IncreasingBitWidth

Chapter1<52>

• Sign bit copied to msb’s• Number value is same

• Example 1:– 4-bit representation of 3 = 0011– 8-bit sign-extended value: 00000011

• Example 2:– 4-bit representation of -5 = 1011– 8-bit sign-extended value: 11111011

Sign-Extension

Chapter1<53>

• Zeros copied to msb’s• Value changes for negative numbers

• Example 1:– 4-bit value = 00112 = 310

– 8-bit zero-extended value: 00000011 = 310

• Example 2:– 4-bit value = 1011 = -510

– 8-bit zero-extended value: 00001011 = 1110

Zero-Extension

Chapter1<54>

-8

1000 1001

-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 Two's Complement

10001001101010111100110111101111

00000001 0010 0011 0100 0101 0110 0111

1000 1001 1010 1011 1100 1101 1110 11110000 0001 0010 0011 0100 0101 0110 0111

Sign/Magnitude

Unsigned

Number System RangeUnsigned [0, 2N-1]Sign/Magnitude [-(2N-1-1), 2N-1-1]Two’s Complement [-2N-1, 2N-1-1]

For example, 4-bit representation:

NumberSystemComparison

Chapter1<55>

• Performlogicfunctions:– inversion(NOT),AND,OR,NAND,NOR,etc.

• Single-input:– NOTgate,buffer

• Two-input:– AND,OR,XOR,NAND,NOR,XNOR

• Multiple-input

LogicGates

Chapter1<56>

NOT

Y = A

A Y01

A Y

BUF

Y = A

A Y01

A Y

Single-InputLogicGates

Chapter1<57>

NOT

Y = A

A Y0 11 0

A Y

BUF

Y = A

A Y0 01 1

A Y

Single-InputLogicGates

Chapter1<58>

AND

Y = AB

A B Y0 00 11 01 1

AB Y

OR

Y = A + B

A B Y0 00 11 01 1

AB Y

Two-InputLogicGates

Chapter1<59>

AND

Y = AB

A B Y0 0 00 1 01 0 01 1 1

AB Y

OR

Y = A + B

A B Y0 0 00 1 11 0 11 1 1

AB Y

Two-InputLogicGates

Chapter1<60>

XNOR

Y = A + B

A B Y0 00 11 01 1

AB Y

XOR NAND NOR

Y = A + B Y = AB Y = A + B

A B Y0 00 11 01 1

A B Y0 00 11 01 1

A B Y0 00 11 01 1

AB Y A

B Y AB Y

MoreTwo-InputLogicGates

Chapter1<61>

XNOR

Y = A + B

A B Y0 00 11 01 1

AB Y

XOR NAND NOR

Y = A + B Y = AB Y = A + B

A B Y0 0 00 1 11 0 11 1 0

A B Y0 0 10 1 11 0 11 1 0

A B Y0 0 10 1 01 0 01 1 0

AB Y A

B Y AB Y

1001

MoreTwo-InputLogicGates

Chapter1<62>

NOR3

Y = A+B+C

B C Y0 00 11 01 1

AB YC

A0000

0 00 11 01 1

1111

Multiple-InputLogicGates

AND3

Y = ABC

AB YC

B C Y0 00 11 01 1

A0000

0 00 11 01 1

1111

Chapter1<63>

NOR3

Y = A+B+C

B C Y0 00 11 01 1

AB YC

A0000

0 00 11 01 1

1111

10000000

• Multi-inputXOR:Oddparity

Multiple-InputLogicGates

AND3

Y = ABC

AB YC

B C Y0 00 11 01 1

A0000

0 00 11 01 1

1111

00000001

Chapter1<64>

• Discretevoltagesrepresent1and0• Forexample:

– 0=ground (GND)or0volts– 1=VDD or5volts

• Whatabout4.99volts?Isthata0ora1?• Whatabout3.2volts?

LogicLevels

Chapter1<65>

• Range ofvoltagesfor1and0• Differentrangesforinputsandoutputstoallowfornoise

LogicLevels

Chapter1<66>

WhatisNoise?

Chapter1<67>

• Anythingthatdegradesthesignal– E.g.,resistance,powersupplynoise,couplingtoneighboringwires,etc.

• Example: agate(driver)outputs5Vbut,becauseofresistanceinalongwire,receivergets4.5V

Driver ReceiverNoise

5 V 4.5 V

WhatisNoise?

Chapter1<68>

• Withlogicallyvalidinputs,everycircuitelementmustproducelogicallyvalidoutputs

• Uselimitedrangesofvoltagestorepresentdiscretevalues

TheStaticDiscipline

Chapter1<69>

Driver Receiver

ForbiddenZone

NML

NMH

Input CharacteristicsOutput Characteristics

VO H

VDD

VO L

GND

VIH

VIL

Logic HighInput Range

Logic LowInput Range

Logic HighOutput Range

Logic LowOutput Range

LogicLevels

Chapter1<70>

Driver Receiver

ForbiddenZone

NML

NMH

Input CharacteristicsOutput Characteristics

VO H

VDD

VO L

GND

VIH

VIL

Logic HighInput Range

Logic LowInput Range

Logic HighOutput Range

Logic LowOutput Range

NMH = VOH – VIH

NML = VIL – VOL

NoiseMargins

Chapter1<71>

VDD

V(A)

V(Y)

VOH VDD

VOL

VIL, VIH

0

A Y

VDD

V(A)

V(Y)

VOH

VDD

VOL

VIL VIH

Unity GainPoints

Slope = 1

0VDD / 2

Ideal Buffer: Real Buffer:

NMH = NML = VDD/2 NMH , NML < VDD/2

DCTransferCharacteristics

Chapter1<72>

ForbiddenZone

NML

NMH

Input CharacteristicsOutput CharacteristicsVDD

VO L

GND

VIHVIL

VO H

A Y

VDD

V(A)

V(Y)

VOHVDD

VOL

VIL VIH

Unity GainPoints

Slope = 1

0

DCTransferCharacteristics

Chapter1<73>

• In1970’sand1980’s,VDD =5V• VDD hasdropped

– Avoidfryingtinytransistors– Savepower

• 3.3V,2.5V,1.8V,1.5V,1.2V,1.0V,…• Becarefulconnectingchipswithdifferentsupplyvoltages

Chipsoperatebecausetheycontainmagicsmoke

Proof:– ifthemagicsmokeisletout,thechipstopsworking

VDD Scaling

Chapter1<74>

Logic Family VDD VIL VIH VOL VOHTTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4

CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84

LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4

LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7

LogicFamilyExamples

Chapter1<75>

g

s

d

g = 0

s

d

g = 1

s

d

OFF ON

• Logic gates built from transistors• 3-ported voltage-controlled switch

– 2 ports connected depending on voltage of 3rd– d and s are connected (ON) when g is 1

Transistors

Chapter1<76>

• Nicknamed “Mayor of Silicon Valley”

• Cofounded Fairchild Semiconductor in 1957

• Cofounded Intel in 1968• Co-invented the integrated

circuit

RobertNoyce,1927-1990

Chapter1<77>

Silicon Lattice

Si SiSi

Si SiSi

Si SiSi

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-

Free electron Free hole

n-Type p-Type

• Transistors built from silicon, a semiconductor• Pure silicon is a poor conductor (no free charges)• Doped silicon is a good conductor (free charges)

– n-type (free negative charges, electrons)– p-type (free positive charges, holes)

Silicon

Chapter1<78>

n

p

gatesource drain

substrate

SiO2

nMOS

Polysilicon

n

gate

source drain

• Metal oxide silicon (MOS) transistors: – Polysilicon (used to be metal) gate– Oxide (silicon dioxide) insulator– Doped silicon

MOSTransistors

Chapter1<79>

n

p

gatesource drain

substrate

n n

p

gatesource drain

substrate

n

GND

GNDVDD

GND

+++++++- - - - - - -

channel

Gate = 0

OFF (no connection between source and drain)

Gate = 1

ON (channel between source and drain)

Transistors:nMOS

Chapter1<80>

• pMOS transistorisopposite– ONwhenGate=0– OFFwhenGate=1

SiO2

n

gatesource drainPolysilicon

p p

gate

source drain

substrate

Transistors:pMOS

Chapter1<81>

gs

d

g = 0

s

d

g = 1

s

d

gd

s

d

s

d

s

nMOS

pMOS

OFF ON

ON OFF

TransistorFunction

Chapter1<82>

• nMOS:passgood0’s,soconnectsourcetoGND

• pMOS:passgood1’s,soconnectsourcetoVDD

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetwork

TransistorFunction

Chapter1<83>

VDD

A Y

GND

N1

P1

NOT

Y = A

A Y0 11 0

A Y

A P1 N1 Y

0

1

CMOSGates:NOTGate

Chapter1<84>

VDD

A Y

GND

N1

P1

NOT

Y = A

A Y0 11 0

A Y

A P1 N1 Y

0 ON OFF 1

1 OFF ON 0

CMOSGates:NOTGate

Chapter1<85>

A

B

Y

N2N1

P2 P1

NAND

Y = AB

A B Y0 0 10 1 11 0 11 1 0

AB Y

A B P1 P2 N1 N2 Y0 00 11 01 1

CMOSGates:NANDGate

Chapter1<86>

A

B

Y

N2N1

P2 P1

NAND

Y = AB

A B Y0 0 10 1 11 0 11 1 0

AB Y

A B P1 P2 N1 N2 Y0 0 ON ON OFF OFF 10 1 ON OFF OFF ON 11 0 OFF ON ON OFF 11 1 OFF OFF ON ON 0

CMOSGates:NANDGate

Chapter1<87>

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetwork

CMOSGateStructure

Chapter1<88>

How do you build a three-input NOR gate?

NORGate

Chapter1<89>

B

CY

A

NOR3Gate

Chapter1<90>

How do you build a two-input AND gate?

OtherCMOSGates

Chapter1<91>

AB Y

AND2Gate

Chapter1<92>

• nMOS pass1’spoorly• pMOS pass0’spoorly• Transmissiongateisabetterswitch

– passesboth0and1well

• WhenEN =1,theswitchisON:– EN =0andA isconnectedtoB

• WhenEN =0,theswitchisOFF:– A isnotconnectedtoB

A B

EN

EN

TransmissionGates

Chapter1<93>

• Replacepull-upnetworkwithweak pMOStransistorthatisalwayson

• pMOS transistor:pullsoutputHIGHonlywhennMOS networknotpullingitLOW

Y

inputs nMOSpull-downnetwork

weak

Pseudo-nMOS Gates

Chapter1<94>

Pseudo-nMOS NOR4

A BY

weak

C D

Pseudo-nMOS Example

Chapter1<95>

• Cofounded Intel in 1968 with Robert Noyce.

• Moore’s Law:number of transistors on a computer chip doubles every year (observed in 1965)

• Since 1975, transistor counts have doubled every two years.

GordonMoore,1929-

Chapter1<96>

• “Iftheautomobilehadfollowedthesamedevelopmentcycleasthecomputer,aRolls-Roycewouldtodaycost$100,getonemillionmilestothegallon,andexplodeonceayear...”

– RobertCringley

Moore’sLaw

Chapter1<97>

• Power=Energyconsumedperunittime– Dynamicpowerconsumption– Staticpowerconsumption

PowerConsumption

Chapter1<98>

• Powertochargetransistorgatecapacitances– Energyrequiredtochargeacapacitance,C,toVDD isCVDD

2

– Circuitrunningatfrequencyf:transistorsswitch(from1to0orviceversa)atthatfrequency

– Capacitorischargedf/2timespersecond(dischargingfrom1to0isfree)

• Dynamicpowerconsumption:

Pdynamic =½CVDD2f

DynamicPowerConsumption

Chapter1<99>

• Powerconsumedwhennogatesareswitching

• Causedbythequiescentsupplycurrent,IDD(alsocalledtheleakagecurrent)

• Staticpowerconsumption:

Pstatic =IDDVDD

StaticPowerConsumption

Chapter1<100>

• Estimatethepowerconsumptionofawirelesshandheldcomputer– VDD =1.2V– C =20nF– f=1GHz– IDD =20mA

PowerConsumptionExample

Chapter1<101>

• Estimatethepowerconsumptionofawirelesshandheldcomputer– VDD =1.2V– C =20nF– f=1GHz– IDD =20mA

P =½CVDD2f +IDDVDD

=½(20nF)(1.2V)2(1GHz)+(20mA)(1.2V)

=(14.4+0.024)W≈14.4W

PowerConsumptionExample