Transcript
8-1 Chapter 8 - Buses and Peripherals
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Computer Architecture andOrganization
Miles Murdocca and Vincent Heuring
Chapter 8 – Buses andPeripherals
8-2 Chapter 8 - Buses and Peripherals
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Chapter Contents8.1 Parallel Bus Architectures8.2 Bridge-Based Bus Architectures8.3 Internal Communication Methodologies8.4 Case Study: Communication on the Intel Pentium Architecture8.5 Serial Bus Architectures8.6 Mass Storage8.7 RAID – Redundant Arrays of Inexpensive Disks8.8 Input Devices8.9 Output Devices8.10 Case Study: Graphics Processing Unit8.11 Case Study: How a Virus Infects a Machine
8-3 Chapter 8 - Buses and Peripherals
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Simple Bus Architecture• A simplified motherboard of a personal computer (top view):
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Simplified Illustration of a Bus
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
100 MHz Bus Clock
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
The Synchronous Bus• Timing diagram for a synchronous memory read (adapted from
[Tanenbaum, 1999]).
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
The Asynchronous Bus• Timing diagram for asynchronous memory read (adapted from
[Tanenbaum, 1999]).
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Bus Arbitration
(a) Simple centralizedbus arbitration; (b)centralized arbitrationwith priority levels; (c)fully centralized busarbitration; (d)decentralized busarbitration. (Source:adapted from[Tanenbaum, 1999].)
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
BridgeBased
Bus Arch-itecture
Bridging with dualPentium processors.
Source:http://www.intel.com.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Programmed I/OFlowchart for aDisk Transfer
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
InterruptDriven I/O
Flowchart fora Disk
Transfer
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
DMA Transfer from Disk to MemoryBypasses the CPU
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
DMA Flowchart for a Disk Transfer
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Intel Memory and I/O Address Spaces
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Standard Intel Pentium Read andWrite Bus Cycles
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Intel Pentium Burst Read Bus Cycle
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
IntelPentium
Hold-HoldAcknow-
ledge BusCycle
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
RS-232• The RS-232 standard commonly uses 9-pin and 25-pin connectors, but
uses others as well (see the figure).
• RS-232 is used for slow-bit-rate devices such as mice, keyboards, andnon-graphics terminals.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
USB and FirewireUniversal Serial Bus (USB) and IEEE 1394 (Firewire) are groups ofstandards for interconnecting peripheral devices. USB 2.0 supports datatransfer rates up to 480 Mbps, with as many as 127 devices connected toa single host controller through special hub devices in a tree-like manner.
Firewire is similar to USB but has traditionally been faster, up to 800 Mbps.A key advantage of Firewire is isochronous data transfer, in which acontinuous, guaranteed data transfer is supported at a predetermined rate.This makes Firewire attractive for digital video and digital audio.
(left) USB hub; (middle) USB cable; (right) Firewire cable.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
A Magnetic Disk with Three Platters
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Manchester Encoding• (a) Straight amplitude (NRZ) encoding of ASCII ‘F’; (b) Manchester
encoding of ASCII ‘F’.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Organization of a Disk Platter with a1:2 Interleave Factor
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
MasterControlBlock
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Magnetic Tape• A portion of a magnetic tape.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Digital Audio Tape (DAT)• Digital audio tape (DAT) formatting supports high densities, on the
order of 72 GB for a small 73 mm × 54 mm profile. The read / writehead is placed at an angle to the tape as shown in the figure, allowingdata to be criss-crossed over the same area, using opposite polaritieswhich maintains separation of the bits.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Spiral Format for Compact Disk• Unlike a magnetic disk in which all of the sectors on concentric tracks
are lined up like a sliced pie (where the disk rotation uses constantangular velocity), a CD is arranged in a spiral format (using constantlinear velocity). The speed of rotation is adjusted so that the diskmoves more slowly when the head is at the edge than when it is at thecenter.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Redundant Arrays of InexpensiveDisks (RAID)
• RAID level 0 – striped disk array without fault tolerance.
• RAID level 1 – mirroring and duplexing.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
RAID (Continued)• RAID level 2 – bit-level striping with Hamming Code ECC.
• RAID level 3 – parallel transfer with parity.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
RAID (Continued)• RAID level 4 – independent data disks with shared parity disk.
• RAID level 5 – independent data disks with distributed parity blocks.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
RAID (Continued)• RAID level 6 – independent data disks with two independent
distributed parity schemes.
• RAID level 7 – asynchronous cached striping with dedicated parity.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
RAID (Continued)• RAID level 10 – very high reliability combined with high performance.
• RAID level 53 – high I/O rates and data transfer performance.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
ECMA-23 Keyboard Layout• Keyboard layout for the ECMA-23 Standard (2nd ed.). Shift keys are
frequently placed in the B row.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
The Dvorak Keyboard Layout
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Tablet with Puck
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Mouse and TrackballA mechanical mouse (left), a three-button trackball (center), and an
optical mouse (right).
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Touch Sensitive Pen-based Display• Pen-based personal digital assistants (PDAs) use a passive matrix in
which the pen can be anything that induces pressure on the screen.• Two transparent
conducting layers areplaced on the screen,separated by spacer dots.When the user appliespressure to the top layer,as with a stylus or simply afinger, the top and bottomlayers make contact. Theinduced voltage at theedges varies according tothe position of the stylus.
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Joystick• A joystick with a selection button and a rotatable rod:
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Laser Printer• Schematic of a laser printer (adapted from [Tanenbaum, 1999]).
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Cathode Ray Tube• A CRT with a single electron gun:
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Display Controller• Display controller
for a 1024×768color monitor(adapted from[Hamacher et al.,1990]).
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Active Matrix Color Liquid CrystalDisplay
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Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
Matrix Parhelia-512 GPU