Cbfox/pub/ANITA_Trigger... · 2014. 1. 8. · l4a_rf_sync l4a_rfin rf_ch0 sheet-5 j1-1 j1-2 j1-3 j1-4 j1-5 1 2 r15a 2k 1 2 r16a 2k 1 2 r17a 1k 1 2 x1a sm_led
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<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
1
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4A_TX_P
L4A_TX_N
L4A_CLK_P
L4A_CLK_N
L4A_SST_P
L4A_SST_N
L4A_WR_EN
L4A_WCLK_P
L4A_WCLK_N
L4A_TIMING_P
L4A_TIMING_N
L4A_SCL
L4A_SDA
L4A_RF
L4F_RF_SYNC
L4A_RX_P
L4A_RX_N
TOP_CH0
SHEET-2
L4B_TX_P
L4B_TX_N
L4B_CLK_P
L4B_CLK_N
L4B_SST_P
L4B_SST_N
L4B_WR_EN
L4B_WCLK_P
L4B_WCLK_N
L4B_TIMING_P
L4B_TIMING_N
L4B_SCL
L4B_SDA
L4B_RF
L4E_RF_SYNC
L4B_RX_P
L4B_RX_N
TOP_CH1
SHEET-6
L4C_TX_P
L4C_TX_N
L4C_CLK_P
L4C_CLK_N
L4C_SST_P
L4C_SST_N
L4C_WR_EN
L4C_WCLK_P
L4C_WCLK_N
L4C_TIMING_P
L4C_TIMING_N
L4C_SCL
L4C_SDA
L4C_RF
L4D_RF_SYNC
L4C_RX_P
L4C_RX_N
TOP_CH2
SHEET-10
L4D_TX_P
L4D_TX_N
L4D_CLK_P
L4D_CLK_N
L4D_SST_P
L4D_SST_N
L4D_WR_EN
L4D_WCLK_P
L4D_WCLK_N
L4D_TIMING_P
L4D_TIMING_N
L4D_SCL
L4D_SDA
L4D_RF
L4C_RF_SYNC
L4D_RX_P
L4D_RX_N
TOP_CH3
SHEET-14
L4E_TX_P
L4E_TX_N
L4E_CLK_P
L4E_CLK_N
L4E_SST_P
L4E_SST_N
L4E_WR_EN
L4E_WCLK_P
L4E_WCLK_N
L4E_TIMING_P
L4E_TIMING_N
L4E_SDA
L4E_SCL
L4E_RF
L4B_RF_SYNC
L4E_RX_P
L4E_RX_N
TOP_CH4
SHEET-18
L4F_TX_P
L4F_TX_N
L4F_CLK_P
L4F_CLK_N
L4F_SST_P
L4F_SST_N
L4F_WR_EN
L4F_WCLK_N
L4F_WCLK_P
L4F_TIMING_P
L4F_TIMING_N
L4F_SCL
L4F_SDA
L4F_RF
L4A_RF_SYNC
L4F_RX_P
L4F_RX_N
TOP_CH5
SHEET-22
L4G_TX_P
L4G_TX_N
L4G_CLK_P
L4G_CLK_N
L4G_SST_P
L4G_SST_N
L4G_WR_EN
L4G_WCLK_P
L4G_WCLK_N
L4G_TIMING_P
L4G_TIMING_N
L4G_SCL
L4G_SDA
L4G_RF
L4L_RF_SYNC
L4G_RX_P
L4G_RX_N
TOP_CH6
SHEET-26
L4H_TX_P
L4H_TX_N
L4H_CLK_P
L4H_CLK_N
L4H_SST_P
L4H_SST_N
L4H_WR_EN
L4H_WCLK_P
L4H_WCLK_N
L4H_TIMING_P
L4H_TIMING_N
L4H_SCL
L4H_SDA
L4H_RF
L4K_RF_SYNC
L4H_RX_P
L4H_RX_N
TOP_CH7
SHEET-30
L4I_TX_P
L4I_TX_N
L4I_CLK_P
L4I_CLK_N
L4I_SST_P
L4I_SST_N
L4I_WR_EN
L4I_WCLK_P
L4I_WCLK_N
L4I_TIMING_P
L4I_TIMING_N
L4I_SCL
L4I_SDA
L4I_RF
L4J_RF_SYNC
L4I_RX_P
L4I_RX_N
TOP_CH8
SHEET-34
L4J_TX_P
L4J_TX_N
L4J_CLK_P
L4J_CLK_N
L4J_SST_P
L4J_SST_N
L4J_WR_EN
L4J_WCLK_P
L4J_WCLK_N
L4J_TIMING_P
L4J_TIMING_N
L4J_SDA
L4J_SCL
L4J_RF
L4I_RF_SYNC
L4J_RX_P
L4J_RX_N
TOP_CH9
SHEET-38
L4K_TX_P
L4K_TX_N
L4K_CLK_P
L4K_CLK_N
L4K_SST_P
L4K_SST_N
L4K_WR_EN
L4K_WCLK_P
L4K_WCLK_N
L4K_TIMING_P
L4K_TIMING_N
L4K_SDA
L4K_SCL
L4K_RF
L4H_RF_SYNC
L4K_RX_P
L4K_RX_N
TOP_C10
SHEET-42
L4L_TX_P
L4L_TX_N
L4L_CLK_P
L4L_CLK_N
L4L_SST_P
L4L_SST_N
L4L_WR_EN
L4L_WCLK_P
L4L_WCLK_N
L4L_TIMING_P
L4L_TIMING_N
L4L_SCL
L4L_SDA
L4L_RF
L4G_RF_SYNC
L4L_RX_P
L4L_RX_N
TOP_C11
SHEET-46
J13
SMA_CONN
J14
SMA_CONN
J15
SMA_CONN
J16
SMA_CONN
J17
SMA_CONN
J18
SMA_CONN
J19
SMA_CONN
J20
SMA_CONN
J21
SMA_CONN
J22
SMA_CONN
J23
SMA_CONN
J24
SMA_CONN
1
X1
MTG_HOLE
1
X2
MTG_HOLE
1
X7
MTG_HOLE
1
X8
MTG_HOLE
1
X9
MTG_HOLE
1
X10
MTG_HOLE
1
X11
MTG_HOLE
1
X12
MTG_HOLE
RF_SYNC_1
RF_SYNC_2
L4A_RF_SYNC
L4B_RF_SYNC
L4C_RF_SYNC
L4D_RF_SYNC
L4E_RF_SYNC
L4F_RF_SYNC
L4G_RF_SYNC
L4H_RF_SYNC
L4I_RF_SYNC
L4J_RF_SYNC
L4K_RF_SYNC
L4L_RF_SYNC
SYNC
SHEET-50
J12
SMA_CONN
J29
SMA_CONN
L4A_TIMING_P
L4A_TIMING_N
L4A_WCLK_P
L4A_WCLK_N
L4A_WR_EN
L4A_TX_P
L4A_TX_N
L4A_RX_P
L4A_RX_N
L4A_CLK_P
L4A_CLK_N
L4B_RX_P
L4B_RX_N
L4B_TX_P
L4B_TX_N
L4B_CLK_P
L4B_CLK_N
PCI_DEVSEL
PCI_FRAME
PCI_GNT
PCI_IDSEL
PCI_CLK
PCI_INTA
PCI_IRDY
PCI_PAR
PCI_PERR
PCI_REQ
PCI_RST
PCI_SERR
PCI_STOP
PCI_TRDY
L4C_TX_P
L4C_TX_N
L4C_RX_P
L4C_RX_N
L4C_CLK_P
L4C_CLK_N
L4D_RX_P
L4D_RX_N
L4D_TX_P
L4D_TX_N
L4D_CLK_P
L4D_CLK_N
L4E_RX_P
L4E_RX_N
L4E_TX_P
L4E_TX_N
L4E_CLK_P
L4E_CLK_N
L4F_RX_P
L4F_RX_N
L4F_TX_P
L4F_TX_N
L4F_CLK_P
L4F_CLK_N
L4G_TX_P
L4G_TX_N
L4G_RX_P
L4G_RX_N
L4G_CLK_P
L4G_CLK_N
L4H_RX_P
L4H_RX_N
L4H_CLK_P
L4H_CLK_N
L4H_TX_P
L4H_TX_N
L4I_RX_P
L4I_RX_N
L4I_TX_P
L4I_TX_N
L4I_CLK_P
L4I_CLK_N
L4J_RX_P
L4J_RX_N
L4J_TX_P
L4J_TX_N
L4J_CLK_P
L4J_CLK_N
L4K_RX_P
L4K_RX_N
L4K_TX_P
L4K_TX_N
L4K_CLK_P
L4K_CLK_N
L4L_RX_P
L4L_RX_N
L4L_TX_P
L4L_TX_N
L4L_CLK_P
L4L_CLK_N
L4A_SCL
L4A_SDA
L4B_WR_EN
L4B_WCLK_P
L4B_WCLK_N
L4B_TIMING_P
L4B_TIMING_N
L4B_SCL
L4B_SDA
L4C_TIMING_P
L4C_TIMING_N
L4C_WCLK_P
L4C_WCLK_N
L4C_WR_EN
L4C_SCL
L4C_SDA
L4D_TIMING_P
L4D_TIMING_N
L4D_WCLK_P
L4D_WCLK_N
L4D_WR_EN
L4D_SCL
L4D_SDA
L4E_TIMING_P
L4E_TIMING_N
L4E_WCLK_P
L4E_WCLK_N
L4E_WR_EN
L4F_TIMING_P
L4F_TIMING_N
L4F_WCLK_N
L4F_WCLK_P
L4F_WR_EN
L4E_SDA
L4E_SCL
L4F_SCL
L4F_SDA
L4G_TIMING_P
L4G_TIMING_N
L4G_WCLK_P
L4G_WCLK_N
L4G_WR_EN
L4G_SCL
L4G_SDA
L4H_TIMING_P
L4H_TIMING_N
L4H_WCLK_P
L4H_WCLK_N
L4H_WR_EN
L4H_SCL
L4H_SDA
L4I_TIMING_P
L4I_TIMING_N
L4I_WCLK_P
L4I_WCLK_N
L4I_WR_EN
L4I_SCL
L4I_SDA
L4J_TIMING_P
L4J_TIMING_N
L4J_WCLK_N
L4J_WCLK_P
L4J_WR_EN
L4J_SDA
L4J_SCL
L4K_TIMING_P
L4K_TIMING_N
L4K_WCLK_P
L4K_WCLK_N
L4K_WR_EN
L4L_WCLK_P
L4L_WCLK_N
L4K_SDA
L4K_SCL
L4L_TIMING_P
L4L_TIMING_N
L4L_WR_EN
L4L_SCL
L4L_SDA
TD_P7
TD_N7
TD_N6
TD_P6
TD_P5
TD_N5
TD_N3
TD_P3
TD_P4
TD_N4
TD_P2
TD_N2
TD_P1
TD_N1
TD_P0
TD_N0
FPG
A_SST_P
FPG
A_SST_N
FPG
A_TU
RF_SST_P
FPG
A_TU
RF_SST_N
LO
CAL_CLK
LO
CAL_O
SC_EN
SREQ
TREQ
PPS_P
PPS_N
SCLK_P
SCLK_N
TCLK_P
TCLK_N
HOLD1
HOLD0
HOLD3
HOLD2
TMGT_TX_N
TMGT_TX_P
TMGT_RX_P
TMGT_RX_N
TMGT_CLK_P
TMGT_CLK_N
FPGA_DONE
TCK_2V5
TDO_2V5
TDI_2V5
FPGA_PROGRAM_B
FPG
A_SST_SEL
UC_SDA
UC_SCL
TMS_2V5
FPGA_INIT_B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
MO
N0
MO
N1
MO
N2
MO
N3
MO
N4
LED
0
LED
1
LED
2
LED
3
FPGA-IO
SHEET-52
J31-1
J31-2
J31-3
J31-4
J31-5
J31-6
FPGA_SST_P
FPGA_SST_N
LAB4_SST_P
LAB4_SST_N
FPGA_SST_SEL
LOCAL_OSC_EN
FPGA_TURF_SST_P
FPGA_TURF_SST_N
L4L_SST_P
L4L_SST_N
L4K_SST_P
L4K_SST_N
L4J_SST_P
L4J_SST_N
L4I_SST_P
L4I_SST_N
L4H_SST_P
L4H_SST_N
L4G_SST_P
L4G_SST_N
L4F_SST_P
L4F_SST_N
L4E_SST_P
L4E_SST_N
L4D_SST_P
L4D_SST_N
L4C_SST_P
L4C_SST_N
L4B_SST_P
L4B_SST_N
L4A_SST_P
L4A_SST_N
LOCAL_CLK
CLOCK_FANOUT
SHEET-53
LED0
LED3
LED1
LED2
FPGA_LED
SHEET-58
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
2
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4A_RFIN
L4A_WR_EN
L4A_WCLK_P
L4A_WCLK_N
L4A_SST_P
L4A_SST_N
L4A_VBS
L4A_VBIAS
L4A_VBIAS2
L4A_ISEL
L4A_SBBIAS
L4A_CMPBIAS
L4A_VPED_BUFF
L4A_VDLYP
L4A_VDLYN
L4A_ROVDD
L4A_CLK_P
L4A_CLK_N
L4A_TX_N
L4A_TX_P
L4A_SPI_NCS
L4A_SPI_MISO
L4A_SPI_MOSI
L4A_SPI_SCK
L4A_CDONE
ICE40_RESET
L4A_TIMING_THR
L4A_SRCLK_P
L4A_SRCLK_N
L4A_RX_P
L4A_RX_N
L4A_MON0
L4A_TIMING_P
L4A_TIMING_N
LAB4_CH0
SHEET-3
L4A_SCL
L4A_SDA
L4A_VBIAS2
L4A_ISEL
L4A_SBBIAS
L4A_CMPBIAS
L4A_VBS
L4A_TIMING_THR
L4A_VDLYP
L4A_VDLYN
L4A_ROVDD
L4A_VPED_BUFF
L4A_VBIAS
DACS_CH0
SHEET-4
L4A_RF
L4A_RF_SYNC
L4A_RFIN
RF_CH0
SHEET-5
J1-1
J1-2
J1-3
J1-4
J1-5
1
2
R15A
2k
1
2
R16A
2k
1
2
R17A
1k
1
2
X1A
SM
_LED
1
2
R18A
1k
L4A_RX_P
L4A_RX_N
L4A_TX_P
L4A_TX_N
L4A_CLK_P
L4A_CLK_N
L4A_SST_P
L4A_SST_N
L4A_WR_EN
L4A_WCLK_P
L4A_WCLK_N
L4A_SRCLK_P
L4A_SRCLK_N
L4A_TIMING_P
L4A_TIMING_N
L4A_SCL
L4A_SDA
L4A_RF
L4A_RF_SYNC
2.5V
2.5V
2.5V
2.5V
ICE40_RESET
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
3
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4A
LAB4B
C2A
100 p
F
C30A
100 uF
RAMPA
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2A
MIC5323-6P
C6A
4.7 uF
C1A
0.1 uF
1
2
R13A
10k
1
2
R14A
10k
C9A
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1A-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1A-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1A-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1A-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1A-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1A-F
1
2
R1A
100
1
2
R2A
150
1
2
R4A
150
1
2
R3A
140
1
2
R5A
100
1
2
R6A
150
1
2
R7A
150
1
2
R8A
140
1
2
R9A
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3A
25LD040
C18A
0.1 uF
C19A
0.1 uF
C20A
0.1 uF
C24A
0.1 uF
C25A
0.1 uF
C26A
0.1 uF
C27A
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2A
LMH7220
C23A
0.1 uF
1
2
R21A
100
1
2
R22A
100
1
2
R23A
100
1
2
R12A
50
GND
PWR
2
3
1
V3A
1.2V
C8A
1 uF
C7A
1 uF
C10A
0.1 uF
C11A
0.1 uF
C12A
0.1 uF
C13A
0.1 uF
C14A
0.1 uF
C15A
0.1 uF
C16A
4.7 uF
C17A
0.1 uF
L4A_2.5V
L4A_RFIN
L4A_WR[0:4]
L4A_WR0
L4A_WR1
L4A_WR2
L4A_WR3
L4A_WR4
L4A_WR_EN
L4A_WCLK_P
L4A_WCLK_N
L4A_2.5V
3.3V_FILT_ABC
L4A_2.5V
L4A_SST_P
L4A_SST_N
L4A_VBS
L4A_VBIAS
L4A_VBIAS2
L4A_ISEL
L4A_SBBIAS
L4A_CMPBIAS
L4A_VPED_BUFF
L4A_VDLYP
L4A_VDLYN
L4A_ROVDD
L4A_CLK_P
L4A_CLK_N
L4A_TX_N
L4A_TX_P
2.5V
L4A_RX_P
L4A_RX_N
L4A_RD[0:4]
L4A_RD0
L4A_RD1
L4A_RD2
L4A_RD3
L4A_RD4
L4A_ICE_SRCLK_P
L4A_ICE_SRCLK_N
L4A_TX_N
L4A_TX_P
2.5V
L4A_1.2V
2.5V
2.5V
2.5V
2.5V
L4A_RD0
L4A_RD2
L4A_RD4
L4A_RD3
L4A_RD1
L4A_SCLK
L4A_SIN
L4A_UPDATE
L4A_PT
L4A_PCLK
L4A_RD_EN
L4A_SEL_ANY
L4A_RAMP
L4A_REGCLR
L4A_DOE_P
L4A_DOE_N
L4A_SS_INCR
L4A_CLR
L4A_SHOUT
L4A_1.2V
L4A_SPI_NCS
L4A_SPI_MISO
L4A_SPI_MOSI
L4A_SPI_SCK
L4A_CDONE
ICE40_RESET
L4A_MON0
L4A_CLK_N
L4A_CLK_N
L4A_SRCLK_P
L4A_SRCLK_N
L4A_SR_SEL
3.3V_FILT_ABC
L4A_TIMING_P
L4A_TIMING_N
L4A_TIMING_THR
L4A_MONTIMING_TO_COMP
L4A_SST_P
L4A_WCLK_P
L4A_SRCLK_P
L4A_SST_N
L4A_WCLK_N
L4A_SRCLK_N
3.3V_FILT_ABC
L4A_1.2V
L4A_2.5V
L4A_2.5V
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
4
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4A
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5A
LTC2635_EP
-
+
2
1
3
U6A
LT6003
1
2
R19A
16k
1
2
R20A
16k
C3A
0.1
uF
C4A
0.1 uF
C5A
0.1 uF
C22A
0.1 uF
C21A
0.1 uF
VPEDA
C28A
0.1 uF
3.3V_FILT_ABC
L4A_VBIAS2
L4A_ISEL
L4A_SBBIAS
L4A_CMPBIAS
L4A_VBS
L4A_TIMING_THR
L4A_SCL
L4A_SDA
L4A_SCL
L4A_SDA
L4A_VDLYP
L4A_VDLYN
L4A_ROVDD
L4A_VPED_BUFF
L4A_VPED
L4A_VBIAS
3.3V_FILT_ABC
3.3V_FILT_ABC
L4A_2.5V
3.3V_FILT_ABC
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
5
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Pass
Block
1
3
4
2
F2A
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Block
Pass
4
2
1
3
F1A
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7A
RF_SPLITTER
4
3
1
2
U8A
EXB24AT2
0 dB
2
1
R11A
475
C29A
0.1
uF
3
4
1
2
6
T1A
TCD-XX-4X+
1
2
R10A
50
C31A
470 pF
L4A_RFIN
L4A_RF
L4A_RF_SYNC
L4A_RFP_IN
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
6
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
L4B_RFIN
L4B_WR_EN
L4B_WCLK_P
L4B_WCLK_N
L4B_SST_P
L4B_SST_N
L4B_VBS
L4B_VBIAS
L4B_VBIAS2
L4B_ISEL
L4B_SBBIAS
L4B_CMPBIAS
L4B_VPED_BUFF
L4B_VDLYP
L4B_VDLYN
L4B_ROVDD
L4B_CLK_P
L4B_CLK_N
L4B_TX_N
L4B_TX_P
L4B_SPI_NCS
L4B_SPI_MISO
L4B_SPI_MOSI
L4B_SPI_SCK
L4A_CDONE
L4A_CRESET
L4B_TIMING_THR
L4B_SRCLK_P
L4B_SRCLK_N
L4B_RX_P
L4B_RX_N
L4B_MON0
L4B_TIMING_P
L4B_TIMING_N
LAB4_CH1
SHEET-7
L4B_SCL
L4B_SDA
L4B_VBIAS2
L4B_ISEL
L4B_SBBIAS
L4B_CMPBIAS
L4B_VBS
L4B_TIMING_THR
L4A_VDLYP
L4B_VDLYN
L4B_ROVDD
L4B_VPED_BUFF
L4B_VBIAS
DACS_CH1
SHEET-8
L4B_RF
L4B_RF_SYNC
L4B_RFIN
RF_CH1
SHEET-9
J2-1
J2-2
J2-3
J2-4
J2-5
1
2
R15B
2k
1
2
R16B
2k
1
2
R17B
1k
1
2
X1B
SM
_LED
L4B_RX_P
L4B_RX_N
L4B_TX_P
L4B_TX_N
L4B_CLK_P
L4B_CLK_N
L4B_SST_P
L4B_SST_N
L4B_WR_EN
L4B_WCLK_P
L4B_WCLK_N
L4B_SRCLK_P
L4B_SRCLK_N
L4B_TIMING_P
L4B_TIMING_N
L4B_SCL
L4B_SDA
L4B_RF
L4B_RF_SYNC
L4B_SPI_MOSI
L4B_SPI_NCS
L4B_SPI_SCK
L4B_SPI_MISO
2.5V
2.5V
2.5V
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
7
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4B
LAB4B
C2B
100 p
F
C30B
100 uF
RAMPB
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2B
MIC5323-6P
C6B
4.7 uF
C1B
0.1 uF
1
2
R13B
10k
1
2
R14B
10k
C9B
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1B-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1B-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1B-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1B-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1B-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1B-F
1
2
R1B
100
1
2
R2B
150
1
2
R4B
150
1
2
R3B
140
1
2
R5B
100
1
2
R6B
150
1
2
R7B
150
1
2
R8B
140
1
2
R9B
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3B
25LD040
C18B
0.1 uF
C19B
0.1 uF
C20B
0.1 uF
C24B
0.1 uF
C25B
0.1 uF
C26B
0.1 uF
C27B
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2B
LMH7220
C23B
0.1 uF
1
2
R21B
100
1
2
R22B
100
1
2
R23B
100
1
2
R12B
50
PWR
GND
2
3
1
V3B
1.2V
C8B
1 uF
C7B
1 uF
C10B
0.1 uF
C11B
0.1 uF
C12B
0.1 uF
C13B
0.1 uF
C14B
0.1 uF
C15B
0.1 uF
C16B
4.7 uF
C17B
0.1 uF
L4B_2.5V
L4B_RFIN
L4B_WR[0:4]
L4B_WR0
L4B_WR1
L4B_WR2
L4B_WR3
L4B_WR4
L4B_WR_EN
L4B_WCLK_P
L4B_WCLK_N
L4B_2.5V
3.3V_FILT_ABC
L4B_2.5V
L4B_SST_P
L4B_SST_N
L4B_VBS
L4B_VBIAS
L4B_VBIAS2
L4B_ISEL
L4B_SBBIAS
L4B_CMPBIAS
L4B_VPED_BUFF
L4B_VDLYP
L4B_VDLYN
L4B_ROVDD
L4B_CLK_P
L4B_CLK_N
L4B_TX_N
L4B_TX_P
2.5V
L4B_RX_P
L4B_RX_N
L4B_RD[0:4]
L4B_RD0
L4B_RD1
L4B_RD2
L4B_RD3
L4B_RD4
L4B_ICE_SRCLK_P
L4B_ICE_SRCLK_N
L4B_TX_N
L4B_TX_P
2.5V
L4B_1.2V
2.5V
2.5V
2.5V
2.5V
L4B_RD0
L4B_RD2
L4B_RD4
L4B_RD3
L4B_RD1
L4B_SCLK
L4B_SIN
L4B_UPDATE
L4B_PT
L4B_PCLK
L4B_RD_EN
L4B_SEL_ANY
L4B_RAMP
L4B_REGCLR
L4B_DOE_P
L4B_DOE_N
L4B_SS_INCR
L4B_CLR
L4B_SHOUT
L4B_1.2V
L4B_SPI_NCS
L4B_SPI_MISO
L4B_SPI_MOSI
L4B_SPI_SCK
L4B_CDONE
ICE40_RESET
L4B_MON0
L4B_CLK_N
L4B_CLK_N
L4B_SRCLK_P
L4B_SRCLK_N
L4B_SR_SEL
3.3V_FILT_ABC
L4B_TIMING_P
L4B_TIMING_N
L4B_TIMING_THR
L4B_MONTIMING_TO_COMP
L4B_SST_P
L4B_WCLK_P
L4B_SRCLK_P
L4B_SST_N
L4B_WCLK_N
L4B_SRCLK_N
3.3V_FILT_ABC
L4B_1.2V
L4B_2.5V
L4B_2.5V
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
8
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4B
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5B
LTC2635_EP
+
-
2
1
3
U6B
LT6003
1
2
R19B
16k
1
2
R20B
16k
C3B
0.1
uF
C4B
0.1 uF
C5B
0.1 uF
C22B
0.1 uF
C21B
0.1 uF
VPEDB
C28B
0.1 uF
3.3V_FILT_ABC
L4B_VBIAS2
L4B_ISEL
L4B_SBBIAS
L4B_CMPBIAS
L4B_VBS
L4B_TIMING_THR
L4B_SCL
L4B_SDA
L4B_SCL
L4B_SDA
L4B_VDLYP
L4B_VDLYN
L4B_ROVDD
L4B_VPED_BUFF
L4B_VPED
L4B_VBIAS
3.3V_FILT_ABC
3.3V_FILT_ABC
L4B_2.5V
3.3V_FILT_ABC
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
9
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
Block
Pass
1
3
4
2
F2B
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Pass
Block
4
2
1
3
F1B
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7B
RF_SPLITTER
4
3
1
2
U8B
EXB24AT2
0 dB
2
1
R11B
475
C29B
0.1
uF
3
4
1
2
6
T1B
TCD-XX-4X+
1
2
R10B
50
C31B
470 pF
L4B_RFIN
L4B_RF
L4B_RF_SYNC
L4B_RFP_IN
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
10
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
L4A_RFIN
L4A_WR_EN
L4A_WCLK_P
L4A_WCLK_N
L4A_SST_P
L4A_SST_N
L4A_VBS
L4A_VBIAS
L4A_VBIAS2
L4A_ISEL
L4A_SBBIAS
L4A_CMPBIAS
L4A_VPED_BUFF
L4A_VDLYP
L4A_VDLYN
L4A_ROVDD
L4A_CLK_P
L4A_CLK_N
L4A_TX_N
L4A_TX_P
L4C_SPI_NCS
L4C_SPI_MISO
L4C_SPI_MOSI
L4C_SPI_SCK
L4A_CDONE
L4A_CRESET
L4A_TIMING_THR
L4A_SRCLK_P
L4A_SRCLK_N
L4A_RX_P
L4A_RX_N
L4C_MON0
L4A_TIMING_P
L4A_TIMING_N
LAB4_CH2
SHEET-11
L4C_SCL
L4C_SDA
L4A_VBIAS2
L4A_ISEL
L4A_SBBIAS
L4A_CMPBIAS
L4A_VBS
L4A_TIMING_THR
L4A_VDLYP
L4A_VDLYN
L4A_ROVDD
L4A_VPED_BUFF
L4A_VBIAS
DACS_CH2
SHEET-12
L4A_RF
L4A_RF_SYNC
L4A_RFIN
RF_CH2
SHEET-13
J3-1
J3-2
J3-3
J3-4
J3-5
1
2
R15C
2k
1
2
R16C
2k
1
2
R17C
1k
1
2
X1C
SM
_LED
L4A_RX_P
L4A_RX_N
L4A_TX_P
L4A_TX_N
L4A_CLK_P
L4A_CLK_N
L4A_SST_P
L4A_SST_N
L4A_WR_EN
L4A_WCLK_P
L4A_WCLK_N
L4A_SRCLK_P
L4A_SRCLK_N
L4A_TIMING_P
L4A_TIMING_N
L4C_SCL
L4C_SDA
L4A_RF
L4A_RF_SYNC
L4C_SPI_MOSI
L4C_SPI_NCS
L4C_SPI_SCK
L4C_SPI_MISO
2.5V
2.5V
2.5V
L4C_MON0
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
11
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4C
LAB4B
C2C
100 p
F
C30C
100 uF
RAMPC
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2C
MIC5323-6P
C6C
4.7 uF
C1C
0.1 uF
1
2
R13C
10k
1
2
R14C
10k
C9C
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1C-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1C-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1C-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1C-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1C-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1C-F
1
2
R1C
100
1
2
R2C
150
1
2
R4C
150
1
2
R3C
140
1
2
R5C
100
1
2
R6C
150
1
2
R7C
150
1
2
R8C
140
1
2
R9C
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3C
25LD040
C18C
0.1 uF
C19C
0.1 uF
C20C
0.1 uF
C24C
0.1 uF
C25C
0.1 uF
C26C
0.1 uF
C27C
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2C
LMH7220
C23C
0.1 uF
1
2
R21C
100
1
2
R22C
100
1
2
R23C
100
1
2
R12C
50
PWR
GND
2
3
1
V3C
1.2V
C8C
1 uF
C7C
1 uF
C10C
0.1 uF
C11C
0.1 uF
C12C
0.1 uF
C13C
0.1 uF
C14C
0.1 uF
C15C
0.1 uF
C16C
4.7 uF
C17C
0.1 uF
L4C_2.5V
L4C_RFIN
L4C_WR[0:4]
L4C_WR0
L4C_WR1
L4C_WR2
L4C_WR3
L4C_WR4
L4C_WR_EN
L4C_WCLK_P
L4C_WCLK_N
L4C_2.5V
3.3V_FILT_ABC
L4C_2.5V
L4C_SST_P
L4C_SST_N
L4C_VBS
L4C_VBIAS
L4C_VBIAS2
L4C_ISEL
L4C_SBBIAS
L4C_CMPBIAS
L4C_VPED_BUFF
L4C_VDLYP
L4C_VDLYN
L4C_ROVDD
L4C_CLK_P
L4C_CLK_N
L4C_TX_N
L4C_TX_P
2.5V
L4C_RX_P
L4C_RX_N
L4C_RD[0:4]
L4C_RD0
L4C_RD1
L4C_RD2
L4C_RD3
L4C_RD4
L4C_ICE_SRCLK_P
L4C_ICE_SRCLK_N
L4C_TX_N
L4C_TX_P
2.5V
L4C_1.2V
2.5V
2.5V
2.5V
2.5V
L4C_RD0
L4C_RD2
L4C_RD4
L4C_RD3
L4C_RD1
L4C_SCLK
L4C_SIN
L4C_UPDATE
L4C_PT
L4C_PCLK
L4C_RD_EN
L4C_SEL_ANY
L4C_RAMP
L4C_REGCLR
L4C_DOE_P
L4C_DOE_N
L4C_SS_INCR
L4C_CLR
L4C_SHOUT
L4C_1.2V
L4C_SPI_NCS
L4C_SPI_MISO
L4C_SPI_MOSI
L4C_SPI_SCK
L4C_CDONE
ICE40_RESET
L4C_MON0
L4C_CLK_N
L4C_CLK_N
L4C_SRCLK_P
L4C_SRCLK_N
L4C_SR_SEL
3.3V_FILT_ABC
L4C_TIMING_P
L4C_TIMING_N
L4C_TIMING_THR
L4C_MONTIMING_TO_COMP
L4C_SST_P
L4C_WCLK_P
L4C_SRCLK_P
L4C_SST_N
L4C_WCLK_N
L4C_SRCLK_N
3.3V_FILT_ABC
L4C_1.2V
L4C_2.5V
L4C_2.5V
L4C_RD_EN
L4C_RAMP
L4C_CLR
L4C_PT
L4C_PCLK
L4C_SCLK
L4C_SIN
L4C_UPDATE
L4C_REGCLR
L4C_SS_INCR
L4C_SEL_ANY
L4C_SHOUT
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
12
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4C
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5C
LTC2635_EP
+
-
2
1
3
U6C
LT6003
1
2
R19C
16k
1
2
R20C
16k
C3C
0.1
uF
C4C
0.1 uF
C5C
0.1 uF
C22C
0.1 uF
C21C
0.1 uF
VPEDC
C28C
0.1 uF
3.3V_FILT_ABC
L4C_VBIAS2
L4C_ISEL
L4C_SBBIAS
L4C_CMPBIAS
L4C_VBS
L4C_TIMING_THR
L4C_SCL
L4C_SDA
L4C_SCL
L4C_SDA
L4C_VDLYP
L4C_VDLYN
L4C_ROVDD
L4C_VPED_BUFF
L4C_VPED
L4C_VBIAS
3.3V_FILT_ABC
3.3V_FILT_ABC
L4C_2.5V
3.3V_FILT_ABC
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
13
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
Block
Pass
1
3
4
2
F2C
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Pass
Block
4
2
1
3
F1C
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7C
RF_SPLITTER
4
3
1
2
U8C
EXB24AT2
0 dB
2
1
R11C
475
C29C
0.1
uF
3
4
1
2
6
T1C
TCD-XX-4X+
1
2
R10C
50
C31C
470 pF
L4C_RFIN
L4C_RF
L4C_RF_SYNC
L4C_RFP_IN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
14
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4D_RFIN
L4D_WR_EN
L4D_WCLK_P
L4D_WCLK_N
L4D_SST_P
L4D_SST_N
L4D_VBS
L4D_VBIAS
L4D_VBIAS2
L4D_ISEL
L4D_SBBIAS
L4D_CMPBIAS
L4D_VPED_BUFF
L4D_VDLYP
L4D_VDLYN
L4D_ROVDD
L4D_CLK_P
L4D_CLK_N
L4D_TX_N
L4D_TX_P
L4D_SPI_NCS
L4D_SPI_MISO
L4D_SPI_MOSI
L4D_SPI_SCK
L4A_CDONE
L4A_CRESET
L4D_TIMING_THR
L4D_SRCLK_P
L4D_SRCLK_N
L4D_RX_P
L4D_RX_N
L4D_MON0
L4D_TIMING_P
L4D_TIMING_N
LAB4_CH3
SHEET-15
L4D_SCL
L4D_SDA
L4D_VBIAS2
L4D_ISEL
L4D_SBBIAS
L4D_CMPBIAS
L4D_VBS
L4D_TIMING_THR
L4D_VDLYP
L4D_VDLYN
L4D_ROVDD
L4D_VPED_BUFF
L4D_VBIAS
DACS_CH3
SHEET-16
L4D_RF
L4D_RF_SYNC
L4D_RFIN
RF_CH3
SHEET-17
J4-1
J4-2
J4-3
J4-4
J4-5
1
2
R15D
2k
1
2
R16D
2k
1
2
R17D
1k
1
2
X1D
SM
_LED
L4D_RX_P
L4D_RX_N
L4D_TX_P
L4D_TX_N
L4D_CLK_P
L4D_CLK_N
L4D_SST_P
L4D_SST_N
L4D_WR_EN
L4D_WCLK_P
L4D_WCLK_N
L4D_SRCLK_P
L4D_SRCLK_N
L4D_TIMING_P
L4D_TIMING_N
L4D_SCL
L4D_SDA
L4D_RF
L4D_RF_SYNC
L4D_SPI_MOSI
L4D_SPI_NCS
L4D_SPI_SCK
L4D_SPI_MISO
2.5V
2.5V
2.5V
L4D_MON0
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
15
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4D
LAB4B
C2D
100 p
F
C30D
100 uF
RAMPA2
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2D
MIC5323-6P
C6D
4.7 uF
C1D
0.1 uF
1
2
R13D
10k
1
2
R14D
10k
C9D
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1D-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1D-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1D-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1D-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1D-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1D-F
1
2
R1D
100
1
2
R2D
150
1
2
R4D
150
1
2
R3D
140
1
2
R5D
100
1
2
R6D
150
1
2
R7D
150
1
2
R8D
140
1
2
R9D
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3D
25LD040
C18D
0.1 uF
C19D
0.1 uF
C20D
0.1 uF
C24D
0.1 uF
C25D
0.1 uF
C26D
0.1 uF
C27D
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2D
LMH7220
C23D
0.1 uF
1
2
R21D
100
1
2
R22D
100
1
2
R23D
100
1
2
R12D
50
GND
PWR
2
3
1
V3D
1.2V
C8D
1 uF
C7D
1 uF
C10D
0.1 uF
C11D
0.1 uF
C12D
0.1 uF
C13D
0.1 uF
C14D
0.1 uF
C15D
0.1 uF
C16D
4.7 uF
C17D
0.1 uF
L4D_2.5V
L4D_RFIN
L4D_WR[0:4]
L4D_WR0
L4D_WR1
L4D_WR2
L4D_WR3
L4D_WR4
L4D_WR_EN
L4D_WCLK_P
L4D_WCLK_N
L4D_2.5V
3.3V_FILT_DEF
L4D_2.5V
L4D_SST_P
L4D_SST_N
L4D_VBS
L4D_VBIAS
L4D_VBIAS2
L4D_ISEL
L4D_SBBIAS
L4D_CMPBIAS
L4D_VPED_BUFF
L4D_VDLYP
L4D_VDLYN
L4D_ROVDD
L4D_CLK_P
L4D_CLK_N
L4D_TX_N
L4D_TX_P
2.5V
L4D_RX_P
L4D_RX_N
L4D_RD[0:4]
L4D_RD0
L4D_RD1
L4D_RD2
L4D_RD3
L4D_RD4
L4D_ICE_SRCLK_P
L4D_ICE_SRCLK_N
L4D_TX_N
L4D_TX_P
2.5V
L4D_1.2V
2.5V
2.5V
2.5V
2.5V
L4D_RD0
L4D_RD2
L4D_RD4
L4D_RD3
L4D_RD1
L4D_SCLK
L4D_SIN
L4D_UPDATE
L4D_PT
L4D_PCLK
L4D_RD_EN
L4D_SEL_ANY
L4D_RAMP
L4D_REGCLR
L4D_DOE_P
L4D_DOE_N
L4D_SS_INCR
L4D_CLR
L4D_SHOUT
L4D_1.2V
L4D_SPI_NCS
L4D_SPI_MISO
L4D_SPI_MOSI
L4D_SPI_SCK
L4D_CDONE
ICE40_RESET
L4D_MON0
L4D_CLK_N
L4D_CLK_N
L4D_SRCLK_P
L4D_SRCLK_N
L4D_SR_SEL
3.3V_FILT_DEF
L4D_TIMING_P
L4D_TIMING_N
L4D_TIMING_THR
L4D_MONTIMING_TO_COMP
L4D_SST_P
L4D_WCLK_P
L4D_SRCLK_P
L4D_SST_N
L4D_WCLK_N
L4D_SRCLK_N
3.3V_FILT_DEF
L4D_1.2V
L4D_2.5V
L4D_2.5V
L4D_RD_EN
L4D_RAMP
L4D_CLR
L4D_PT
L4D_PCLK
L4D_SCLK
L4D_SIN
L4D_UPDATE
L4D_REGCLR
L4D_SS_INCR
L4D_SEL_ANY
L4D_SHOUT
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
16
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4D
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5D
LTC2635_EP
-
+
2
1
3
U6D
LT6003
1
2
R19D
16k
1
2
R20D
16k
C3D
0.1
uF
C4D
0.1 uF
C5D
0.1 uF
C22D
0.1 uF
C21D
0.1 uF
VPEDD
C28D
0.1 uF
3.3V_FILT_DEF
L4D_VBIAS2
L4D_ISEL
L4D_SBBIAS
L4D_CMPBIAS
L4D_VBS
L4D_TIMING_THR
L4D_SCL
L4D_SDA
L4D_SCL
L4D_SDA
L4D_VDLYP
L4D_VDLYN
L4D_ROVDD
L4D_VPED_BUFF
L4D_VPED
L4D_VBIAS
3.3V_FILT_DEF
3.3V_FILT_DEF
L4D_2.5V
3.3V_FILT_DEF
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
17
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Pass
Block
1
3
4
2
F2D
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Block
Pass
4
2
1
3
F1D
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7D
RF_SPLITTER
4
3
1
2
U8D
EXB24AT2
0 dB
2
1
R11D
475
C29D
0.1
uF
3
4
1
2
6
T1D
TCD-XX-4X+
1
2
R10D
50
C31D
470 pF
L4D_RFIN
L4D_RF
L4D_RF_SYNC
L4D_RFP_IN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
18
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4E_RFIN
L4E_WR_EN
L4E_WCLK_P
L4E_WCLK_N
L4E_SST_P
L4E_SST_N
L4E_VBS
L4E_VBIAS
L4E_VBIAS2
L4E_ISEL
L4E_SBBIAS
L4E_CMPBIAS
L4E_VPED_BUFF
L4E_VDLYP
L4E_VDLYN
L4E_ROVDD
L4E_CLK_P
L4E_CLK_N
L4E_TX_N
L4E_TX_P
L4E_SPI_NCS
L4E_SPI_MISO
L4E_SPI_MOSI
L4E_SPI_SCK
L4E_CDONE
L4E_CRESET
L4E_TIMING_THR
L4E_SRCLK_P
L4E_SRCLK_N
L4E_RX_P
L4E_RX_N
L4E_MON0
L4E_TIMING_P
L4E_TIMING_N
LAB4_CH4
SHEET-19
L4E_SCL
L4E_SDA
L4E_VBIAS2
L4E_ISEL
L4E_SBBIAS
L4E_CMPBIAS
L4E_VBS
L4E_TIMING_THR
L4E_VDLYP
L4E_VDLYN
L4E_ROVDD
L4E_VPED_BUFF
L4E_VBIAS
DACS_CH4
SHEET-20
L4E_RF
L4E_RF_SYNC
L4E_RFIN
RF_CH4
SHEET-21
J5-1
J5-2
J5-3
J5-4
J5-5
1
2
R15E
2k
1
2
R16E
2k
1
2
R17E
1k
1
2
X1E
SM
_LED
L4E_RX_P
L4E_RX_N
L4E_TX_P
L4E_TX_N
L4E_CLK_P
L4E_CLK_N
L4E_SST_P
L4E_SST_N
L4E_WR_EN
L4E_WCLK_P
L4E_WCLK_N
L4E_SRCLK_P
L4E_SRCLK_N
L4E_TIMING_P
L4E_TIMING_N
L4E_SCL
L4E_SDA
L4E_RF
L4E_RF_SYNC
L4E_SPI_MOSI
L4E_SPI_NCS
L4E_SPI_SCK
L4E_SPI_MISO
2.5V
2.5V
2.5V
L4E_MON0
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
19
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4E
LAB4B
C2E
100 p
F
C30E
100 uF
RAMPE
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2E
MIC5323-6P
C6E
4.7 uF
C1E
0.1 uF
1
2
R13E
10k
1
2
R14E
10k
C9E
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1E-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1E-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1E-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1E-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1E-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1E-F
1
2
R1E
100
1
2
R2E
150
1
2
R4E
150
1
2
R3E
140
1
2
R5E
100
1
2
R6E
150
1
2
R7E
150
1
2
R8E
140
1
2
R9E
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3E
25LD040
C18E
0.1 uF
C19E
0.1 uF
C20E
0.1 uF
C24E
0.1 uF
C25E
0.1 uF
C26E
0.1 uF
C27E
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2E
LMH7220
C23E
0.1 uF
1
2
R21E
100
1
2
R22E
100
1
2
R23E
100
1
2
R12E
50
GND
PWR
2
3
1
V3E
1.2V
C8E
1 uF
C7E
1 uF
C10E
0.1 uF
C11E
0.1 uF
C12E
0.1 uF
C13E
0.1 uF
C14E
0.1 uF
C15E
0.1 uF
C16E
4.7 uF
C17E
0.1 uF
L4E_2.5V
L4E_RFIN
L4E_WR[0:4]
L4E_WR0
L4E_WR1
L4E_WR2
L4E_WR3
L4E_WR4
L4E_WR_EN
L4E_WCLK_P
L4E_WCLK_N
L4E_2.5V
3.3V_FILT_DEF
L4E_2.5V
L4E_SST_P
L4E_SST_N
L4E_VBS
L4E_VBIAS
L4E_VBIAS2
L4E_ISEL
L4E_SBBIAS
L4E_CMPBIAS
L4E_VPED_BUFF
L4E_VDLYP
L4E_VDLYN
L4E_ROVDD
L4E_CLK_P
L4E_CLK_N
L4E_TX_N
L4E_TX_P
2.5V
L4E_RX_P
L4E_RX_N
L4E_RD[0:4]
L4E_RD0
L4E_RD1
L4E_RD2
L4E_RD3
L4E_RD4
L4E_ICE_SRCLK_P
L4E_ICE_SRCLK_N
L4E_TX_N
L4E_TX_P
2.5V
L4E_1.2V
2.5V
2.5V
2.5V
2.5V
L4E_RD0
L4E_RD2
L4E_RD4
L4E_RD3
L4E_RD1
L4E_SCLK
L4E_SIN
L4E_UPDATE
L4E_PT
L4E_PCLK
L4E_RD_EN
L4E_SEL_ANY
L4E_RAMP
L4E_REGCLR
L4E_DOE_P
L4E_DOE_N
L4E_SS_INCR
L4E_CLR
L4E_SHOUT
L4E_1.2V
L4E_SPI_NCS
L4E_SPI_MISO
L4E_SPI_MOSI
L4E_SPI_SCK
L4E_CDONE
ICE40_RESET
L4E_MON0
L4E_CLK_N
L4E_CLK_N
L4E_SRCLK_P
L4E_SRCLK_N
L4E_SR_SEL
3.3V_FILT_DEF
L4E_TIMING_P
L4E_TIMING_N
L4E_TIMING_THR
L4E_MONTIMING_TO_COMP
L4E_SST_P
L4E_WCLK_P
L4E_SRCLK_P
L4E_SST_N
L4E_WCLK_N
L4E_SRCLK_N
3.3V_FILT_DEF
L4E_1.2V
L4E_2.5V
L4E_2.5V
L4E_RD_EN
L4E_CLR
L4E_RAMP
L4E_PT
L4E_PCLK
L4E_SCLK
L4E_SIN
L4E_UPDATE
L4E_REGCLR
L4E_SS_INCR
L4E_SEL_ANY
L4E_SHOUT
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
20
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4E
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5E
LTC2635_EP
-
+
2
1
3
U6E
LT6003
1
2
R19E
16k
1
2
R20E
16k
C3E
0.1
uF
C4E
0.1 uF
C5E
0.1 uF
C22E
0.1 uF
C21E
0.1 uF
VPEDE
C28E
0.1 uF
3.3V_FILT_DEF
L4E_VBIAS2
L4E_ISEL
L4E_SBBIAS
L4E_CMPBIAS
L4E_VBS
L4E_TIMING_THR
L4E_SCL
L4E_SDA
L4E_SCL
L4E_SDA
L4E_VDLYP
L4E_VDLYN
L4E_ROVDD
L4E_VPED_BUFF
L4E_VPED
L4E_VBIAS
3.3V_FILT_DEF
3.3V_FILT_DEF
L4E_2.5V
3.3V_FILT_DEF
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
21
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Pass
Block
1
3
4
2
F2E
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Block
Pass
4
2
1
3
F1E
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7E
RF_SPLITTER
4
3
1
2
U8E
EXB24AT2
0 dB
2
1
R11E
475
C29E
0.1
uF
3
4
1
2
6
T1E
TCD-XX-4X+
1
2
R10E
50
C31E
470 pF
L4E_RFIN
L4E_RF
L4E_RF_SYNC
L4E_RFP_IN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
22
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4F_RFIN
L4F_WR_EN
L4F_WCLK_P
L4F_WCLK_N
L4F_SST_P
L4F_SST_N
L4F_VBS
L4F_VBIAS
L4F_VBIAS2
L4F_ISEL
L4F_SBBIAS
L4F_CMPBIAS
L4F_VPED_BUFF
L4F_VDLYP
L4F_VDLYN
L4F_ROVDD
L4F_CLK_P
L4F_CLK_N
L4F_TX_N
L4F_TX_P
L4F_SPI_NCS
L4F_SPI_MISO
L4F_SPI_MOSI
L4F_SPI_SCK
L4F_CDONE
L4F_CRESET
L4F_TIMING_THR
L4F_SRCLK_P
L4F_SRCLK_N
L4F_RX_P
L4F_RX_N
L4F_MON0
L4F_TIMING_P
L4F_TIMING_N
LAB4_CH5
SHEET-23
L4F_SCL
L4F_SDA
L4F_VBIAS2
L4F_ISEL
L4F_SBBIAS
L4F_CMPBIAS
L4F_VBS
L4F_TIMING_THR
L4F_VDLYP
L4F_VDLYN
L4F_ROVDD
L4F_VPED_BUFF
L4F_VBIAS
DACS_CH5
SHEET-24
L4F_RF
L4F_RF_SYNC
L4F_RFIN
RF_CH5
SHEET-25
J6-1
J6-2
J6-3
J6-4
J6-5
1
2
R15F
2k
1
2
R16F
2k
1
2
R17F
1k
1
2
X1F
SM
_LED
L4F_RX_P
L4F_RX_N
L4F_TX_P
L4F_TX_N
L4F_CLK_P
L4F_CLK_N
L4F_SST_P
L4F_SST_N
L4F_WR_EN
L4F_WCLK_P
L4F_WCLK_N
L4F_SRCLK_P
L4F_SRCLK_N
L4F_TIMING_P
L4F_TIMING_N
L4F_SCL
L4F_SDA
L4F_RF
L4F_RF_SYNC
L4F_SPI_MOSI
L4F_SPI_NCS
L4F_SPI_SCK
L4F_SPI_MISO
2.5V
2.5V
2.5V
L4F_MON0
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
23
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4F
LAB4B
C2F
100 p
F
C30F
100 uF
RAMPF
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2F
MIC5323-6P
C6F
4.7 uF
C1F
0.1 uF
1
2
R13F
10k
1
2
R14F
10k
C9F
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1F-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1F-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1F-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1F-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1F-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1F-F
1
2
R1F
100
1
2
R2F
150
1
2
R4F
150
1
2
R3F
140
1
2
R5F
100
1
2
R6F
150
1
2
R7F
150
1
2
R8F
140
1
2
R9F
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3F
25LD040
C18F
0.1 uF
C19F
0.1 uF
C20F
0.1 uF
C24F
0.1 uF
C25F
0.1 uF
C26F
0.1 uF
C27F
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2F
LMH7220
C23F
0.1 uF
1
2
R21F
100
1
2
R22F
100
1
2
R23F
100
1
2
R12F
50
GND
PWR
2
3
1
V3F
1.2V
C8F
1 uF
C7F
1 uF
C10F
0.1 uF
C11F
0.1 uF
C12F
0.1 uF
C13F
0.1 uF
C14F
0.1 uF
C15F
0.1 uF
C16F
4.7 uF
C17F
0.1 uF
L4F_2.5V
L4F_RFIN
L4F_WR[0:4]
L4F_WR0
L4F_WR1
L4F_WR2
L4F_WR3
L4F_WR4
L4F_WR_EN
L4F_WCLK_P
L4F_WCLK_N
L4F_2.5V
3.3V_FILT_DEF
L4F_2.5V
L4F_SST_P
L4F_SST_N
L4F_VBS
L4F_VBIAS
L4F_VBIAS2
L4F_ISEL
L4F_SBBIAS
L4F_CMPBIAS
L4F_VPED_BUFF
L4F_VDLYP
L4F_VDLYN
L4F_ROVDD
L4F_CLK_P
L4F_CLK_N
L4F_TX_N
L4F_TX_P
2.5V
L4F_RX_P
L4F_RX_N
L4F_RD[0:4]
L4F_RD0
L4F_RD1
L4F_RD2
L4F_RD3
L4F_RD4
L4F_ICE_SRCLK_P
L4F_ICE_SRCLK_N
L4F_TX_N
L4F_TX_P
2.5V
L4F_1.2V
2.5V
2.5V
2.5V
2.5V
L4F_RD0
L4F_RD2
L4F_RD4
L4F_RD3
L4F_RD1
L4F_SCLK
L4F_SIN
L4F_UPDATE
L4F_PT
L4F_PCLK
L4F_RD_EN
L4F_SEL_ANY
L4F_RAMP
L4F_REGCLR
L4F_DOE_P
L4F_DOE_N
L4F_SS_INCR
L4F_CLR
L4F_SHOUT
L4F_1.2V
L4F_SPI_NCS
L4F_SPI_MISO
L4F_SPI_MOSI
L4F_SPI_SCK
L4F_CDONE
ICE40_RESET
L4F_MON0
L4F_CLK_N
L4F_CLK_N
L4F_SRCLK_P
L4F_SRCLK_N
L4F_SR_SEL
3.3V_FILT_DEF
L4F_TIMING_P
L4F_TIMING_N
L4F_TIMING_THR
L4F_MONTIMING_TO_COMP
L4F_SST_P
L4F_WCLK_P
L4F_SRCLK_P
L4F_SST_N
L4F_WCLK_N
L4F_SRCLK_N
3.3V_FILT_DEF
L4F_1.2V
L4F_2.5V
L4F_2.5V
L4F_RD_EN
L4F_RAMP
L4F_CLR
L4F_PT
L4F_PCLK
L4F_SCLK
L4F_SIN
L4F_UPDATE
L4F_REGCLR
L4F_SS_INCR
L4F_SEL_ANY
L4F_DOE_N
L4F_SHOUT
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
24
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4F
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5F
LTC2635_EP
-
+
2
1
3
U6F
LT6003
1
2
R19F
16k
1
2
R20F
16k
C3F
0.1
uF
C4F
0.1 uF
C5F
0.1 uF
C22F
0.1 uF
C21F
0.1 uF
VPEDF
C28F
0.1 uF
3.3V_FILT_DEF
L4F_VBIAS2
L4F_ISEL
L4F_SBBIAS
L4F_CMPBIAS
L4F_VBS
L4F_TIMING_THR
L4F_SCL
L4F_SDA
L4F_SCL
L4F_SDA
L4F_VDLYP
L4F_VDLYN
L4F_ROVDD
L4F_VPED_BUFF
L4F_VPED
L4F_VBIAS
3.3V_FILT_DEF
3.3V_FILT_DEF
L4F_2.5V
3.3V_FILT_DEF
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
25
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Pass
Block
1
3
4
2
F2F
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Block
Pass
4
2
1
3
F1F
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7F
RF_SPLITTER
4
3
1
2
U8F
EXB24AT2
0 dB
2
1
R11F
475
C29F
0.1
uF
3
4
1
2
6
T1F
TCD-XX-4X+
1
2
R10F
50
C31F
470 pF
L4F_RFIN
L4F_RF
L4F_RF_SYNC
L4F_RFP_IN
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
26
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
L4G_RFIN
L4G_WR_EN
L4G_WCLK_P
L4G_WCLK_N
L4G_SST_P
L4G_SST_N
L4G_VBS
L4G_VBIAS
L4G_VBIAS2
L4G_ISEL
L4G_SBBIAS
L4G_CMPBIAS
L4G_VPED_BUFF
L4G_VDLYP
L4G_VDLYN
L4G_ROVDD
L4G_CLK_P
L4G_CLK_N
L4G_TX_N
L4G_TX_P
L4G_SPI_NCS
L4G_SPI_MISO
L4G_SPI_MOSI
L4G_SPI_SCK
L4G_CDONE
L4G_CRESET
L4G_TIMING_THR
L4G_SRCLK_P
L4G_SRCLK_N
L4G_RX_P
L4G_RX_N
L4G_MON0
L4G_TIMING_P
L4G_TIMING_N
LAB4_CH6
SHEET-27
L4G_SCL
L4G_SDA
L4G_VBIAS2
L4G_ISEL
L4G_SBBIAS
L4G_CMPBIAS
L4G_VBS
L4G_TIMING_THR
L4G_VDLYP
L4G_VDLYN
L4G_ROVDD
L4G_VPED_BUFF
L4G_VBIAS
DACS_CH6
SHEET-28
L4G_RF
L4G_RF_SYNC
L4G_RFIN
RF_CH6
SHEET-29
J7-1
J7-2
J7-3
J7-4
J7-5
1
2
R15G
2k
1
2
R16G
2k
1
2
R17G
1k
1
2
X1G
SM
_LED
L4G_RX_P
L4G_RX_N
L4G_TX_P
L4G_TX_N
L4G_CLK_P
L4G_CLK_N
L4G_SST_P
L4G_SST_N
L4G_WR_EN
L4G_WCLK_P
L4G_WCLK_N
L4G_SRCLK_P
L4G_SRCLK_N
L4G_TIMING_P
L4G_TIMING_N
L4G_SCL
L4G_SDA
L4G_RF
L4G_RF_SYNC
L4G_SPI_MOSI
L4G_SPI_NCS
L4G_SPI_SCK
L4G_SPI_MISO
2.5V
2.5V
2.5V
L4G_MON0
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
27
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4G
LAB4B
C2G
100 p
F
C30G
100 uF
RAMPG
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2G
MIC5323-6P
C6G
4.7 uF
C1G
0.1 uF
1
2
R13G
10k
1
2
R14G
10k
C9G
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1G-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1G-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1G-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1G-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1G-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1G-F
1
2
R1G
100
1
2
R2G
150
1
2
R4G
150
1
2
R3G
140
1
2
R5G
100
1
2
R6G
150
1
2
R7G
150
1
2
R8G
140
1
2
R9G
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3G
25LD040
C18G
0.1 uF
C19G
0.1 uF
C20G
0.1 uF
C24G
0.1 uF
C25G
0.1 uF
C26G
0.1 uF
C27G
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2G
LMH7220
C23G
0.1 uF
1
2
R21G
100
1
2
R22G
100
1
2
R23G
100
1
2
R12G
50
PWR
GND
2
3
1
V3G
1.2V
C8G
1 uF
C7G
1 uF
C10G
0.1 uF
C11G
0.1 uF
C12G
0.1 uF
C13G
0.1 uF
C14G
0.1 uF
C15G
0.1 uF
C16G
4.7 uF
C17G
0.1 uF
L4G_2.5V
L4G_RFIN
L4G_WR[0:4]
L4G_WR0
L4G_WR1
L4G_WR2
L4G_WR3
L4G_WR4
L4G_WR_EN
L4G_WCLK_P
L4G_WCLK_N
L4G_2.5V
3.3V_FILT_GHI
L4G_2.5V
L4G_SST_P
L4G_SST_N
L4G_VBS
L4G_VBIAS
L4G_VBIAS2
L4G_ISEL
L4G_SBBIAS
L4G_CMPBIAS
L4G_VPED_BUFF
L4G_VDLYP
L4G_VDLYN
L4G_ROVDD
L4G_CLK_P
L4G_CLK_N
L4G_TX_N
L4G_TX_P
2.5V
L4G_RX_P
L4G_RX_N
L4G_RD[0:4]
L4G_RD0
L4G_RD1
L4G_RD2
L4G_RD3
L4G_RD4
L4G_ICE_SRCLK_P
L4G_ICE_SRCLK_N
L4G_TX_N
L4G_TX_P
2.5V
L4G_1.2V
2.5V
2.5V
2.5V
2.5V
L4G_RD0
L4G_RD2
L4G_RD4
L4G_RD3
L4G_RD1
L4G_SCLK
L4G_SIN
L4G_UPDATE
L4G_PT
L4G_PCLK
L4G_RD_EN
L4G_SEL_ANY
L4G_RAMP
L4G_REGCLR
L4G_DOE_P
L4G_DOE_N
L4G_SS_INCR
L4G_CLR
L4G_SHOUT
L4G_1.2V
L4G_SPI_NCS
L4G_SPI_MISO
L4G_SPI_MOSI
L4G_SPI_SCK
L4G_CDONE
ICE40_RESET
L4G_MON0
L4G_CLK_N
L4G_CLK_N
L4G_SRCLK_P
L4G_SRCLK_N
L4G_SR_SEL
3.3V_FILT_GHI
L4G_TIMING_P
L4G_TIMING_N
L4G_TIMING_THR
L4G_MONTIMING_TO_COMP
L4G_SST_P
L4G_WCLK_P
L4G_SRCLK_P
L4G_SST_N
L4G_WCLK_N
L4G_SRCLK_N
3.3V_FILT_GHI
L4G_1.2V
L4G_2.5V
L4G_2.5V
L4G_RD_EN
L4G_RAMP
L4G_CLR
L4G_PT
L4G_SHOUT
L4G_PCLK
L4G_SCLK
L4G_SIN
L4G_UPDATE
L4G_REGCLR
L4G_SS_INCR
L4G_SEL_ANY
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
28
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4G
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5G
LTC2635_EP
+
-
2
1
3
U6G
LT6003
1
2
R19G
16k
1
2
R20G
16k
C3G
0.1
uF
C4G
0.1 uF
C5G
0.1 uF
C22G
0.1 uF
C21G
0.1 uF
VPEDG
C28G
0.1 uF
3.3V_FILT_GHI
L4G_VBIAS2
L4G_ISEL
L4G_SBBIAS
L4G_CMPBIAS
L4G_VBS
L4G_TIMING_THR
L4G_SCL
L4G_SDA
L4G_SCL
L4G_SDA
L4G_VDLYP
L4G_VDLYN
L4G_ROVDD
L4G_VPED_BUFF
L4G_VPED
L4G_VBIAS
3.3V_FILT_GHI
3.3V_FILT_GHI
L4G_2.5V
3.3V_FILT_GHI
A
B
D
C
A
B
C
D
6
5
4
3
2
1
DATE:
LTR
ECO NO:
APPROVED:
REVISION RECORD
SCALE:
SHEET: OF
DRAWING NO:
TITLE:
COMPANY:
RELEASED:
DATED:
DATED:
QUALITY CONTROL:
CHECKED:
DATED:
DATED:
DRAWN:
CODE:
SIZE:
REV:
58
29
<Scale>
<Revision>
<Drawing Number>
C
<Code>
<Title>
<Company Name>
<Release Date>
<QC Date>
<Checked Date>
<Drawn Date>
<Released By>
<QC By>
<Checked By>
<Drawn By>
Block
Pass
1
3
4
2
F2G
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Pass
Block
4
2
1
3
F1G
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7G
RF_SPLITTER
4
3
1
2
U8G
EXB24AT2
0 dB
2
1
R11G
475
C29G
0.1
uF
3
4
1
2
6
T1G
TCD-XX-4X+
1
2
R10G
50
C31G
470 pF
L4G_RFIN
L4G_RF
L4G_RF_SYNC
L4G_RFP_IN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
30
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4H_RFIN
L4H_WR_EN
L4H_WCLK_P
L4H_WCLK_N
L4H_SST_P
L4H_SST_N
L4H_VBS
L4H_VBIAS
L4H_VBIAS2
L4H_ISEL
L4H_SBBIAS
L4H_CMPBIAS
L4H_VPED_BUFF
L4H_VDLYP
L4H_VDLYN
L4H_ROVDD
L4H_CLK_P
L4H_CLK_N
L4H_TX_N
L4H_TX_P
L4H_SPI_NCS
L4H_SPI_MISO
L4H_SPI_MOSI
L4H_SPI_SCK
L4H_CDONE
L4H_CRESET
L4H_TIMING_THR
L4H_SRCLK_P
L4H_SRCLK_N
L4H_RX_P
L4H_RX_N
L4H_MON0
L4H_TIMING_P
L4H_TIMING_N
LAB4_CH7
SHEET-31
L4H_SCL
L4H_SDA
L4H_VBIAS2
L4H_ISEL
L4H_SBBIAS
L4H_CMPBIAS
L4H_VBS
L4H_TIMING_THR
L4H_VDLYP
L4H_VDLYN
L4H_ROVDD
L4H_VPED_BUFF
L4H_VBIAS
DACS_CH7
SHEET-32
L4H_RF
L4H_RF_SYNC
L4H_RFIN
RF_CH7
SHEET-33
J8-1
J8-2
J8-3
J8-4
J8-5
1
2
R15H
2k
1
2
R16H
2k
1
2
R17H
1k
1
2
X1H
SM
_LED
L4H_RX_P
L4H_RX_N
L4H_TX_P
L4H_TX_N
L4H_CLK_P
L4H_CLK_N
L4H_SST_P
L4H_SST_N
L4H_WR_EN
L4H_WCLK_P
L4H_WCLK_N
L4H_SRCLK_P
L4H_SRCLK_N
L4H_TIMING_P
L4H_TIMING_N
L4H_SCL
L4H_SDA
L4H_RF
L4H_RF_SYNC
L4H_SPI_MOSI
L4H_SPI_NCS
L4H_SPI_SCK
L4H_SPI_MISO
2.5V
2.5V
2.5V
L4H_MON0
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
31
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4H
LAB4B
C2H
100 p
F
C30H
100 uF
RAMPH
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2H
MIC5323-6P
C6H
4.7 uF
C1H
0.1 uF
1
2
R13H
10k
1
2
R14H
10k
C9H
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1H-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1H-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1H-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1H-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1H-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1H-F
1
2
R1H
100
1
2
R2H
150
1
2
R4H
150
1
2
R3H
140
1
2
R5H
100
1
2
R6H
150
1
2
R7H
150
1
2
R8H
140
1
2
R9H
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3H
25LD040
C18H
0.1 uF
C19H
0.1 uF
C20H
0.1 uF
C24H
0.1 uF
C25H
0.1 uF
C26H
0.1 uF
C27H
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2H
LMH7220
C23H
0.1 uF
1
2
R21H
100
1
2
R22H
100
1
2
R23H
100
1
2
R12H
50
GND
PWR
2
3
1
V3H
1.2V
C8H
1 uF
C7H
1 uF
C10H
0.1 uF
C11H
0.1 uF
C12H
0.1 uF
C13H
0.1 uF
C14H
0.1 uF
C15H
0.1 uF
C16H
4.7 uF
C17H
0.1 uF
L4H_2.5V
L4H_RFIN
L4H_WR[0:4]
L4H_WR0
L4H_WR1
L4H_WR2
L4H_WR3
L4H_WR4
L4H_WR_EN
L4H_WCLK_P
L4H_WCLK_N
L4H_2.5V
3.3V_FILT_GHI
L4H_2.5V
L4H_SST_P
L4H_SST_N
L4H_VBS
L4H_VBIAS
L4H_VBIAS2
L4H_ISEL
L4H_SBBIAS
L4H_CMPBIAS
L4H_VPED_BUFF
L4H_VDLYP
L4H_VDLYN
L4H_ROVDD
L4H_CLK_P
L4H_CLK_N
L4H_TX_N
L4H_TX_P
2.5V
L4H_RX_P
L4H_RX_N
L4H_RD[0:4]
L4H_RD0
L4H_RD1
L4H_RD2
L4H_RD3
L4H_RD4
L4H_ICE_SRCLK_P
L4H_ICE_SRCLK_N
L4H_TX_N
L4H_TX_P
2.5V
L4H_1.2V
2.5V
2.5V
2.5V
2.5V
L4H_RD0
L4H_RD2
L4H_RD4
L4H_RD3
L4H_RD1
L4H_SCLK
L4H_SIN
L4H_UPDATE
L4H_PT
L4H_PCLK
L4H_RD_EN
L4H_SEL_ANY
L4H_RAMP
L4H_REGCLR
L4H_DOE_P
L4H_DOE_N
L4H_SS_INCR
L4H_CLR
L4H_SHOUT
L4H_1.2V
L4H_SPI_NCS
L4H_SPI_MISO
L4H_SPI_MOSI
L4H_SPI_SCK
L4H_CDONE
ICE40_RESET
L4H_MON0
L4H_CLK_N
L4H_CLK_N
L4H_SRCLK_P
L4H_SRCLK_N
L4H_SR_SEL
3.3V_FILT_GHI
L4H_TIMING_P
L4H_TIMING_N
L4H_TIMING_THR
L4H_MONTIMING_TO_COMP
L4H_SST_P
L4H_WCLK_P
L4H_SRCLK_P
L4H_SST_N
L4H_WCLK_N
L4H_SRCLK_N
3.3V_FILT_GHI
L4H_1.2V_GHI
L4H_2.5V
L4H_2.5V
L4H_DOE_P
L4H_DOE_N
L4H_SHOUT
L4H_RD_EN
L4H_RAMP
L4H_CLR
L4H_PT
L4H_PCLK
L4H_SCLK
L4H_SIN
L4H_UPDATE
L4H_REGCLR
L4H_SR_SEL
L4H_CDONE
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
32
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4H
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5H
LTC2635_EP
-
+
2
1
3
U6H
LT6003
1
2
R19H
16k
1
2
R20H
16k
C3H
0.1
uF
C4H
0.1 uF
C5H
0.1 uF
C22H
0.1 uF
C21H
0.1 uF
VPEDH
C28H
0.1 uF
3.3V_FILT_GHI
L4H_VBIAS2
L4H_ISEL
L4H_SBBIAS
L4H_CMPBIAS
L4H_VBS
L4H_TIMING_THR
L4H_SCL
L4H_SDA
L4H_SCL
L4H_SDA
L4H_VDLYP
L4H_VDLYN
L4H_ROVDD
L4H_VPED_BUFF
L4H_VPED
L4H_VBIAS
3.3V_FILT_GHI
3.3V_FILT_GHI
L4H_2.5V
3.3V_FILT_GHI
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
33
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Pass
Block
1
3
4
2
F2H
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Block
Pass
4
2
1
3
F1H
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7H
RF_SPLITTER
4
3
1
2
U8H
EXB24AT2
0 dB
2
1
R11H
475
C29H
0.1
uF
3
4
1
2
6
T1H
TCD-XX-4X+
1
2
R10H
50
C31H
470 pF
L4H_RFIN
L4H_RF
L4H_RF_SYNC
L4H_RFP_IN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
34
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4I_RFIN
L4I_WR_EN
L4I_WCLK_P
L4I_WCLK_N
L4I_SST_P
L4I_SST_N
L4I_VBS
L4I_VBIAS
L4I_VBIAS2
L4I_ISEL
L4I_SBBIAS
L4I_CMPBIAS
L4I_VPED_BUFF
L4I_VDLYP
L4I_VDLYN
L4I_ROVDD
L4I_CLK_P
L4I_CLK_N
L4I_TX_N
L4I_TX_P
L4I_SPI_NCS
L4I_SPI_MISO
L4I_SPI_MOSI
L4I_SPI_SCK
L4I_CDONE
L4A_CRESET
L4I_TIMING_THR
L4I_SRCLK_P
L4I_SRCLK_N
L4I_RX_P
L4I_RX_N
L4I_MON0
L4I_TIMING_P
L4I_TIMING_N
LAB4_CH8
SHEET-35
L4I_SCL
L4I_SDA
L4I_VBIAS2
L4I_ISEL
L4I_SBBIAS
L4I_CMPBIAS
L4I_VBS
L4I_TIMING_THR
L4I_VDLYP
L4I_VDLYN
L4I_ROVDD
L4I_VPED_BUFF
L4I_VBIAS
DACS_CH8
SHEET-36
L4I_RF
L4I_RF_SYNC
L4I_RFIN
RF_CH8
SHEET-37
J9-1
J9-2
J9-3
J9-4
J9-5
1
2
R15I
2k
1
2
R16I
2k
1
2
R17I
1k
1
2
X1I
SM
_LED
L4I_RX_P
L4I_RX_N
L4I_TX_P
L4I_TX_N
L4I_CLK_P
L4I_CLK_N
L4I_SST_P
L4I_SST_N
L4I_WR_EN
L4I_WCLK_P
L4I_WCLK_N
L4I_SRCLK_P
L4I_SRCLK_N
L4I_TIMING_P
L4I_TIMING_N
L4I_SCL
L4I_SDA
L4I_RF
L4I_RF_SYNC
L4I_SPI_MOSI
L4I_SPI_NCS
L4I_SPI_SCK
L4I_SPI_MISO
2.5V
2.5V
2.5V
L4I_MON0
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
35
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4I
LAB4B
C2I
100 p
F
C30I
100 uF
RAMPI
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2I
MIC5323-6P
C6I
4.7 uF
C1I
0.1 uF
1
2
R13I
10k
1
2
R14I
10k
C9I
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1I-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1I-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1I-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1I-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1I-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1I-F
1
2
R1I
100
1
2
R2I
150
1
2
R4I
150
1
2
R3I
140
1
2
R5I
100
1
2
R6I
150
1
2
R7I
150
1
2
R8I
140
1
2
R9I
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3I
25LD040
C18I
0.1 uF
C19I
0.1 uF
C20I
0.1 uF
C24I
0.1 uF
C25I
0.1 uF
C26I
0.1 uF
C27I
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2I
LMH7220
C23I
0.1 uF
1
2
R21I
100
1
2
R22I
100
1
2
R23I
100
1
2
R12I
50
GND
PWR
2
3
1
V3I
1.2V
C8I
1 uF
C7I
1 uF
C10I
0.1 uF
C11I
0.1 uF
C12I
0.1 uF
C13I
0.1 uF
C14I
0.1 uF
C15I
0.1 uF
C16I
4.7 uF
C17I
0.1 uF
L4I_2.5V
L4I_RFIN
L4I_WR[0:4]
L4I_WR0
L4I_WR1
L4I_WR2
L4I_WR3
L4I_WR4
L4I_WR_EN
L4I_WCLK_P
L4I_WCLK_N
L4I_2.5V
3.3V_FILT_GHI
L4I_2.5V
L4I_SST_P
L4I_SST_N
L4I_VBS
L4I_VBIAS
L4I_VBIAS2
L4I_ISEL
L4I_SBBIAS
L4I_CMPBIAS
L4I_VPED_BUFF
L4I_VDLYP
L4I_VDLYN
L4I_ROVDD
L4I_CLK_P
L4I_CLK_N
L4I_TX_N
L4I_TX_P
2.5V
L4I_RX_P
L4I_RX_N
L4I_RD[0:4]
L4I_RD0
L4I_RD1
L4I_RD2
L4I_RD3
L4I_RD4
L4I_ICE_SRCLK_P
L4I_ICE_SRCLK_N
L4I_TX_N
L4I_TX_P
2.5V
L4I_1.2V
2.5V
2.5V
2.5V
2.5V
L4I_RD0
L4I_RD2
L4I_RD4
L4I_RD3
L4I_RD1
L4I_SCLK
L4I_SIN
L4I_UPDATE
L4I_PT
L4I_PCLK
L4I_RD_EN
L4I_SEL_ANY
L4I_RAMP
L4I_REGCLR
L4I_DOE_P
L4I_DOE_N
L4I_SS_INCR
L4I_CLR
L4I_SHOUT
L4I_1.2V
L4I_SPI_NCS
L4I_SPI_MISO
L4I_SPI_MOSI
L4I_SPI_SCK
L4I_CDONE
ICE40_RESET
L4I_MON0
L4I_CLK_N
L4I_CLK_N
L4I_SRCLK_P
L4I_SRCLK_N
L4I_SR_SEL
3.3V_FILT_GHI
L4I_TIMING_P
L4I_TIMING_N
L4I_TIMING_THR
L4I_MONTIMING_TO_COMP
L4I_SST_P
L4I_WCLK_P
L4I_SRCLK_P
L4I_SST_N
L4I_WCLK_N
L4I_SRCLK_N
3.3V_FILT_GHI
L4I_1.2V
L4I_2.5V
L4I_2.5V
L4I_RD_EN
L4I_RAMP
L4I_CLR
L4I_PT
L4I_SHOUT
L4I_PCLK
L4I_SCLK
L4I_SIN
L4I_UPDATE
L4I_REGCLR
L4I_SS_INCR
L4I_SEL_ANY
L4I_CDONE
L4I_SR_SEL
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
36
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4I
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5I
LTC2635_EP
-
+
2
1
3
U6I
LT6003
1
2
R19I
16k
1
2
R20I
16k
C3I
0.1
uF
C4I
0.1 uF
C5I
0.1 uF
C22I
0.1 uF
C21I
0.1 uF
VPEDI
C28I
0.1 uF
3.3V_FILT_GHI
L4I_VBIAS2
L4I_ISEL
L4I_SBBIAS
L4I_CMPBIAS
L4I_VBS
L4I_TIMING_THR
L4I_SCL
L4I_SDA
L4I_SCL
L4I_SDA
L4I_VDLYP
L4I_VDLYN
L4I_ROVDD
L4I_VPED_BUFF
L4I_VPED
L4I_VBIAS
3.3V_FILT_GHI
3.3V_FILT_GHI
L4I_2.5V
3.3V_FILT_GHI
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
37
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Pass
Block
1
3
4
2
F2I
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Block
Pass
4
2
1
3
F1I
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7I
RF_SPLITTER
4
3
1
2
U8I
EXB24AT2
0 dB
2
1
R11I
475
C29I
0.1
uF
3
4
1
2
6
T1I
TCD-XX-4X+
1
2
R10I
50
C31I
470 pF
L4I_RFIN
L4I_RF
L4I_RF_SYNC
L4I_RFP_IN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
38
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4J_RFIN
L4J_WR_EN
L4J_WCLK_P
L4J_WCLK_N
L4J_SST_P
L4J_SST_N
L4J_VBS
L4A_VBIAS
L4J_VBIAS2
L4J_ISEL
L4J_SBBIAS
L4J_CMPBIAS
L4J_VPED_BUFF
L4J_VDLYP
L4J_VDLYN
L4J_ROVDD
L4J_CLK_P
L4J_CLK_N
L4J_TX_N
L4J_TX_P
L4J_SPI_NCS
L4J_SPI_MISO
L4J_SPI_MOSI
L4J_SPI_SCK
L4J_CDONE
L4J_CRESET
L4J_TIMING_THR
L4J_SRCLK_P
L4J_SRCLK_N
L4J_RX_P
L4J_RX_N
L4J_MON0
L4J_TIMING_P
L4J_TIMING_N
LAB4_CH9
SHEET-39
L4J_SCL
L4J_SDA
L4J_VBIAS2
L4J_ISEL
L4J_SBBIAS
L4J_CMPBIAS
L4J_VBS
L4J_TIMING_THR
L4J_VDLYP
L4J_VDLYN
L4J_ROVDD
L4J_VPED_BUFF
L4A_VBIAS
DACS_CH9
SHEET-40
L4J_RF
L4J_RF_SYNC
L4J_RFIN
RF_CH9
SHEET-41
J10-1
J10-2
J10-3
J10-4
J10-5
1
2
R15J
2k
1
2
R16J
2k
1
2
R17J
1k
1
2
X1J
SM
_LED
L4J_RX_P
L4J_RX_N
L4J_TX_P
L4J_TX_N
L4J_CLK_P
L4J_CLK_N
L4J_SST_P
L4J_SST_N
L4J_WR_EN
L4J_WCLK_P
L4J_WCLK_N
L4J_SRCLK_P
L4J_SRCLK_N
L4J_TIMING_P
L4J_TIMING_N
L4J_SCL
L4J_SDA
L4J_RF
L4J_RF_SYNC
L4J_SPI_MOSI
L4J_SPI_NCS
L4J_SPI_SCK
L4J_SPI_MISO
2.5V
2.5V
2.5V
L4J_MON0
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
39
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4J
LAB4B
C2J
100 p
F
C30J
100 uF
RAMPJ
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2J
MIC5323-6P
C6J
4.7 uF
C1J
0.1 uF
1
2
R13J
10k
1
2
R14J
10k
C9J
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1J-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1J-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1J-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1J-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1J-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1J-F
1
2
R1J
100
1
2
R2J
150
1
2
R4J
150
1
2
R3J
140
1
2
R5J
100
1
2
R6J
150
1
2
R7J
150
1
2
R8J
140
1
2
R9J
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3J
25LD040
C18J
0.1 uF
C19J
0.1 uF
C20J
0.1 uF
C24J
0.1 uF
C25J
0.1 uF
C26J
0.1 uF
C27J
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2J
LMH7220
C23J
0.1 uF
1
2
R21J
100
1
2
R22J
100
1
2
R23J
100
1
2
R12J
50
GND
PWR
2
3
1
V3J
1.2V
C8J
1 uF
C7J
1 uF
C10J
0.1 uF
C11J
0.1 uF
C12J
0.1 uF
C13J
0.1 uF
C14J
0.1 uF
C15J
0.1 uF
C16J
4.7 uF
C17J
0.1 uF
L4J_2.5V
L4J_RFIN
L4J_WR[0:4]
L4J_WR0
L4J_WR1
L4J_WR2
L4J_WR3
L4J_WR4
L4J_WR_EN
L4J_WCLK_P
L4J_WCLK_N
L4J_2.5V
3.3V_FILT_JKL
L4J_2.5V
L4J_SST_P
L4J_SST_N
L4J_VBS
L4J_VBIAS
L4J_VBIAS2
L4J_ISEL
L4J_SBBIAS
L4J_CMPBIAS
L4J_VPED_BUFF
L4J_VDLYP
L4J_VDLYN
L4J_ROVDD
L4J_CLK_P
L4J_CLK_N
L4J_TX_N
L4J_TX_P
2.5V
L4J_RX_P
L4J_RX_N
L4J_RD[0:4]
L4J_RD0
L4J_RD1
L4J_RD2
L4J_RD3
L4J_RD4
L4J_ICE_SRCLK_P
L4J_ICE_SRCLK_N
L4J_TX_N
L4J_TX_P
2.5V
L4J_1.2V
2.5V
2.5V
2.5V
2.5V
L4J_RD0
L4J_RD2
L4J_RD4
L4J_RD3
L4J_RD1
L4J_SCLK
L4J_SIN
L4J_UPDATE
L4J_PT
L4J_PCLK
L4J_RD_EN
L4J_SEL_ANY
L4J_RAMP
L4J_REGCLR
L4J_DOE_P
L4J_DOE_N
L4J_SS_INCR
L4J_CLR
L4J_SHOUT
L4J_1.2V
L4J_SPI_NCS
L4J_SPI_MISO
L4J_SPI_MOSI
L4J_SPI_SCK
L4J_CDONE
ICE40_RESET
L4J_MON0
L4J_CLK_N
L4J_CLK_N
L4J_SRCLK_P
L4J_SRCLK_N
L4J_SR_SEL
3.3V_FILT_JKL
L4J_TIMING_P
L4J_TIMING_N
L4J_TIMING_THR
L4J_MONTIMING_TO_COMP
L4J_SST_P
L4J_WCLK_P
L4J_SRCLK_P
L4J_SST_N
L4J_WCLK_N
L4J_SRCLK_N
3.3V_FILT_JKL
L4J_1.2V
L4J_2.5V
L4J_2.5V
L4J_RD_EN
L4J_CLR
L4J_RAMP
L4J_PT
L4J_PCLK
L4J_SCLK
L4J_SIN
L4J_UPDATE
L4J_REGCLR
L4J_SS_INCR
L4J_SEL_ANY
L4J_SHOUT
L4J_DOE_N
L4J_DOE_P
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
40
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4J
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5J
LTC2635_EP
-
+
2
1
3
U6J
LT6003
1
2
R19J
16k
1
2
R20J
16k
C3J
0.1
uF
C4J
0.1 uF
C5J
0.1 uF
C22J
0.1 uF
C21J
0.1 uF
VPEDJ
C28J
0.1 uF
3.3V_FILT_JKL
L4J_VBIAS2
L4J_ISEL
L4J_SBBIAS
L4J_CMPBIAS
L4J_VBS
L4J_TIMING_THR
L4J_SCL
L4J_SDA
L4J_SCL
L4J_SDA
L4J_VDLYP
L4J_VDLYN
L4J_ROVDD
L4J_VPED_BUFF
L4J_VPED
L4J_VBIAS
3.3V_FILT_JKL
3.3V_FILT_JKL
L4J_2.5V
3.3V_FILT_JKL
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
41
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Pass
Block
1
3
4
2
F2J
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Block
Pass
4
2
1
3
F1J
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7J
RF_SPLITTER
4
3
1
2
U8J
EXB24AT2
0 dB
2
1
R11J
475
C29J
0.1
uF
3
4
1
2
6
T1J
TCD-XX-4X+
1
2
R10A9
50
C31J
470 pF
L4J_RFIN
L4J_RF
L4J_RF_SYNC
L4J_RFP_IN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
42
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4K_RFIN
L4K_WR_EN
L4K_WCLK_P
L4K_WCLK_N
L4K_SST_P
L4K_SST_N
L4K_VBS
L4K_VBIAS
L4K_VBIAS2
L4K_ISEL
L4K_SBBIAS
L4K_CMPBIAS
L4K_VPED_BUFF
L4K_VDLYP
L4K_VDLYN
L4K_ROVDD
L4K_CLK_P
L4K_CLK_N
L4K_TX_N
L4K_TX_P
L4K_SPI_NCS
L4K_SPI_MISO
L4K_SPI_MOSI
L4K_SPI_SCK
L4K_CDONE
L4K_CRESET
L4K_TIMING_THR
L4K_SRCLK_P
L4K_SRCLK_N
L4K_RX_P
L4K_RX_N
L4K_MON0
L4K_TIMING_P
L4K_TIMING_N
LAB4_C10
SHEET-43
L4K_SCL
L4K_SDA
L4K_VBIAS2
L4K_ISEL
L4K_SBBIAS
L4K_CMPBIAS
L4K_VBS
L4K_TIMING_THR
L4K_VDLYP
L4K_VDLYN
L4K_ROVDD
L4K_VPED_BUFF
L4K_VBIAS
DACS_C10
SHEET-44
L4K_RF
L4K_RF_SYNC
L4K_RFIN
RF_C10
SHEET-45
J27-1
J27-2
J27-3
J27-4
J27-5
1
2
R15K
2k
1
2
R16K
2k
1
2
R17K
1k
1
2
X1K
SM
_LED
L4K_RX_P
L4K_RX_N
L4K_TX_P
L4K_TX_N
L4K_CLK_P
L4K_CLK_N
L4K_SST_P
L4K_SST_N
L4K_WR_EN
L4K_WCLK_P
L4K_WCLK_N
L4K_SRCLK_P
L4K_SRCLK_N
L4K_TIMING_P
L4K_TIMING_N
L4K_SCL
L4K_SDA
L4K_RF
L4K_RF_SYNC
L4K_SPI_MOSI
L4K_SPI_NCS
L4K_SPI_SCK
L4K_SPI_MISO
2.5V
2.5V
2.5V
L4K_MON0
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
43
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4A9
LAB4B
C2K
100 p
F
C30K
100 uF
RAMPK
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2K
MIC5323-6P
C6K
4.7 uF
C1K
0.1 uF
1
2
R13K
10k
1
2
R14K
10k
C9K
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1A9-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1A9-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1A9-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1A9-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1A9-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1A9-F
1
2
R1K
100
1
2
R2K
150
1
2
R4K
150
1
2
R3K
140
1
2
R5K
100
1
2
R6K
150
1
2
R7K
150
1
2
R8K
140
1
2
R9K
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3K
25LD040
C18K
0.1 uF
C19K
0.1 uF
C20K
0.1 uF
C24K
0.1 uF
C25K
0.1 uF
C26K
0.1 uF
C27K
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2K
LMH7220
C23K
0.1 uF
1
2
R21K
100
1
2
R22K
100
1
2
R23K
100
1
2
R12K
50
GND
PWR
2
3
1
V3K
1.2V
C8K
1 uF
C7K
1 uF
C10K
0.1 uF
C11K
0.1 uF
C12K
0.1 uF
C13K
0.1 uF
C14K
0.1 uF
C15K
0.1 uF
C16K
4.7 uF
C17K
0.1 uF
L4K_2.5V
L4K_RFIN
L4K_WR[0:4]
L4K_WR0
L4K_WR1
L4K_WR2
L4K_WR3
L4K_WR4
L4K_WR_EN
L4K_WCLK_P
L4K_WCLK_N
L4K_2.5V
3.3V_FILT_JKL
L4K_2.5V
L4K_SST_P
L4K_SST_N
L4K_VBS
L4K_VBIAS
L4K_VBIAS2
L4K_ISEL
L4K_SBBIAS
L4K_CMPBIAS
L4K_VPED_BUFF
L4K_VDLYP
L4K_VDLYN
L4K_ROVDD
L4K_CLK_P
L4K_CLK_N
L4K_TX_N
L4K_TX_P
2.5V
L4K_RX_P
L4K_RX_N
L4K_RD[0:4]
L4K_RD0
L4K_RD1
L4K_RD2
L4K_RD3
L4K_RD4
L4K_ICE_SRCLK_P
L4K_ICE_SRCLK_N
L4K_TX_N
L4K_TX_P
2.5V
L4K_1.2V
2.5V
2.5V
2.5V
2.5V
L4K_RD0
L4K_RD2
L4K_RD4
L4K_RD3
L4K_RD1
L4K_SCLK
L4K_SIN
L4K_UPDATE
L4K_PT
L4K_PCLK
L4K_RD_EN
L4K_SEL_ANY
L4K_RAMP
L4K_REGCLR
L4K_DOE_P
L4K_DOE_N
L4K_SS_INCR
L4K_CLR
L4K_SHOUT
L4K_1.2V
L4K_SPI_NCS
L4K_SPI_MISO
L4K_SPI_MOSI
L4K_SPI_SCK
L4K_CDONE
ICE40_RESET
L4K_MON0
L4K_CLK_N
L4K_CLK_N
L4K_SRCLK_P
L4K_SRCLK_N
L4K_SR_SEL
3.3V_FILT_JKL
L4K_TIMING_P
L4K_TIMING_N
L4K_TIMING_THR
L4K_MONTIMING_TO_COMP
L4K_SST_P
L4K_WCLK_P
L4K_SRCLK_P
L4K_SST_N
L4K_WCLK_N
L4K_SRCLK_N
3.3V_FILT_JKL
L4K_1.2V
L4K_2.5V
L4K_2.5V
L4K_DOE_N
L4K_DOE_P
L4K_SHOUT
L4K_RAMP
L4K_CLR
L4K_PT
L4K_PCLK
L4K_SCLK
L4K_SIN
L4K_UPDATE
L4K_REGCLR
L4K_SS_INCR
L4K_SEL_ANY
L4K_DOE_N
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
44
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4K
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5K
LTC2635_EP
-
+
2
1
3
U6K
LT6003
1
2
R19K
16k
1
2
R20K
16k
C3K
0.1
uF
C4K
0.1 uF
C5K
0.1 uF
C22K
0.1 uF
C21K
0.1 uF
VPEDK
C28K
0.1 uF
3.3V_FILT_JKL
L4K_VBIAS2
L4K_ISEL
L4K_SBBIAS
L4K_CMPBIAS
L4K_VBS
L4K_TIMING_THR
L4K_SCL
L4K_SDA
L4K_SCL
L4K_SDA
L4K_VDLYP
L4K_VDLYN
L4K_ROVDD
L4K_VPED_BUFF
L4K_VPED
L4K_VBIAS
3.3V_FILT_JKL
3.3V_FILT_JKL
L4K_2.5V
3.3V_FILT_JKL
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
45
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Pass
Block
1
3
4
2
F2K
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Block
Pass
4
2
1
3
F1K
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7K
RF_SPLITTER
4
3
1
2
U8K
EXB24AT2
0 dB
2
1
R11K
475
C29K
0.1
uF
3
4
1
2
6
T1K
TCD-XX-4X+
1
2
R10K
50
C31K
470 pF
L4K_RFIN
L4K_RF
L4K_RF_SYNC
L4K_RFP_IN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
46
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
L4L_RFIN
L4L_WR_EN
L4L_WCLK_P
L4L_WCLK_N
L4L_SST_P
L4L_SST_N
L4L_VBS
L4L_VBIAS
L4L_VBIAS2
L4L_ISEL
L4L_SBBIAS
L4L_CMPBIAS
L4L_VPED_BUFF
L4L_VDLYP
L4L_VDLYN
L4L_ROVDD
L4L_CLK_P
L4L_CLK_N
L4L_TX_N
L4L_TX_P
L4L_SPI_NCS
L4L_SPI_MISO
L4L_SPI_MOSI
L4L_SPI_SCK
L4L_CDONE
L4L_CRESET
L4L_TIMING_THR
L4L_SRCLK_P
L4L_SRCLK_N
L4L_RX_P
L4L_RX_N
L4L_MON0
L4L_TIMING_P
L4L_TIMING_N
LAB4_C11
SHEET-47
L4L_SCL
L4L_SDA
L4L_VBIAS2
L4L_ISEL
L4L_SBBIAS
L4L_CMPBIAS
L4L_VBS
L4L_TIMING_THR
L4L_VDLYP
L4L_VDLYN
L4L_ROVDD
L4L_VPED_BUFF
L4L_VBIAS
DACS_C11
SHEET-48
L4L_RF
L4L_RF_SYNC
L4L_RFIN
RF_C11
SHEET-49
J28-1
J28-2
J28-3
J28-4
J28-5
1
2
R15L
2k
1
2
R16L
2k
1
2
R17L
1k
1
2
X1L
SM
_LED
L4L_RX_P
L4L_RX_N
L4L_TX_P
L4L_TX_N
L4L_CLK_P
L4L_CLK_N
L4L_SST_P
L4L_SST_N
L4L_WR_EN
L4L_WCLK_P
L4L_WCLK_N
L4L_SRCLK_P
L4L_SRCLK_N
L4L_TIMING_P
L4L_TIMING_N
L4L_SCL
L4L_SDA
L4L_RF
L4L_RF_SYNC
L4L_SPI_MOSI
L4L_SPI_NCS
L4L_SPI_SCK
L4L_SPI_MISO
2.5V
2.5V
2.5V
L4L_MON0
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
47
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Stage 2 power filtering: decouple 3.3V devices from LAB4s
Note: DOE is inverted!
Invert again in logic.
15
RFIN
16
RFN
11
SSTINP
12
SSTINN
50
WR_S4
51
WR_S3
52
WR_S2
53
WR_S1
54
WR_S0
2
WR_ENA
31
RD_S4
30
RD_S3
29
RD_S2
28
RD_S1
27
RD_S0
1
RD_ENA
41
WCLKP
40
WCLKN
55
RAMP
4
CLR
10
PT
5
PCLK
23
SCLK
22
SIN
24
UPDATE
64
REGCLR
46
SRCLKP
45
SRCLKN
39
SR_SEL
38
SS_INCR
3
SEL_ANY
18
VDLYP
19
VDLYN
33
ROVDD
35
MONTIMING
36
SSTDLY
48
DOE_LVDSP
47
DOE_LVDSN
43
DOE
57
RAMPMON
25
SHOUT
62
CM
PBIA
S
61
SBBIA
S
58
ISEL
7
VBIA
S2
20
VBIA
S
8
VBS
6
VD
D
14
VD
D
21
VD
D
32
VD
D
37
VD
D
42
VD
D
49
VD
D
60
VD
D
9
GN
D
13
GN
D
17
GN
D
26
GN
D
34
GN
D
44
GN
D
56
GN
D
63
GN
D
59
VRAM
PREF
LAB4L
LAB4B
C2L
100 p
F
C30L
100 uF
RAMPL
3
VIN
1
EN
4
VOUT
5
ADJ/NC
6
BYP
2
GN
D
V2L
MIC5323-6P
C6L
4.7 uF
C1L
0.1 uF
1
2
R13L
10k
1
2
R14L
10k
C9L
4.7 uF
BANK0
A42
VCCIO0
B32
GBIN0/PIO0_00
A43
GBIN1/PIO0_01
A38
PIO0_02
A39
PIO0_03
A40
PIO0_04
A41
PIO0_05
A44
PIO0_06
A45
PIO0_07
A46
PIO0_08
A47
PIO0_09
A48
PIO0_10
B29
PIO0_11
B30
PIO0_12
B31
PIO0_13
B34
PIO0_14
B35
PIO0_15
B36
PIO0_16
U1L-A
BANK1
B22
GBIN2/PIO1_00
A29
GBIN3/PIO1_01
B25
VCCIO1
A25
PIO1_02
A26
PIO1_03
A27
PIO1_04
A31
PIO1_05
A32
PIO1_06
A33
PIO1_07
A34
PIO1_08
A35
PIO1_09
B19
PIO1_10
B20
PIO1_11
B21
PIO1_12
B23
PIO1_13
B24
PIO1_14
B26
PIO1_15
B27
PIO1_16
U1L-B
BANK2
B16
CDONE
A21
CRESET_B
A14
GBIN4/PIO2_00
A16
GBIN5/PIO2_01
B15
PIO2_09/CBSEL0
A20
PIO2_10/CBSEL1
A17
VCCIO2
A13
PIO2_02
B12
PIO2_03
A19
PIO2_04
B10
PIO2_05
B11
PIO2_06
B13
PIO2_07
B14
PIO2_08
U1L-C
BANK3
A9
GBIN6/PIO3_00
A8
GBIN7/PIO3_01
B6
VCCIO3
A1
PIO3_02
A2
PIO3_03
A3
PIO3_04
A4
PIO3_05
A5
PIO3_06
A10
PIO3_07
A11
PIO3_08
A12
PIO3_09
B1
PIO3_10
B2
PIO3_11
B3
PIO3_12
B4
PIO3_13
B5
PIO3_14
B7
PIO3_15
B8
PIO3_16
B9
PIO3_17
U1L-D
SPI
A24
SPI_VCC
B17
PIOS_01/SPI_SO
A22
PIOS_02/SPI_SI
A23
PIOS_03/SPI_SCK
B18
PIOS_04/SPI_SS_B
U1L-E
POWER
A6
GND1
A18
GND2
A30
GND3
B33
GND4
A7
VCC1
A15
VCC2
A28
VCC3
B28
VCC4
A36
VPP_2V5
A37
VPP_FAST
U1L-F
1
2
R1L
100
1
2
R2L
150
1
2
R4L
150
1
2
R3L
140
1
2
R5L
100
1
2
R6L
150
1
2
R7L
150
1
2
R8L
140
1
2
R9L
100
1
CE
2
SO
3
WP
4
GND
8
VCC
7
HOLD
6
SCK
5
SIO
U3L
25LD040
C18L
0.1 uF
C19L
0.1 uF
C20L
0.1 uF
C24L
0.1 uF
C25L
0.1 uF
C26L
0.1 uF
C27L
0.1 uF
1
IN-
2
GND
3
Q
6
IN+
5
VCC
4
Q
U2L
LMH7220
C23L
0.1 uF
1
2
R21L
100
1
2
R22L
100
1
2
R23L
100
1
2
R12L
50
GND
PWR
2
3
1
V3L
1.2V
C8L
1 uF
C7L
1 uF
C10L
0.1 uF
C11L
0.1 uF
C12L
0.1 uF
C13L
0.1 uF
C14L
0.1 uF
C15L
0.1 uF
C16L
4.7 uF
C17L
0.1 uF
L4L_2.5V
L4L_RFIN
L4L_WR[0:4]
L4L_WR0
L4L_WR1
L4L_WR2
L4L_WR3
L4L_WR4
L4L_WR_EN
L4L_WCLK_P
L4L_WCLK_N
L4L_2.5V
3.3V_FILT_JKL
L4L_2.5V
L4L_SST_P
L4L_SST_N
L4L_VBS
L4L_VBIAS
L4L_VBIAS2
L4L_ISEL
L4L_SBBIAS
L4L_CMPBIAS
L4L_VPED_BUFF
L4L_VDLYP
L4L_VDLYN
L4L_ROVDD
L4L_CLK_P
L4L_CLK_N
L4L_TX_N
L4L_TX_P
2.5V
L4L_RX_P
L4L_RX_N
L4L_RD[0:4]
L4L_RD0
L4L_RD1
L4L_RD2
L4L_RD3
L4L_RD4
L4L_ICE_SRCLK_P
L4L_ICE_SRCLK_N
L4L_TX_N
L4L_TX_P
2.5V
L4L_1.2V
2.5V
2.5V
2.5V
2.5V
L4L_RD0
L4L_RD2
L4L_RD4
L4L_RD3
L4L_RD1
L4L_SCLK
L4L_SIN
L4L_UPDATE
L4L_PT
L4L_PCLK
L4L_RD_EN
L4L_SEL_ANY
L4L_RAMP
L4L_REGCLR
L4L_DOE_P
L4L_DOE_N
L4L_SS_INCR
L4L_CLR
L4L_SHOUT
L4L_1.2V
L4L_SPI_NCS
L4L_SPI_MISO
L4L_SPI_MOSI
L4L_SPI_SCK
L4L_CDONE
ICE40_RESET
L4L_MON0
L4L_CLK_N
L4L_CLK_N
L4L_SRCLK_P
L4L_SRCLK_N
L4L_SR_SEL
3.3V_FILT_JKL
L4L_TIMING_P
L4L_TIMING_N
L4L_TIMING_THR
L4L_MONTIMING_TO_COMP
L4L_SST_P
L4L_WCLK_P
L4L_SRCLK_P
L4L_SST_N
L4L_WCLK_N
L4L_SRCLK_N
3.3V_FILT_JKL
L4L_1.2V
L4L_2.5V
L4L_2.5V
L4L_SHOUT
L4L_DOE_P
L4L_DOE_N
L4L_RD_EN
L4L_RAMP
L4L_CLR
L4L_PT
L4L_PCLK
L4L_SCLK
L4L_SIN
L4L_UPDATE
L4L_REGCLR
L4L_SS_INCR
L4L_SEL_ANY
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
48
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address is 10
Address is 12
1
VCC
2
VOUTA
3
VOUTB
4
VOUTC
5
VOUTD
6
CA2
7
CAO
8
SCL
16
GND
15
VOUTH
14
VOUTG
13
VOUTF
12
VOUTE
11
REF
10
CA1
9
SDA
U4L
LTC2637
1
VCC
7
REF
5
SCL
6
SDA
4
CA0
10
GND
2
VOUTA
3
VOUTB
8
VOUTC
9
VOUTD
U5L
LTC2635_EP
-
+
2
1
3
U6L
LT6003
1
2
R19L
16k
1
2
R20L
16k
C3L
0.1
uF
C4L
0.1 uF
C5L
0.1 uF
C22L
0.1 uF
C21L
0.1 uF
VPEDL
C28L
0.1 uF
3.3V_FILT_JKL
L4L_VBIAS2
L4L_ISEL
L4L_SBBIAS
L4L_CMPBIAS
L4L_VBS
L4L_TIMING_THR
L4L_SCL
L4L_SDA
L4L_SCL
L4L_SDA
L4L_VDLYP
L4L_VDLYN
L4L_ROVDD
L4L_VPED_BUFF
L4L_VPED
L4L_VBIAS
3.3V_FILT_JKL
3.3V_FILT_JKL
L4L_2.5V
3.3V_FILT_JKL
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
49
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Pass
Block
1
3
4
2
F2L
LP_FILT_4TERM
1200 MHz
LFCN-1200+
Block
Pass
4
2
1
3
F1L
HFCV-145+
2
IN
5
IN
6
IN
1
GND
4
P2
3
P1
U7L
RF_SPLITTER
4
3
1
2
U8L
EXB24AT2
0 dB
2
1
R11L
475
C29L
0.1
uF
3
4
1
2
6
T1L
TCD-XX-4X+
1
2
R10L
50
C31L
470 pF
L4L_RF
L4L_RF_SYNC
L4L_RFP_IN
L4L_RFIN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
50
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
1
SUM
2
GND
8
P1
7
P2
6
P3
5
P4
4
P5
3
P6
U7
AD6PS
1
SUM
2
GND
8
P1
7
P2
6
P3
5
P4
4
P5
3
P6
U8
AD6PS
RF_SYNC_1
RF_SYNC_2
L4A_RF_SYNC
L4B_RF_SYNC
L4C_RF_SYNC
L4F_RF_SYNC
L4D_RF_SYNC
L4E_RF_SYNC
L4G_RF_SYNC
L4H_RF_SYNC
L4I_RF_SYNC
L4L_RF_SYNC
L4J_RF_SYNC
L4K_RF_SYNC
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
51
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
BRSVP1A5
+5V
TCK
3.3V
3.3V
3.3V
3.3V
3.3V
+5V
3.3V
3.3V
INTC
TMS
TRST
+12V
TDO
M66EN
+5V
TDI
INTD
INTS
PCI_LOCK
ACK64
+5V
3.3V
Original TURF interface used J4 rows D & E
TD[7:0] are the primary data bus
SREQ indicates the SURF is holding the bus
TREQ indicates that the TURF wants the bus
SURF is the bus master
SCLK+/- is the bus clock.
TCLK+/- is the data-synchronous TURF clock
HOLD0/1/2/3 indicate that an event should be held/readout
REFCLK+/- is the GLITC reference clock
I/Os to FPGA:
16 - TD[7:0]
TREQ, SREQ (probably only TREQ)
4 - HOLD[0:3]
SCLK+/-
So 20 total
Row A
Row B
Row C
Row D
Row E
Row F
102
A25
103
A24
104
A23
105
A22
106
A21
107
A20
108
A19
109
A18
110
A17
111
A16
112
A15
113
A11
114
A10
115
A9
116
A8
117
A7
118
A6
119
A5
120
A4
121
A3
122
A2
123
A1
1
F13
2
F12
3
F11
4
F10
5
F9
7
F7
6
F8
8
F6
9
F5
10
F4
11
F3
12
F2
13
F1
125
PG
2
124
PG
1
101
B1
100
B2
99
B3
98
B4
97
B5
96
B6
95
B7
94
B8
93
B9
92
B10
91
B11
90
B15
89
B16
88
B17
87
B18
86
B19
85
B20
84
B21
83
B22
82
B23
81
B24
80
B25
79
C1
78
C2
77
C3
76
C4
75
C5
74
C6
73
C7
72
C8
71
C9
70
C10
69
C11
68
C15
67
C16
66
C17
65
C18
64
C19
63
C20
62
C21
61
C22
60
C23
59
C24
58
C25
36
D25
37
D24
38
D23
39
D22
40
D21
41
D20
42
D19
43
D18
44
D17
45
D16
46
D15
47
D11
48
D10
49
D9
50
D8
51
D7
52
D6
53
D5
54
D4
55
D3
56
D2
57
D1
14
E25
15
E24
16
E23
17
E22
18
E21
19
E20
20
E19
21
E18
22
E17
23
E16
24
E15
25
E11
26
E10
27
E9
28
E8
29
E7
30
E6
31
E5
32
E4
33
E3
34
E2
35
E1
J25
CPCI_J1
Row A
Row B
Row C
Row D
Row E
Row F
102
A25
103
A24
104
A23
105
A22
106
A21
107
A20
108
A19
109
A18
110
A17
111
A16
112
A15
113
A11
114
A10
115
A9
116
A8
117
A7
118
A6
119
A5
120
A4
121
A3
122
A2
123
A1
1
F13
2
F12
3
F11
4
F10
5
F9
7
F7
6
F8
8
F6
9
F5
10
F4
11
F3
12
F2
13
F1
125
PG
2
124
PG
1
101
B1
100
B2
99
B3
98
B4
97
B5
96
B6
95
B7
94
B8
93
B9
92
B10
91
B11
90
B15
89
B16
88
B17
87
B18
86
B19
85
B20
84
B21
83
B22
82
B23
81
B24
80
B25
79
C1
78
C2
77
C3
76
C4
75
C5
74
C6
73
C7
72
C8
71
C9
70
C10
69
C11
68
C15
67
C16
66
C17
65
C18
64
C19
63
C20
62
C21
61
C22
60
C23
59
C24
58
C25
36
D25
37
D24
38
D23
39
D22
40
D21
41
D20
42
D19
43
D18
44
D17
45
D16
46
D15
47
D11
48
D10
49
D9
50
D8
51
D7
52
D6
53
D5
54
D4
55
D3
56
D2
57
D1
14
E25
15
E24
16
E23
17
E22
18
E21
19
E20
20
E19
21
E18
22
E17
23
E16
24
E15
25
E11
26
E10
27
E9
28
E8
29
E7
30
E6
31
E5
32
E4
33
E3
34
E2
35
E1
J26
CPCI_J4
1
2
R70
2k
1
2
R71
2k
1
X3
CPCI_FP_BOT_BRACKET
1
X4
CPCI_FP_TOP_BRACKET
wedgelock
1
2
3
4
5
6
7
8
9
10
11
12
13
X5
FP_WEDGE_LOCK
wedgelock
1
2
3
4
5
6
7
8
9
10
11
12
13
X6
FP_WEDGE_LOCK
C10
100 pF
C12
100 pF
C9
100 pF
C11
100 pF
CPCI_AD1
CPCI_AD7
CPCI_AD12
CPCI_SERR
CPCI_DEVSEL
CPCI_AD18
CPCI_AD21
CPCI_C/BE3
CPCI_AD26
CPCI_AD30
PCI_REQ
IPMB_PWR
CPCI_INTA
CPCI_AD4
CPCI_AD9
CPCI_AD15
IPMI_SCL
CPCI_FRAME
CPCI_AD3
CPCI_AD8
CPCI_AD14
IPMI_SDA
CPCI_IRDY
CPCI_AD16
CPCI_AD23
CPCI_AD28
CPCI_RST
CPCI_AD17
CPCI_AD29
CPCI_AD0
CPCI_AD6
CPCI_AD11
CPCI_PAR
CPCI_STOP
CPCI_AD20
CPCI_AD25
PCI_CLK
CPCI_AD2
CPCI_AD5
CPCI_C/BE0
CPCI_AD10
CPCI_AD13
CPCI_C/BE1
CPCI_PERR
CPCI_TRDY
CPCI_C/BE2
CPCI_AD19
CPCI_AD22
CPCI_AD24
CPCI_AD27
CPCI_AD31
PCI_GNT
3.3V_IN
-12V
3.3V_IN
+12V
CPCI_IDSEL
PCI_HEALTHY
CPCI_ENUM
PCI_VIO
3.3V_EARLY
PCI_VIO
PCI_VIO
PCI_VIO
3.3V_EARLY
VIO_EARLY
+5V_EARLY
GND
GND
GND
GND
GND
GND
GND
+5V_EARLY
3.3V_IN
SREQ
TREQ
HOLD0
HOLD1
HOLD2
HOLD3
SCLK_P
SCLK_N
T_SCL
TCK_2V5
TMS_2V5
TDI_2V5
TDO_2V5
2.5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TCLK_P
TCLK_N
PPS_P
PPS_N
LAB4_SST_P
TD_P7
TD_P6
TD_P5
TD_P4
TD_P3
TD_P2
TD_P1
TD_P0
2.5V
T_SDA
LAB4_SST_N
TD_N7
TD_N6
TD_N5
TD_N4
TD_N3
TD_N2
TD_N1
TD_N0
TMGT_CLK_P
TMGT_CLK_N
TMGT_RX_P
TMGT_RX_N
TMGT_TX_P
TMGT_TX_N
MGT_CLK_N
MGT_CLK_P
MGT_TX_P
MGT_TX_N
+5V_IN
+5V_IN
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
52
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
AC25
VCCO_13
T16
VCCO_13
T26
VCCO_13
U23
VCCO_13
V20
VCCO_13
Y24
VCCO_13
AB24
IO_L9P_T1_DQS_13
AC24
IO_L9N_T1_DQS_13
AA22
IO_L8P_T1_13
AA23
IO_L8N_T1_13
AA24
IO_L7P_T1_13
AB25
IO_L7N_T1_13
V24
IO_L6P_T0_13
W24
IO_L6N_T0_VREF_13
Y25
IO_L5P_T0_13
AA25
IO_L5N_T0_13
W25
IO_L4P_T0_13
Y26
IO_L4N_T0_13
AB26
IO_L3P_T0_DQS_13
AC26
IO_L3N_T0_DQS_13
V26
IO_L2P_T0_13
W26
IO_L2N_T0_13
V16
IO_L24P_T3_13
V17
IO_L24N_T3_13
U14
IO_L23P_T3_13
V14
IO_L23N_T3_13
U15
IO_L22P_T3_13
U16
IO_L22N_T3_13
T17
IO_L21P_T3_DQS_13
T18
IO_L21N_T3_DQS_13
T14
IO_L20P_T3_13
T15
IO_L20N_T3_13
U25
IO_L1P_T0_13
U26
IO_L1N_T0_13
V18
IO_L19P_T3_13
W18
IO_L19N_T3_VREF_13
V19
IO_L18P_T2_13
W19
IO_L18N_T2_13
T19
IO_L17P_T2_13
U19
IO_L17N_T2_13
W20
IO_L16P_T2_13
Y20
IO_L16N_T2_13
T20
IO_L15P_T2_DQS_13
U20
IO_L15N_T2_DQS_13
W21
IO_L14P_T2_SRCC_13
Y21
IO_L14N_T2_SRCC_13
U21
IO_L13P_T2_MRCC_13
V21
IO_L13N_T2_MRCC_13
U22
IO_L12P_T1_MRCC_13
V22
IO_L12N_T1_MRCC_13
Y22
IO_L11P_T1_SRCC_13
Y23
IO_L11N_T1_SRCC_13
V23
IO_L10P_T1_13
W23
IO_L10N_T1_13
U17
IO_25_13
U24
IO_0_13
U1-A
XC7A200TFBG676
K24
VCCO_14
L21
VCCO_14
N15
VCCO_14
N25
VCCO_14
P22
VCCO_14
R19
VCCO_14
L24
IO_L9P_T1_DQS_14
L25
IO_L9N_T1_DQS_D13_14
M20
IO_L8P_T1_D11_14
L20
IO_L8N_T1_D12_14
K25
IO_L7P_T1_D09_14
K26
IO_L7N_T1_D10_14
P18
IO_L6P_T0_FCS_B_14
N18
IO_L6N_T0_D08_VREF_14
R16
IO_L5P_T0_D06_14
R17
IO_L5N_T0_D07_14
N16
IO_L4P_T0_D04_14
N17
IO_L4N_T0_D05_14
P15
IO_L3P_T0_DQS_PUDC_B_14
P16
IO_L3N_T0_DQS_EMCCLK_14
P14
IO_L2P_T0_D02_14
N14
IO_L2N_T0_D03_14
T23
IO_L24P_T3_A01_D17_14
R23
IO_L24N_T3_A00_D16_14
T22
IO_L23P_T3_A03_D19_14
R22
IO_L23N_T3_A02_D18_14
R26
IO_L22P_T3_A05_D21_14
P26
IO_L22N_T3_A04_D20_14
T24
IO_L21P_T3_DQS_14
T25
IO_L21N_T3_DQS_A06_D22_14
N26
IO_L20P_T3_A08_D24_14
M26
IO_L20N_T3_A07_D23_14
R14
IO_L1P_T0_D00_MOSI_14
R15
IO_L1N_T0_D01_DIN_14
R25
IO_L19P_T3_A10_D26_14
P25
IO_L19N_T3_A09_D25_VREF_14
R20
IO_L18P_T2_A12_D28_14
R21
IO_L18N_T2_A11_D27_14
P23
IO_L17P_T2_A14_D30_14
P24
IO_L17N_T2_A13_D29_14
P19
IO_L16P_T2_CSI_B_14
N19
IO_L16N_T2_A15_D31_14
N23
IO_L15P_T2_DQS_RDWR_B_14
N24
IO_L15N_T2_DQS_DOUT_CSO_B_14
P20
IO_L14P_T2_SRCC_14
P21
IO_L14N_T2_SRCC_14
N21
IO_L13P_T2_MRCC_14
N22
IO_L13N_T2_MRCC_14
M21
IO_L12P_T1_MRCC_14
M22
IO_L12N_T1_MRCC_14
L22
IO_L11P_T1_SRCC_14
L23
IO_L11N_T1_SRCC_14
M24
IO_L10P_T1_D14_14
M25
IO_L10N_T1_D15_14
R18
IO_25_14
M19
IO_0_14
U1-B
XC7A200TFBG676
F26
VCCO_15
G23
VCCO_15
H20
VCCO_15
J17
VCCO_15
K14
VCCO_15
M18
VCCO_15
K20
IO_L9P_T1_DQS_AD3P_15
J20
IO_L9N_T1_DQS_AD3N_15
L17
IO_L8P_T1_AD10P_15
L18
IO_L8N_T1_AD10N_15
J19
IO_L7P_T1_AD2P_15
H19
IO_L7N_T1_AD2N_15
M16
IO_L6P_T0_15
M17
IO_L6N_T0_VREF_15
M15
IO_L5P_T0_AD9P_15
L15
IO_L5N_T0_AD9N_15
M14
IO_L4P_T0_15
L14
IO_L4N_T0_15
K16
IO_L3P_T0_DQS_AD1P_15
K17
IO_L3N_T0_DQS_AD1N_15
J14
IO_L2P_T0_AD8P_15
J15
IO_L2N_T0_AD8N_15
J25
IO_L24P_T3_RS1_15
J26
IO_L24N_T3_RS0_15
G25
IO_L23P_T3_FOE_B_15
F25
IO_L23N_T3_FWE_B_15
H26
IO_L22P_T3_A17_15
G26
IO_L22N_T3_A16_15
E26
IO_L21P_T3_DQS_15
D26
IO_L21N_T3_DQS_A18_15
E25
IO_L20P_T3_A20_15
D25
IO_L20N_T3_A19_15
K15
IO_L1P_T0_AD0P_15
J16
IO_L1N_T0_AD0N_15
G24
IO_L19P_T3_A22_15
F24
IO_L19N_T3_A21_VREF_15
K22
IO_L18P_T2_A24_15
K23
IO_L18N_T2_A23_15
F23
IO_L17P_T2_A26_15
E23
IO_L17N_T2_A25_15
J24
IO_L16P_T2_A28_15
H24
IO_L16N_T2_A27_15
G22
IO_L15P_T2_DQS_15
F22
IO_L15N_T2_DQS_ADV_B_15
J23
IO_L14P_T2_SRCC_15
H23
IO_L14N_T2_SRCC_15
H21
IO_L13P_T2_MRCC_15
H22
IO_L13N_T2_MRCC_15
K21
IO_L12P_T1_MRCC_15
J21
IO_L12N_T1_MRCC_15
G20
IO_L11P_T1_SRCC_15
G21
IO_L11N_T1_SRCC_15
J18
IO_L10P_T1_AD11P_15
H18
IO_L10N_T1_AD11N_15
L19
IO_25_15
K18
IO_0_15
U1-C
XC7A200TFBG676
A21
VCCO_16
B18
VCCO_16
C25
VCCO_16
D22
VCCO_16
E19
VCCO_16
F16
VCCO_16
A17
IO_L9P_T1_DQS_16
A18
IO_L9N_T1_DQS_16
E16
IO_L8P_T1_16
D16
IO_L8N_T1_16
C17
IO_L7P_T1_16
B17
IO_L7N_T1_16
H16
IO_L6P_T0_16
G16
IO_L6N_T0_VREF_16
G19
IO_L5P_T0_16
F20
IO_L5N_T0_16
G15
IO_L4P_T0_16
F15
IO_L4N_T0_16
F18
IO_L3P_T0_DQS_16
F19
IO_L3N_T0_DQS_16
G17
IO_L2P_T0_16
F17
IO_L2N_T0_16
D23
IO_L24P_T3_16
D24
IO_L24N_T3_16
C24
IO_L23P_T3_16
B24
IO_L23N_T3_16
C26
IO_L22P_T3_16
B26
IO_L22N_T3_16
A23
IO_L21P_T3_DQS_16
A24
IO_L21N_T3_DQS_16
B25
IO_L20P_T3_16
A25
IO_L20N_T3_16
H14
IO_L1P_T0_16
H15
IO_L1N_T0_16
C22
IO_L19P_T3_16
C23
IO_L19N_T3_VREF_16
E21
IO_L18P_T2_16
D21
IO_L18N_T2_16
B22
IO_L17P_T2_16
A22
IO_L17N_T2_16
C21
IO_L16P_T2_16
B21
IO_L16N_T2_16
B20
IO_L15P_T2_DQS_16
A20
IO_L15N_T2_DQS_16
E20
IO_L14P_T2_SRCC_16
D20
IO_L14N_T2_SRCC_16
D19
IO_L13P_T2_MRCC_16
C19
IO_L13N_T2_MRCC_16
D18
IO_L12P_T1_MRCC_16
C18
IO_L12N_T1_MRCC_16
E17
IO_L11P_T1_SRCC_16
E18
IO_L11N_T1_SRCC_16
B19
IO_L10P_T1_16
A19
IO_L10N_T1_16
E22
IO_25_16
H17
IO_0_16
U1-D
XC7A200TFBG676
K4
VCCO_34
L1
VCCO_34
M8
VCCO_34
N5
VCCO_34
P2
VCCO_34
T6
VCCO_34
N1
IO_L9P_T1_DQS_34
M1
IO_L9N_T1_DQS_34
L3
IO_L8P_T1_34
K2
IO_L8N_T1_34
K1
IO_L7P_T1_34
J1
IO_L7N_T1_34
M6
IO_L6P_T0_34
M5
IO_L6N_T0_VREF_34
N7
IO_L5P_T0_34
N6
IO_L5N_T0_34
L5
IO_L4P_T0_34
K5
IO_L4N_T0_34
M4
IO_L3P_T0_DQS_34
L4
IO_L3N_T0_DQS_34
M7
IO_L2P_T0_34
L7
IO_L2N_T0_34
T8
IO_L24P_T3_34
T7
IO_L24N_T3_34
R7
IO_L23P_T3_34
R6
IO_L23N_T3_34
R8
IO_L22P_T3_34
P8
IO_L22N_T3_34
U6
IO_L21P_T3_DQS_34
U5
IO_L21N_T3_DQS_34
T5
IO_L20P_T3_34
R5
IO_L20N_T3_34
K3
IO_L1P_T0_34
J3
IO_L1N_T0_34
P6
IO_L19P_T3_34
P5
IO_L19N_T3_VREF_34
U2
IO_L18P_T2_34
U1
IO_L18N_T2_34
T2
IO_L17P_T2_34
R2
IO_L17N_T2_34
T4
IO_L16P_T2_34
T3
IO_L16N_T2_34
R1
IO_L15P_T2_DQS_34
P1
IO_L15N_T2_DQS_34
P4
IO_L14P_T2_SRCC_34
N4
IO_L14N_T2_SRCC_34
R3
IO_L13P_T2_MRCC_34
P3
IO_L13N_T2_MRCC_34
N3
IO_L12P_T1_MRCC_34
N2
IO_L12N_T1_MRCC_34
M2
IO_L11P_T1_SRCC_34
L2
IO_L11N_T1_SRCC_34
H2
IO_L10P_T1_34
H1
IO_L10N_T1_34
U4
IO_25_34
N8
IO_0_34
U1-E
XC7A200TFBG676
A1
VCCO_35
C5
VCCO_35
D2
VCCO_35
F6
VCCO_35
G3
VCCO_35
J7
VCCO_35
J4
IO_L9P_T1_DQS_AD7P_35
H4
IO_L9N_T1_DQS_AD7N_35
L8
IO_L8P_T1_AD14P_35
K8
IO_L8N_T1_AD14N_35
J6
IO_L7P_T1_AD6P_35
J5
IO_L7N_T1_AD6N_35
H9
IO_L6P_T0_35
G9
IO_L6N_T0_VREF_35
H6
IO_L5P_T0_AD13P_35
G6
IO_L5N_T0_AD13N_35
F8
IO_L4P_T0_35
F7
IO_L4N_T0_35
H7
IO_L3P_T0_DQS_AD5P_35
G7
IO_L3N_T0_DQS_AD5N_35
H8
IO_L2P_T0_AD12P_35
G8
IO_L2N_T0_AD12N_35
G2
IO_L24P_T3_35
G1
IO_L24N_T3_35
E1
IO_L23P_T3_35
D1
IO_L23N_T3_35
F2
IO_L22P_T3_35
E2
IO_L22N_T3_35
C1
IO_L21P_T3_DQS_35
B1
IO_L21N_T3_DQS_35
A3
IO_L20P_T3_35
A2
IO_L20N_T3_35
E6
IO_L1P_T0_AD4P_35
D6
IO_L1N_T0_AD4N_35
C2
IO_L19P_T3_35
B2
IO_L19N_T3_VREF_35
F3
IO_L18P_T2_35
E3
IO_L18N_T2_35
D3
IO_L17P_T2_35
C3
IO_L17N_T2_35
B4
IO_L16P_T2_35
A4
IO_L16N_T2_35
B5
IO_L15P_T2_DQS_35
A5
IO_L15N_T2_DQS_35
D4
IO_L14P_T2_SRCC_35
C4
IO_L14N_T2_SRCC_35
E5
IO_L13P_T2_MRCC_35
D5
IO_L13N_T2_MRCC_35
G5
IO_L12P_T1_MRCC_35
F5
IO_L12N_T1_MRCC_35
G4
IO_L11P_T1_SRCC_35
F4
IO_L11N_T1_SRCC_35
K7
IO_L10P_T1_AD15P_35
K6
IO_L10N_T1_AD15N_35
H3
IO_25_35
J8
IO_0_35
U1-F
XC7A200TFBG676
AF15
MGTRREF_213
AA11
MGTREFCLK1P_213
AB11
MGTREFCLK1N_213
AA13
MGTREFCLK0P_213
AB13
MGTREFCLK0N_213
AE7
MGTPTXP3_213
AC8
MGTPTXP2_213
AE9
MGTPTXP1_213
AC10
MGTPTXP0_213
AF7
MGTPTXN3_213
AD8
MGTPTXN2_213
AF9
MGTPTXN1_213
AD10
MGTPTXN0_213
AE11
MGTPRXP3_213
AC14
MGTPRXP2_213
AE13
MGTPRXP1_213
AC12
MGTPRXP0_213
AF11
MGTPRXN3_213
AD14
MGTPRXN2_213
AF13
MGTPRXN1_213
AD12
MGTPRXN0_213
AD15
MGTAVTT_G10
AD7
MGTAVTT_G10
AE10
MGTAVTT_G10
AE12
MGTAVTT_G10
AE14
MGTAVTT_G10
AE8
MGTAVTT_G10
AA10
MGTAVCC_G10
AA12
MGTAVCC_G10
AC11
MGTAVCC_G10
AC13
MGTAVCC_G10
AC9
MGTAVCC_G10
U1-I
XC7A200TFBG676
A15
MGTRREF_216
F13
MGTREFCLK1P_216
E13
MGTREFCLK1N_216
F11
MGTREFCLK0P_216
E11
MGTREFCLK0N_216
D10
MGTPTXP3_216
B9
MGTPTXP2_216
D8
MGTPTXP1_216
B7
MGTPTXP0_216
C10
MGTPTXN3_216
A9
MGTPTXN2_216
C8
MGTPTXN1_216
A7
MGTPTXN0_216
D12
MGTPRXP3_216
B13
MGTPRXP2_216
D14
MGTPRXP1_216
B11
MGTPRXP0_216
C12
MGTPRXN3_216
A13
MGTPRXN2_216
C14
MGTPRXN1_216
A11
MGTPRXN0_216
B10
MGTAVTT_G11
B12
MGTAVTT_G11
B14
MGTAVTT_G11
B8
MGTAVTT_G11
C15
MGTAVTT_G11
C7
MGTAVTT_G11
D11
MGTAVCC_G11
D13
MGTAVCC_G11
D9
MGTAVCC_G11
F10
MGTAVCC_G11
F12
MGTAVCC_G11
U1-J
XC7A200TFBG676
Y14
VCCO_0
W11
VCCO_0
W10
DONE_0
H12
TCK_0
G14
VCCBATT_0
P11
VN_0
P12
VREFP_0
M11
GNDADC_0
M12
VCCADC_0
R12
DXP_0
H13
CCLK_0
N12
VP_0
N11
VREFN_0
R11
DXN_0
J10
TDO_0
H10
TDI_0
V11
INIT_B_0
Y9
M1_0
AB7
M0_0
H11
TMS_0
AE16
PROGRAM_B_0
AB15
CFGBVS_0
W9
M2_0
U1-K
XC7A200TFBG676
J11
VCCIN
T
J13
VCCIN
T
K10
VCCIN
T
K12
VCCIN
T
L11
VCCIN
T
L13
VCCIN
T
M10
VCCIN
T
P10
VCCIN
T
T10
VCCIN
T
T12
VCCIN
T
U11
VCCIN
T
V10
VCCIN
T
V12
VCCIN
T
L9
VCCAU
X
N9
VCCAU
X
R9
VCCAU
X
U9
VCCAU
X
J9
VCCAU
X
N13
VCCBRAM
R13
VCCBRAM
U13
VCCBRAM
W13
VCCBRAM
AE15
GN
D
B15
GN
D
A10
GN
D
A12
GN
D
A14
GN
D
A16
GN
D
A26
GN
D
A6
GN
D
A8
GN
D
AA14
GN
D
AA16
GN
D
AA26
GN
D
AA6
GN
D
AB10
GN
D
AB12
GN
D
AB14
GN
D
AB23
GN
D
AB3
GN
D
AA9
GN
D
AB8
GN
D
AC15
GN
D
AC20
GN
D
AC7
GN
D
AD
11
GN
D
AD
13
GN
D
AD
6
GN
D
AD
9
GN
D
AD
16
GN
D
AE24
GN
D
AE4
GN
D
AE6
GN
D
AF1
GN
D
AF10
GN
D
AF12
GN
D
AF14
GN
D
AF16
GN
D
AF21
GN
D
AF6
GN
D
AF8
GN
D
B16
GN
D
B23
GN
D
B3
GN
D
B6
GN
D
C11
GN
D
C13
GN
D
C16
GN
D
C20
GN
D
C6
GN
D
C9
GN
D
D15
GN
D
D17
GN
D
D7
GN
D
E10
GN
D
E12
GN
D
E14
GN
D
E24
GN
D
E4
GN
D
E7
GN
D
E8
GN
D
E9
GN
D
F1
GN
D
F14
GN
D
F21
GN
D
F9
GN
D
G10
GN
D
G11
GN
D
AB9
GN
D
G13
GN
D
Y12
GN
D
G18
GN
D
G12
GN
D
H25
GN
D
H5
GN
D
J12
GN
D
J2
GN
D
J22
GN
D
K11
GN
D
K13
GN
D
K19
GN
D
K9
GN
D
L10
GN
D
L12
GN
D
L16
GN
D
L26
GN
D
L6
GN
D
M13
GN
D
M23
GN
D
M3
GN
D
M9
GN
D
N10
GN
D
N20
GN
D
P13
GN
D
P17
GN
D
P7
GN
D
P9
GN
D
R10
GN
D
R24
GN
D
R4
GN
D
T1
GN
D
T11
GN
D
T13
GN
D
T21
GN
D
T9
GN
D
U10
GN
D
U12
GN
D
U18
GN
D
U8
GN
D
V15
GN
D
V25
GN
D
V5
GN
D
E15
GN
D
W12
GN
D
W2
GN
D
W22
GN
D
Y11
GN
D
Y10
GN
D
Y13
GN
D
Y19
GN
D
V13
GN
D
U1-L
XC7A200TFBG676
AA21
VCCO_12
AB18
VCCO_12
AD22
VCCO_12
AE19
VCCO_12
AF26
VCCO_12
W17
VCCO_12
AE22
IO_L9P_T1_DQS_12
AF22
IO_L9N_T1_DQS_12
AF19
IO_L8P_T1_12
AF20
IO_L8N_T1_12
AD21
IO_L7P_T1_12
AE21
IO_L7N_T1_12
AD23
IO_L6P_T0_12
AD24
IO_L6N_T0_VREF_12
AE23
IO_L5P_T0_12
AF23
IO_L5N_T0_12
AD25
IO_L4P_T0_12
AD26
IO_L4N_T0_12
AF24
IO_L3P_T0_DQS_12
AF25
IO_L3N_T0_DQS_12
AC22
IO_L2P_T0_12
AC23
IO_L2N_T0_12
W14
IO_L24P_T3_12
W15
IO_L24N_T3_12
Y15
IO_L23P_T3_12
AA15
IO_L23N_T3_12
AB16
IO_L22P_T3_12
AC16
IO_L22N_T3_12
Y16
IO_L21P_T3_DQS_12
Y17
IO_L21N_T3_DQS_12
AC17
IO_L20P_T3_12
AD17
IO_L20N_T3_12
AE25
IO_L1P_T0_12
AE26
IO_L1N_T0_12
AA17
IO_L19P_T3_12
AB17
IO_L19N_T3_VREF_12
AE17
IO_L18P_T2_12
AF17
IO_L18N_T2_12
Y18
IO_L17P_T2_12
AA18
IO_L17N_T2_12
AE18
IO_L16P_T2_12
AF18
IO_L16N_T2_12
AC18
IO_L15P_T2_DQS_12
AD18
IO_L15N_T2_DQS_12
AC19
IO_L14P_T2_SRCC_12
AD19
IO_L14N_T2_SRCC_12
AA19
IO_L13P_T2_MRCC_12
AB19
IO_L13N_T2_MRCC_12
AA20
IO_L12P_T1_MRCC_12
AB20
IO_L12N_T1_MRCC_12
AB21
IO_L11P_T1_SRCC_12
AC21
IO_L11N_T1_SRCC_12
AD20
IO_L10P_T1_12
AE20
IO_L10N_T1_12
W16
IO_25_12
AB22
IO_0_12
U1-G
XC7A200TFBG676
AA1
VCCO_33
AC5
VCCO_33
AD2
VCCO_33
U3
VCCO_33
W7
VCCO_33
Y4
VCCO_33
AD1
IO_L9P_T1_DQS_33
AE1
IO_L9N_T1_DQS_33
Y2
IO_L8P_T1_33
Y1
IO_L8N_T1_33
AB1
IO_L7P_T1_33
AC1
IO_L7N_T1_33
U7
IO_L6P_T0_33
V7
IO_L6N_T0_VREF_33
W3
IO_L5P_T0_33
Y3
IO_L5N_T0_33
V6
IO_L4P_T0_33
W6
IO_L4N_T0_33
V3
IO_L3P_T0_DQS_33
V2
IO_L3N_T0_DQS_33
W5
IO_L2P_T0_33
W4
IO_L2N_T0_33
AB6
IO_L24P_T3_33
AC6
IO_L24N_T3_33
Y8
IO_L23P_T3_33
AA8
IO_L23N_T3_33
AA5
IO_L22P_T3_33
AB5
IO_L22N_T3_33
V8
IO_L21P_T3_DQS_33
W8
IO_L21N_T3_DQS_33
Y6
IO_L20P_T3_33
Y5
IO_L20N_T3_33
V1
IO_L1P_T0_33
W1
IO_L1N_T0_33
Y7
IO_L19P_T3_33
AA7
IO_L19N_T3_VREF_33
AC4
IO_L18P_T2_33
AD4
IO_L18N_T2_33
AF5
IO_L17P_T2_33
AF4
IO_L17N_T2_33
AE3
IO_L16P_T2_33
AF3
IO_L16N_T2_33
AD5
IO_L15P_T2_DQS_33
AE5
IO_L15N_T2_DQS_33
AC3
IO_L14P_T2_SRCC_33
AD3
IO_L14N_T2_SRCC_33
AA4
IO_L13P_T2_MRCC_33
AB4
IO_L13N_T2_MRCC_33
AA3
IO_L12P_T1_MRCC_33
AA2
IO_L12N_T1_MRCC_33
AB2
IO_L11P_T1_SRCC_33
AC2
IO_L11N_T1_SRCC_33
AE2
IO_L10P_T1_33
AF2
IO_L10N_T1_33
V9
IO_25_33
V4
IO_0_33
U1-H
XC7A200TFBG676
1
2
R38
100
2
VCC
14
VIO
7
CS
3
RESET
16
SCK
10
VSS
15
IO0
8
IO1
9
IO2
1
IO3
U3
S25FLXXXS
1
2
R25
33
1
2
R26
33
1
2
R27
33
1
2
R28
33
1
2
R29
100
2
1
3
D1
CX21
???
J33-1
J33-2
J33-3
J33-4
J33-5
J33-6
CX152
0.1 uF
1V
1.8V
1V
L4A_TIMING_P
L4A_TIMING_N
L4A_WCLK_P
L4A_WCLK_N
L4A_WR1
L4A_WR_EN
L4A_TX_P
L4A_TX_N
L4A_RX_P
L4A_RX_N
L4A_CLK_P
L4A_CLK_N
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
L4B_RX_P
L4B_RX_N
L4B_TX_P
L4B_TX_N
L4B_CLK_P
L4B_CLK_N
3.3VCCO
PCI_DEVSEL
PCI_FRAME
PCI_GNT
PCI_IDSEL
PCI_CLK
PCI_INTA
PCI_IRDY
PCI_PAR
PCI_PERR
PCI_REQ
PCI_RST
PCI_SERR
PCI_STOP
PCI_TRDY
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
MGT_1V
MGT_1.2V
MGT_1.2V
L4C_TX_P
L4C_TX_N
L4C_RX_P
L4C_RX_N
L4C_CLK_P
L4C_CLK_N
L4D_RX_P
L4D_RX_N
L4D_TX_P
L4D_TX_N
L4D_CLK_P
L4D_CLK_N
L4E_RX_P
L4E_RX_N
L4E_TX_P
L4E_TX_N
L4E_CLK_P
L4E_CLK_N
L4F_RX_P
L4F_RX_N
L4F_TX_P
L4F_TX_N
L4F_CLK_P
L4F_CLK_N
L4G_TX_P
L4G_TX_N
L4G_RX_P
L4G_RX_N
L4G_CLK_P
L4G_CLK_N
L4H_RX_P
L4H_RX_N
L4H_CLK_P
L4H_CLK_N
L4H_TX_P
L4H_TX_N
L4I_RX_P
L4I_RX_N
L4I_TX_P
L4I_TX_N
L4I_CLK_P
L4I_CLK_N
L4J_RX_P
L4J_RX_N
L4J_TX_P
L4J_TX_N
L4J_CLK_P
L4J_CLK_N
L4K_RX_P
L4K_RX_N
L4K_TX_P
L4K_TX_N
L4K_CLK_P
L4K_CLK_N
L4L_RX_P
L4L_RX_N
L4L_TX_P
L4L_TX_N
L4L_CLK_P
L4L_CLK_N
2.5V
L4A_WR3
L4A_WR0
L4A_WR2
L4A_WR4
L4A_SCL
L4A_SDA
L4B_WR_EN
L4B_WR1
L4B_WR3
L4B_WR0
L4B_WR2
L4B_WR4
L4B_WCLK_P
L4B_WCLK_N
L4B_TIMING_P
L4B_TIMING_N
L4B_SCL
L4B_SDA
SPI_D0_MOSI
SPI_D1_MISO
SPI_D2
SPI_D3
SPI_CS
2.5V
L4C_TIMING_P
L4C_TIMING_N
L4C_WCLK_P
L4C_WCLK_N
L4C_WR_EN
L4C_WR1
L4C_WR3
L4C_WR0
L4C_WR2
L4C_WR4
L4C_SCL
L4C_SDA
L4D_TIMING_P
L4D_TIMING_N
L4D_WCLK_P
L4D_WCLK_N
L4D_WR_EN
L4D_WR1
L4D_WR3
L4D_WR0
L4D_WR2
L4D_WR4
L4D_SCL
L4D_SDA
L4E_TIMING_P
L4E_TIMING_N
L4E_WCLK_P
L4E_WCLK_N
L4E_WR_EN
L4E_WR1
L4E_WR3
L4E_WR0
L4E_WR2
L4E_WR4
L4F_TIMING_P
L4F_TIMING_N
L4F_WCLK_N
L4F_WCLK_P
L4F_WR_EN
L4F_WR1
L4F_WR3
L4F_WR0
L4F_WR2
L4F_WR4
L4E_SDA
L4E_SCL
L4F_SCL
L4F_SDA
L4G_TIMING_P
L4G_TIMING_N
L4G_WCLK_P
L4G_WCLK_N
L4G_WR_EN
L4G_WR1
L4G_WR3
L4G_WR0
L4G_WR2
L4G_WR4
L4G_SCL
L4G_SDA
L4H_TIMING_P
L4H_TIMING_N
L4H_WCLK_P
L4H_WCLK_N
L4H_WR_EN
L4H_WR1
L4H_WR3
L4H_WR0
L4H_WR2
L4H_WR4
L4H_SCL
L4H_SDA
L4I_TIMING_P
L4I_TIMING_N
L4I_WCLK_P
L4I_WCLK_N
3.3V
SPI_CS
SPI_SCK
SPI_D0_MOSI
SPI_D1_MISO
SPI_D2
SPI_D3
SPI_2.5V
3.3V
L4I_WR_EN
L4I_WR1
L4I_WR3
L4I_WR2
L4I_WR4
L4I_WR0
L4I_SCL
L4I_SDA
L4J_TIMING_P
L4J_TIMING_N
L4J_WCLK_N
L4J_WCLK_P
L4J_WR_EN
L4J_WR1
L4J_WR3
L4J_WR0
L4J_WR2
L4J_WR4
L4J_SDA
L4J_SCL
L4K_TIMING_P
L4K_TIMING_N
L4K_WCLK_P
L4K_WCLK_N
L4K_WR_EN
L4K_WR1
L4K_WR3
L4K_WR0
L4K_WR2
L4K_WR4
L4L_WCLK_P
L4L_WCLK_N
L4K_SDA
L4K_SCL
L4L_TIMING_P
L4L_TIMING_N
L4L_WR1
L4L_WR0
L4L_WR_EN
L4L_WR3
L4L_WR2
L4L_WR4
L4L_SCL
L4L_SDA
TD_P7
TD_N7
TD_N6
TD_P6
TD_P5
TD_N5
TD_N3
TD_P3
TD_P4
TD_N4
TD_P2
TD_N2
TD_P1
TD_N1
TD_P0
TD_N0
FPGA_SST_P
FPGA_SST_N
FPGA_TURF_SST_P
FPGA_TURF_SST_N
LOCAL_CLK
LOCAL_OSC_EN
SREQ
TREQ
PPS_P
PPS_N
SCLK_P
SCLK_N
TCLK_P
TCLK_N
HOLD1
HOLD0
HOLD3
HOLD2
TMGT_TX_N
TMGT_TX_P
TMGT_RX_P
TMGT_RX_N
TMGT_CLK_P
TMGT_CLK_N
SPI_SCK
FPGA_DONE
TCK_2V5
TDO_2V5
TDI_2V5
FPGA_PROGRAM_B
FPGA_SST_SEL
UC_SDA
UC_SCL
TMS_2V5
1.8V
FPGA_INIT_B
MGT_1V
MGT_1.2V
ICE40_RESET
MON0
MON1
MON2
MON3
MON4
LED0
LED1
LED2
LED3
2.5V
SPI_CS
SPI_SCK
SPI_D0_MOSI
SPI_D1_MISO
2.5V
3.3V
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
53
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
No pullup/pulldown: undriven means no output
Place at the input of CDCLVD1212
Place at the input of CDCLVD1212
Place at input of ZL40212
Filter supply to clock buffers to reduce jitter
FPGA_SST_P/N are derived from other clocks (PCI, etc.)
if the TURF clock is not present.
1
2
R72
100
1
2
R73
100
1
2
R74
100
CX8
0.1 uF
CX7
0.1 uF
CX1
0.1 uF
CX2
0.1 uF
CX3
0.1 uF
CX4
0.1 uF
CX5
0.1 uF
CX6
0.1 uF
CX11
4.7 uF
1
2
L17
FERRITE
???
CX10
47 uF
1
2
R75
1
1
CLK_P
4
CLK_N
12
OUT0_P
11
OUT0_N
10
OUT1_P
9
OUT1_N
13
VD
D
8
VD
D
5
GN
D
16
GN
D
U91
ZL40212
7
VAC_REF0
4
VAC_REF1
2
INP1
3
INN1
9
INP0
8
INN0
1
IN_SEL
12
OUTP0
13
OUTN0
14
OUTP1
15
OUTN1
16
OUTP2
17
OUTN2
18
OUTP3
19
OUTN3
22
OUTP4
23
OUTN4
24
OUTP5
25
OUTN5
26
OUTP6
27
OUTN6
28
OUTP7
29
OUTN7
32
OUTP8
33
OUTN8
34
OUTP9
35
OUTN9
36
OUTP10
37
OUTN10
38
OUTP11
39
OUTN11
5
VCC
6
VCC
11
VCC
20
VCC
31
VCC
40
VCC
21
GN
D
30
GN
D
U90
CDCLVD1212
CX9
10 uF
E
EN
O
O
P
VCC
G
GN
D
Y1
OSC_EN
CX26
0.1 uF
2.5VCBUFF
FPGA_SST_P
FPGA_SST_N
FPGA_TURF_SST_P
FPGA_TURF_SST_N
2.5VCBUFF
LAB4_SST_P
LAB4_SST_N
2.5VCBUFF
2.5VCBUFF
FPGA_SST_SEL
2.5VCBUFF
2.5V
2.5VCBUFF
L4L_SST_P
L4L_SST_N
L4K_SST_P
L4K_SST_N
L4J_SST_P
L4J_SST_N
L4I_SST_P
L4I_SST_N
L4H_SST_P
L4H_SST_N
L4G_SST_P
L4G_SST_N
L4F_SST_P
L4F_SST_N
L4E_SST_P
L4E_SST_N
L4D_SST_P
L4D_SST_N
L4C_SST_P
L4C_SST_N
L4B_SST_P
L4B_SST_N
L4A_SST_P
L4A_SST_N
TURF_SST_P
TURF_SST_N
2.5V
LOCAL_OSC_EN
LOCAL_CLK
2.5V
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
54
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Sequenced turnon: +5V turns on, then 3.3V
VCCINT/VCCAUX turn on before VCCO
use 0.18 uF 0402: resonance frequency ~12 MHz (3rd harmonic of switching reg.)
use 0.18 uF 0402: resonance frequency ~12 MHz (3rd harmonic of switching reg.)
ADR[2:0] = LLH: address = 1001_111 (0x4F)
26
FB1
25
GPIO1
24
EN1
23
ADIN1
8
TIMER
1
SS
18
ADIN2
17
EN2
16
GPIO2
15
FB2
32
OV1
22
ON
19
SDA
20
SCL
21
ALERT
2
CONFIG
5
ADR0
6
ADR1
7
ADR2
3
INTVCC
4
GND
9
OV2
31
UV1
30
VD
D1
29
SEN
SE1-
28
GATE1
27
SO
URCE1
10
UV2
11
VD
D2
12
SEN
SE2-
13
GATE2
14
SO
URCE2
U2
LTC4222
1
2
R1
0.025
1
2
R2
0.012
Q1
Q2
1
2
R3
10k
1
2
R10
680
1
2
R11
5.7
6k
1
2
R12
3.0
9k
1
2
R13
680
1
2
R14
10k
1
2
R15
10k
1
2
R16
30.1
k
1
2
R17
16k
1
2
R18
10k
C1
???
C2
???
C3
0.1 uF
1
VIN
2
EN
6
VOUT
5
FB
4
GN
D
8
GN
D
3
SS
7
VOUT
V1
LMZ10503
13
PVIN
14
PVIN
10
AVIN1
4
AVIN2
12
ENABLE
7
VOUT
8
VOUT
5
VFB
11
POK
2
PG
ND
3
PG
ND
9
AG
ND
V2
EP53F8QI
1
2
R19
10
C4
1 uF
CX12
1 uF
CX13
10 uF
CX14
4.7 uF
CX15
22 uF
1
2
R20
237k
1
2
R21
118k
C7
5 pF
1
2
R22
56.2
k
1
2
R23
2.1
k
1
2
R24
226k
C6
270
CX16
100 uF
CX17
47 uF
CX18
0.1 uF
CX19
???
CX20
???
13
PVIN
14
PVIN
10
AVIN1
4
AVIN2
12
ENABLE
7
VOUT
8
VOUT
5
VFB
11
POK
2
PG
ND
3
PG
ND
9
AG
ND
V3
EP53F8QI
1
2
R30
10
C5
1 uF
CX22
1 uF
CX23
10 uF
CX24
4.7 uF
CX25
22 uF
1
2
R31
237k
1
2
R32
75k
C8
5 pF
1
2
R33
10k
5
VIN
6
VIN
4
EN
3
GND
1
VOUT
2
VOUT
V5
MIC94305
CX30
4.7 uF
CX31
4.7 uF
5
VIN
6
VIN
4
EN
3
GND
1
VOUT
2
VOUT
V6
MIC94305
CX32
4.7 uF
CX33
4.7 uF
5
VIN
6
VIN
4
EN
3
GND
1
VOUT
2
VOUT
V7
MIC94305
CX34
4.7 uF
CX35
4.7 uF
5
VIN
6
VIN
4
EN
3
GND
1
VOUT
2
VOUT
V8
MIC94305
CX36
4.7 uF
CX37
4.7 uF
1
2
X13
SM
_LED
1
2
R44
1k
1
2
X14
SM
_LED
1
2
R45
1k
5V_IN
3V3_IN
3V3ABC
3V3DEF
3V3GHI
3V3JKL
2V5
1V8
1V
5V
3V3
G1
G2
G3
G4
1
2
R65
10k
JP1-1
JP1-2
1
IN
3
EN
5
OUT
2
GN
D
V9
TLV71333
CX153
1 uF
3V3O
1
2
R76
10k
1
BIAS
3
IN
4
IN
8
EN
2
GND
5
OUT
6
ADJ
7
PGOOD
V4
MIC47053
1
2
R34
15k
1
2
R35
10k
1
2
R36
10k
1
BIAS
3
VIN
6
EN
2
GND
4
OUT
5
PGOOD
V10
MIC47050
CX29
1 uF
CX27
1 uF
CX28
1 uF
CX98
1 uF
CX105
1 uF
CX112
1 uF
3.3V
+5V_IN
3.3V_IN
UC_SDA
UC_SCL
UC_ALERT
1.8V
1V
3.3V
2.5V
3.3V
1.8V
3.3V
3.3V_FILT_ABC
3.3V
3.3V_FILT_DEF
3.3V
3.3V_FILT_GHI
3.3V
3.3V_FILT_JKL
3.3V_IN
3.3V_IN
3.3V_IN
3.3VCCO
ENABLE_1.8V
3.3V
1.8V
MGT_1V
3.3V
3.3V
1.8V
MGT_1.2V
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
55
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
1
2
R4-A
10
5
6
R4-C
10
3
4
R4-B
10
11
12
R4-F
10
9
10
R4-E
10
7
8
R4-D
10
13
14
R4-G
10
15
16
R4-H
10
1
2
R5-A
10
3
4
R5-B
10
5
6
R5-C
10
7
8
R5-D
10
9
10
R5-E
10
11
12
R5-F
10
13
14
R5-G
10
15
16
R5-H
10
1
2
R6-A
10
3
4
R6-B
10
5
6
R6-C
10
7
8
R6-D
10
9
10
R6-E
10
11
12
R6-F
10
13
14
R6-G
10
15
16
R6-H
10
5
6
R7-C
10
3
4
R7-B
10
1
2
R7-A
10
7
8
R7-D
10
13
14
R7-G
10
11
12
R7-F
10
9
10
R7-E
10
15
16
R7-H
10
5
6
R8-C
10
3
4
R8-B
10
1
2
R8-A
10
7
8
R8-D
10
13
14
R8-G
10
11
12
R8-F
10
9
10
R8-E
10
15
16
R8-H
10
5
6
R9-C
10
3
4
R9-B
10
1
2
R9-A
10
7
8
R9-D
10
13
14
R9-G
10
11
12
R9-F
10
9
10
R9-E
10
15
16
R9-H
10
CPCI_ENUM
PCI_ENUM
CPCI_AD0
PCI_AD0
CPCI_AD1
CPCI_AD2
CPCI_AD3
CPCI_AD4
CPCI_AD7
CPCI_AD6
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD7
PCI_AD6
CPCI_AD5
PCI_AD5
CPCI_AD9
CPCI_AD8
CPCI_C/BE0
CPCI_AD12
CPCI_AD11
CPCI_AD10
CPCI_AD15
PCI_AD9
PCI_AD8
PCI_C/BE0
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD15
CPCI_AD14
CPCI_AD13
CPCI_SERR
CPCI_PAR
CPCI_C/BE1
CPCI_PERR
CPCI_DEVSEL
CPCI_STOP
PCI_AD14
PCI_AD13
PCI_SERR
PCI_PAR
PCI_C/BE1
PCI_PERR
PCI_DEVSEL
PCI_STOP
CPCI_TRDY
CPCI_IRDY
CPCI_FRAME
CPCI_C/BE2
CPCI_AD16
CPCI_AD17
CPCI_AD18
CPCI_AD21
PCI_TRDY
PCI_IRDY
PCI_FRAME
PCI_C/BE2
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD21
CPCI_AD20
CPCI_C/BE3
CPCI_AD19
CPCI_AD22
CPCI_AD23
CPCI_IDSEL
CPCI_AD26
CPCI_AD25
PCI_AD20
PCI_C/BE3
PCI_AD19
PCI_AD22
PCI_AD23
PCI_IDSEL
PCI_AD26
PCI_AD25
CPCI_AD24
CPCI_AD30
CPCI_AD29
CPCI_AD28
CPCI_AD27
PCI_AD24
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
CPCI_AD31
PCI_AD31
CPCI_RST
PCI_RST
CPCI_INTA
PCI_INTA
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
56
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
Address = 1001_100 (0x4C)
1
P6.3/CB3/A3
2
P6.4/CB4/A4
3
P6.5/CB5/A5
4
P5.0/VREF+/VEREF+/A8
5
P5.1/VREF-/VEREF-/A9
6
AVCC1
7
P5.4/XIN
8
P5.5/XOUT
9
AVSS1
10
DVCC1
11
DVSS1
12
VCORE
36
P4.7/PM_NONE
35
P4.6/PM_NONE
34
P4.5/PM_UCA1RXD/PM_UCA1SOMI
33
P4.4/PM_UCA1TXD/PM_UCA1SIMO
32
DVCC2
31
DVSS2
30
P4.3/PM_UCB1CLK/PM_UCA1STE
29
P4.2//PM_UCB1SOMI/PM_UCB1SCL
28
P4.1/PM_UCB1SIMO/PM_UCB1SDA
27
P4.0/PM_UCB1STE/PM_UCA1CLK
26
P3.4/UCA0RXD/UCA0SOMI
25
P3.3/UCA0TXD/UCA0SIMO
37
P5.7
/TB0.1
38
DVSS3
39
P5.2
/XT2IN
40
P5.3
/XT2O
UT
41
TEST/S
BW
TCK
42
PJ.
0/T
DO
43
PJ.
1/T
DI/
TCLK
44
PJ.
2/T
MS
45
PJ.
3/T
CK
46
RST/N
MI/
SBW
TD
IO
47
P6.1
/CB1/A
1
48
P6.2
/CB2/A
2
24
P3.2
/UCB0CLK/U
CA0STE
23
P3.1
/UCB0SO
MI/
UCB0SCL
22
P3.0
/UCB0SIM
O/U
CB0SD
A
21
P2.7
/UCB0STE/U
CA0CLK
20
P1.7
/TA1.0
19
P1.6
/TA1CLK/C
BO
UT
18
P1.5
/TA0.4
17
P1.4
/TA0.3
16
P1.3
/TA0.2
15
P1.2
/TA0.1
14
P1.1
/TA0.0
13
P1.0
/TA0CLK/A
CLK
U4
MSP430F534X
50
VREGIN
49
VREGOUT
7
DM
8
DP
6
REF
14
RESET#
63
EECS
62
EECLK
61
EEDATA
2
OSCI
3
OSCO
13
TEST
16
ADBUS0
17
ADBUS1
18
ADBUS2
19
ADBUS3
21
ADBUS4
22
ADBUS5
23
ADBUS6
24
ADBUS7
26
ACBUS0
27
ACBUS1
28
ACBUS2
29
ACBUS3
30
ACBUS4
32
ACBUS5
33
ACBUS6
34
ACBUS7
38
BDBUS0
39
BDBUS1
40
BDBUS2
41
BDBUS3
43
BDBUS4
44
BDBUS5
45
BDBUS6
46
BDBUS7
48
BCBUS0
52
BCBUS1
53
BCBUS2
54
BCBUS3
55
BCBUS4
57
BCBUS5
58
BCBUS6
59
BCBUS7
60
PWREN#
36
SUSPEND#
56
VCCIO
42
VCCIO
31
VCCIO
20
VCCIO
64
VCO
RE
37
VCO
RE
12
VCO
RE
9
VPLL
4
VPH
Y
51
GN
D
47
GN
D
35
GN
D
25
GN
D
15
GN
D
11
GN
D
5
GN
D
1
GN
D
10
AG
ND
U5
FT2232H
1
DO
2
VSS
3
DI
6
VCC
5
CS
4
CLK
U6
93CX6
3
1
Y2
12MHz
C25
12p
C26
12p
1
2
R39
2.2k
1
2
R40
10k
1
2
R41
10k
1
2
R42
10k
1
VCC
2
D-
3
D+
5
GND
J11-A
MICRO_USB_B
1
2
L1
FERRITE
???
1
2
L2
FERRITE
???
C27
0.1 uF
C28
0.1 uF
C29
10 uF
C30
0.1 uF
C31
0.1 uF
C32
0.1 uF
1
2
R43
12k
1
2
R46
4.7
k
1
2
R47
4.7
k
1
2
R48
10K
1
2
R49
2k
1
2
R50
2k
1
2
R51
2k
1
VCCA
2
A1
3
A2
4
A3
5
A4
8
OE
14
VCCB
13
B1
12
B2
11
B3
10
B4
7
GND
U9
MAX3378
1
2
R52
50k
1
2
R53
50k
1
2
R54
50k
1
2
R55
50k
1
2
R56
50k
1
2
R57
50k
1
2
R58
50k
1
2
R59
50k
JTAG
SER
GRO
UN
D
1
NC
3
INIT
5
DONE
7
DIN
9
CCLK
2
VREF
4
TMS
6
TCK
8
TDO
10
TDI
11
PROG
12
NC
13
VREF
14
NC
J30
JTAG_2MM
CX148
0.1 uF
CX147
0.1 uF
E
B
C
Q3
BC846B
E
B
C
Q4
BC846B
1
2
R60
10k
1
2
R61
10k
1
2
R62
50k
1
2
X15
SM_LED
Green
1
2
X16
SM_LED
Red
1
2
R63
1k
1
2
R64
1k
7
SDA
6
SCL
1
IO0
2
IO1
3
IO2
5
IO3
U10
PCA9536
1
2
X17
SM_LED
1
2
X18
SM_LED
1
2
R66
1k
1
2
R67
1k
1
2
R68
10k
J32-1
J32-2
J32-3
J32-4
J32-5
1
VDD
2
DP
3
DN
4
THERM/ADDR
8
SMCLK
7
SMDATA
6
ALERT
5
GND
U11
EMC1412
1
2
R69
10k
T1-1
T1-2
CX149
0.1 uF
CX150
4.7 uF
CX151
1 uF
1
2
R77
10k
CX154
0.47 uF
3.3V_IN
IPM
I_SD
A
IPM
I_SCL
UC_TX
UC_RX
3.3V_IN
UC_SCL
UC_SDA
UC_ALERT
UC_RTS
UC_D
TR
TCK_3V3
TDI_3V3
TDO_3V3
TMS_3V3
3.3V
3.3V
3.3V
1.8V_USB
1.8V_USB
3.3V
3.3V
UC_RX
UC_TX
UC_RTS
UC_DTR
USB_D-
USB_D+
3.3V_IN
TCK_2V5
TDI_2V5
TDO_2V5
TMS_2V5
2.5V
3.3V
TCK_3V3
TDI_3V3
TDO_3V3
TMS_3V3
JTAG_DISABLE
2.5V
3.3V
TD
O_3V3
TD
I_3V3
TM
S_3V3
TCK_3V3
3.3V
TMS_3V3
TCK_3V3
TDI_3V3
TDO_3V3
2.5V
UC_PRO
GRAM
_B
UC_IN
IT_B
FPGA_PROGRAM_B
FPGA_INIT_B
3.3V_IN
FPG
A_D
ON
E
3.3V_IN
3.3V_IN
3.3V_IN
T_SDA
T_SCL
FPGA_DONE
JTAG_DISABLE
2.5V
2.5V
2.5V
UC_DTR
UC_RTS
UC_TX
UC_RX
UC_SCL
UC_SDA
UC_ALERT
3.3V_IN
3.3V_IN
3.3V_IN
2.5V
ENABLE_1.8V
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
57
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
VCCINT
VCCBRAM
VCCAUX
VCCO_0
VCCO_12
VCCO_13
VCCO_14
VCCO_15
VCCO_16
VCCO_33
VCCO_34
VCCO_35
MGTAVCC/MGTAVTT
+
CX38
680 uF
CX39
4.7 uF
CX40
4.7 uF
CX41
4.7 uF
CX42
4.7 uF
CX43
4.7 uF
CX44
4.7 uF
CX45
4.7 uF
CX46
4.7 uF
CX47
4.7 uF
CX48
4.7 uF
CX49
4.7 uF
CX50
4.7 uF
CX51
0.47 uF
CX52
0.47 uF
CX53
0.47 uF
CX54
0.47 uF
CX55
0.47 uF
CX56
0.47 uF
CX57
0.47 uF
CX58
0.47 uF
CX59
0.47 uF
CX60
0.47 uF
CX61
0.47 uF
CX62
0.47 uF
CX63
0.47 uF
CX64
0.47 uF
CX65
100 uF
CX66
0.47 uF
CX67
0.47 uF
CX68
0.47 uF
CX69
47 uF
CX70
4.7 uF
CX71
4.7 uF
CX72
4.7 uF
CX73
4.7 uF
CX74
4.7 uF
CX75
0.47 uF
CX76
0.47 uF
CX77
0.47 uF
CX78
0.47 uF
CX79
0.47 uF
CX80
0.47 uF
CX81
0.47 uF
CX82
0.47 uF
CX83
0.47 uF
CX84
4.7 uF
CX85
100 uF
CX86
4.7 uF
CX87
4.7 uF
CX88
0.47 uF
CX89
0.47 uF
CX90
0.47 uF
CX91
0.47 uF
CX92
4.7 uF
CX93
0.47 uF
CX94
0.47 uF
CX95
4.7 uF
CX96
0.47 uF
CX97
0.47 uF
CX99
4.7 uF
CX100
4.7 uF
CX101
0.47 uF
CX102
0.47 uF
CX103
0.47 uF
CX104
0.47 uF
CX106
4.7 uF
CX107
4.7 uF
CX108
0.47 uF
CX109
0.47 uF
CX110
0.47 uF
CX111
0.47 uF
CX113
4.7 uF
CX114
4.7 uF
CX115
0.47 uF
CX116
0.47 uF
CX117
0.47 uF
CX118
0.47 uF
CX120
4.7 uF
CX121
4.7 uF
CX122
0.47 uF
CX123
0.47 uF
CX124
0.47 uF
CX125
0.47 uF
CX126
47 uF
CX127
4.7 uF
CX128
4.7 uF
CX129
0.47 uF
CX130
0.47 uF
CX131
0.47 uF
CX132
0.47 uF
CX134
4.7 uF
CX135
4.7 uF
CX136
0.47 uF
CX137
0.47 uF
CX138
0.47 uF
CX139
0.47 uF
CX141
4.7 uF
CX142
4.7 uF
CX143
0.47 uF
CX144
0.47 uF
CX145
0.47 uF
CX146
0.47 uF
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
MGT_1V
MGT_1V
MGT_1V
MGT_1.2V
MGT_1.2V
MGT_1.2V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
3.3VCCO
3.3VCCO
3.3VCCO
3.3VCCO
3.3VCCO
3.3VCCO
3.3VCCO
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
<Drawn By>
<Checked By>
<QC By>
<Released By>
<Drawn Date>
<Checked Date>
<QC Date>
<Release Date>
<Company Name>
<Title>
<Code>
C
<Drawing Number>
<Revision>
<Scale>
58
58
REV:
SIZE:
CODE:
DRAWN:
DATED:
DATED:
CHECKED:
QUALITY CONTROL:
DATED:
DATED:
RELEASED:
COMPANY:
TITLE:
DRAWING NO:
SHEET: OF
SCALE:
REVISION RECORD
APPROVED:
ECO NO:
LTR
DATE:
1
2
3
4
5
6
D
C
B
A
C
D
B
A
3
1
2
4
X19
LTST-C155GEKT
Red
Green
3
1
2
4
X20
LTST-C155GEKT
Red
Green
3
1
2
4
X21
LTST-C155GEKT
Red
Green
3
1
2
4
X22
LTST-C155GEKT
Red
Green
3
1
2
4
X23
LTST-C155GEKT
Red
Green
3
1
2
4
X24
LTST-C155GEKT
Red
Green
LED0
LED3
LED3
LED1
LED1
LED0
LED3
LED0
LED3
LED3
LED1
LED2
LED2
LED3
LED2
LED3
LED0
LED2
LED0
LED2
LED1
LED2
LED2
LED1
LED0
LED1
LED1
LED0
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