APU CARC 04 Registers and Memory
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Prepared by: KNT First Prepared on: 31-1-14 Last Modified on: xx-xx-xxQuality checked by: xxx
Copyright 2014 Asia Pacific University
Degree : Level-3
Computer ArchitectureCT063-3.5-2
Registers & Memory
Register & Memory Title of Slides
Topic & Structure of the lesson
• What is a Register?• Types of Registers• Operations of Registers• Memory
Register & Memory Title of Slides
Learning Outcomes
• At the end of the session you will be able to:-– describe a register– explain its operations– compare user visible registers (UVR) & user invisible
registers (UIR)– apply the idea of Status Flags for dynamic evaluation
of the ALU status.– calculate the current value of the PSW Register.– describe the type of memory
Register & Memory Title of Slides
Key Terms you must be able to use
• If you have mastered this topic, you should be able to use the following terms correctly in your assignments and exams:-– register– Accumulator, Base register, Counter register, Data
register– Program counter (PC)– Instruction register (IR)– Memory address register (MAR)– Memory data register (MDR)– PSW– flag registers
Register & Memory Title of Slides
CPU Architecture
• The function of the CPU is to:
– fetch instructions (from memory)
– interpret instructions (decode them to determine action)
– fetch data (instruction execution may need operands from memory)
– process data (perform arithmetic operation)
– write data (results are stored back in memory)
Register & Memory Title of Slides
CPU Architecture
• The CPU has three important parts:-– Control Unit - to fetch & decode instructions– ALU to perform arithmetic(*/+-) and logical operations
(and,or,not)– Registers to store temporary data
High Speed Registers
ALU Control Unit
CPUAnother critical aspect of CPU architecture is
number and design of registers
Register & Memory Title of Slides
What is a Register?
• Small, permanent storage locations within the CPU used for a particular purpose.
• Manipulated directly by the Control Unit.• Wired for specific function.• Size in bits or bytes (not MB like memory).• Can hold data, an address or an
instruction.
Register & Memory Title of Slides
Why Registers?
• CPU must have some working space (temporary storage)
• CPU can't directly perform arithmetic in memory • E.g. if you want to add 1 to a memory location, the processor will
normally do this by loading the initial value from memory into a register, adding 1 to the register, and then saving the value back to memory.
• This of course happens very quickly and transparently to the programmer
• Scratchpad for currently executing program.– used to hold data that must be accessed by the CPU very
quickly
Register & Memory Title of Slides
Why Registers?
• Stores information about status of CPU and currently executing program.– Hold data being processed.– Hold an instruction to be executed.– Hold a memory address.– Hold status codes.
Register & Memory Title of Slides
Register Operations
• Registers are also used for:1. Storing values from other locations.
– The register can be loaded with values from other registers or from memory locations.
– This operation overwrites previous value stored in the register
2. Addition and subtraction.– Data from either other register or memory location can be
added to or subtracted from the value stored in the register, leaving a sum or a difference in the register
3. Shifting or rotating data.– Data in the register can be shifted or rotated right or left by
one or more bits. – The shift operation is used to implement multiply and divide
arithmetic operations
Register & Memory Title of Slides
Arithmetic Shift
Register & Memory Title of Slides
Register Operations
• Registers are also used for:-4. Testing contents for conditions such as
zero or positive.
Register & Memory Title of Slides
Register Organisation
• A processor includes both– User Visible Registers
(UVR) • visible to programmer• may be general purpose
or have a special use– User Invisible Registers
(UIR) • used solely by the CPU
and special O/S functions
• are used to control the operation of the CPU.
Register & Memory Title of Slides
Register Organisation
• General purpose registers: – can be used for any operation; hold address
as well as data. – Hold intermediate results or data values, for
example, loop counters.– Early computers had only one, the
accumulator. – Typically several dozen in current CPUs– Numbers limited by cost versus ability to
make use of greater numbers.
Register & Memory Title of Slides
User Visible Registers
• While General Purpose Registers can be used by most instructions, they may be optimised for specific operations, such as the accumulator.
• If registers are specialised then their use will be implicit and need not be mentioned in the instruction. This means the instruction will be shorter and less memory required.
• Example:-– Data Registers : some instructions expect to use certain
registers to hold data such as; MUL CX whereas the other operand is assumed to be in AX and result will be placed in AX.
– Address Registers : Stack Pointer, Segment Pointer, and Index Pointer.
Register & Memory Title of Slides
x86 General Purpose Registers
Accumulator AXBase BXCounter CXData DXBase Pointer BPStack Pointer SPSource Index SIDestination Index DI
16bits
Register & Memory Title of Slides
User Invisible Registers (UIR)
• Every processor contains some special purpose or control registers. These are generally contained within the control unit. Several important ones are:– Program Count Register (PC)– Instruction Register (IR)– Memory Address Register (MAR)– Memory Data Register (MDR) – Status/Flag Registers
Register & Memory Title of Slides
Program Counter (PC)
• Program Counter (PC)– Also called instruction pointer (IP).– Contains the address of the next instruction to
be fetched from memory; it is automatically updated by the CPU during Fetch/Execute cycle.
– May be forced to change: for example a “jump” instruction.
– Usually initialise to zero when machine starts, or is reset.
Register & Memory Title of Slides
Instruction Register (IR)
• Instruction Register (IR)– copy of the current instruction being
executed.– stores instruction fetched from memory.
Register & Memory Title of Slides
A dedicated register in the CPU which contains the actual current instruction.
Op Code + Address
What To Do Location of Data
Simple 16-bit example: 1101 101101100100
Instruction Register (IR)
Register & Memory Title of Slides
MAR and MDR
• Memory Address Register (MAR) – holds address of memory location and connected to address bus– Contains Address in memory to find or place data.
• Memory Data Register (MDR)– also referred to as the Memory Buffer Register (MBR).– holds data being transferred to/from memory - connected to data
bus– Contains Actual Data to be placed in location given in MAR, or
which has been retrieved from location given in MAR.
• The MAR & MDR are used for data exchange between memory and the CPU.
Register & Memory Title of Slides
Status / Flags Registers
• Status/Flags Registers– sometimes called Program Status Word (PSW)
Registers.– contain individual bit fields indicating status
information from program execution, often error conditions.
– shows status of CPU and currently executing program.
– Flags (one bit Boolean variable) to track condition like arithmetic carry and overflow, power failure, internal computer error.
Register & Memory Title of Slides
Program Status Word (PSW)
• Types of Status Flags (1- bit Cells)– Sign Flag
• This Flag is set (assigned a value of 1) if the result of the arithmetic operation is negative. Otherwise it is reset (assigned a value of 0).
– Zero Flag• This Flag is set (assigned a value of 1) if the
result of the arithmetic operation is zero. Otherwise it is reset (assigned a value of 0).
Register & Memory Title of Slides
Program Status Word (PSW)
• Types of Status Flags (1- bit Cells)– Half-Carry (HC) Flag
• This Flag is set (assigned a value of 1) if there is a carry from the HSB (Half Significant Bit position). Otherwise it is reset (assigned a value of 0).
– Carry (C) Flag• This Flag is set (assigned a value of 1) if there is a
carry from the MSB (Most Significant Bit position). Otherwise it is reset (assigned a value of 0).
Register & Memory Title of Slides
Program Status Word (PSW)
• Types of Status Flags (1- bit Cells)– Overflow (V) Flag
• This Flag is set (assigned a value of 1) if there is a carry from the MSB (Most Significant Bit position or the MSB -1) Bit positions but not both. Otherwise it is reset (assigned a value of 0).
– Parity (P) Flag• For Even Parity, this Flag is set (assigned a value
of 1) if the number of 1s in the result inclusive of parity is even. Otherwise it is reset (assigned a value of 0).
Register & Memory Title of Slides
Program Status Word (PSW)
• Example– A 16bit PSW– Each position is a binary value representing
a true/false condition.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15S 0 0 P 0 1 Z HC 1 1 0 C 1 0 V 1
PSW
Register & Memory Title of Slides
Example:Given that the current ALU operation on two 8-bit operands, 12 and 16 is Addition, encode the value of the following 16-bit Program Status Word (PSW), using hexadecimal notation.
Solution:a) Represent the operands using 8-bit signed 2’s complement
representation.b) Perform the operation (Addition) and compute the result.c) Find out the values of the binary Flags: S, Z, HC, C, P, Vd) Fill in the entries in the PSW Register.e) Encode the Register contents using hexadecimal notation.
Condition Codes Register
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15S 0 0 P 0 1 Z HC 1 1 0 C 1 0 V 1
PSW
Register & Memory Title of Slides
Condition Codes Register
Decimal Binary12 0000110016 00010000
Decimal 2s Complements12 1111010016 11110000
11110100+ 11110000
111100100
00011011+ 1
00011100
Register & Memory Title of Slides
Memory Organisation
• Computer systems employ a memory hierarchy.
• At higher levels, memory is faster, smaller & more expensive.
• Within the CPU, there is a set of registers that function at a level above main memory & cache in the hierarchy.
Slide 29 of 26
Register & Memory Title of Slides
Memory Organisation - Hierarchy
Slide 30 of 26
Register & Memory Title of Slides
Registers vs Main Memory
• Registers that is faster and smaller than main memory.
• Temporarily stores data during processing.• Each register is wired to perform its specific
role. – Unlike memory, where every address is just like other
addresses, each register serves a particular purpose.• Registers are not addressed directly as a
memory location but are manipulated directly by the control unit.
Slide 31 of 26
Register & Memory Title of Slides
Cache Memory
• Generally speaking – The CPU asks for data/instructions from
memory faster than it receives from them.– This type of waiting is bad for performance
• Much of the time data and instructions are used over and over. (e.g. loop)
• Sometimes you can ‘predict’ what instructions are next
Slide 32 of 26
Register & Memory Title of Slides
Cache Memory
• We can use these tendencies to advantage by keeping likely to be referenced (soon) data in a faster memory than main memory.
• This faster memory is called a CACHE. – It is located very close to the processor. – It contains COPIES of PARTS of memory.
• Question: Where does the data from cache go to?
Slide 33 of 26
CPU Cache Main Memory
Register & Memory Title of Slides
Desktop, Drawer, and File Cabinet Analogy
Slide 34 of 26
Items on a desktop (register) or in a drawer (cache) are more readily accessible than those in a file cabinet (main memory).
Main memory
Register file
Access cabinet in 30 s
Access desktop in 2 s
Access drawer in 5 s
Cache memory
Once the “working set” is in the drawer, very few trips to the file cabinet are needed.
Register & Memory Title of Slides
Memory Organisation
Slide 35 of 26
Register & Memory Title of Slides
The Operation of Memory
• Main memory consist of cells, each of which can hold a single value and each of which has a single address.
• The MAR & MDR acts as an interface between the CPU & memory.– MDR is also called memory buffer register.
• The MAR holds the address to be “opened”.• The MAR is connected to a decoder that
interprets the address and activates a single address line into the memory.
Slide 36 of 26
Register & Memory Title of Slides
The Operation of Memory
• The output from the MAR is passed to the address decoder.
• The row of memory cells corresponding to the decoded address will be activated.
• The MDR will read this group of cells.
Slide 37 of 26
Register & Memory Title of Slides
Memory Capacity
• Memory Capacity is the maximum number of addressable memory locations.
• Let the size of the address be ‘k’ bits and the number of addressable memory locations be ‘M’ locations.
• Then => M = 2k locations• If each location can accommodate B bytes,
then memory capacity in bytes is (2k * B).
Register & Memory Title of Slides
Memory Capacity
• 2n x m• n - address bits = 2n addresses• m - data bits• m - the “width” of the data path• Typical values:-
– n: 16, 17, 18, 19, 20, 21, 22, etc.– m: 8, 16, 32, 64
Register & Memory Title of Slides
Types of Memory
• Magnetic Core Memory• Static RAM• Dynamic RAM• ROM
P-ROME-PROMEE-PROM
Register & Memory Title of Slides
Types of Memory
• Magnetic Core Memory• Static RAM• Dynamic RAM• ROM
P-ROME-PROMEE-PROM
Register & Memory Title of Slides
Types of Memory
• Magnetic Core Memory• Static RAM• Dynamic RAM• ROM
P-ROME-PROMEE-PROM
Register & Memory Title of Slides
Slide 43 of 26
More RAM = Better Performance!
Memory Slots
Register & Memory Title of Slides
SRAM v DRAM Summary
SRAM DRAM• Faster
• More complex
• No refresh
• More expensive
• Cache
• Smaller
• Slower
• Simpler to build
• Needs refresh
• Less expensive
• Main memory
• Larger
Register & Memory Title of Slides
Types of Memory
• Magnetic Core Memory• Static RAM• Dynamic RAM• ROM
P-ROME-PROMEE-PROM
Register & Memory Title of Slides
Types Of Memory
Slide 46 of 26
Register & Memory Title of Slides
Quick Review Questions
1. What is a register? Describe briefly the operations of registers.
2. Why are there two different registers(MAR and MDR) associated with memory?
Register & Memory Title of Slides
Quick Review Questions
1. What are the differences between registers, cache and main memory?
2. In what order does the Processor search for data or instructions?
3. What are the two (2) major types of RAM? 4. What are differences between the two types of
RAM?5. For what parts are the 2 types of RAM used?
Register & Memory Title of Slides
Quick Review Questions
1. How many bits of memory are contained in a memory unit with 512KB of memory locations?
2. How many bits of memory are contained in a memory unit with 2MB of memory locations?
3. One large modern computer has a 36 bit memory address register. How much memory can this computer address?
Register & Memory Title of Slides
Answers
• Q1– 512 = 29, K = 210, B = byte = 8bits = 23
– 29 x 210 x 23 = 222 = 4,194,304 bits• Q2
– 2 = 21, M = 220, B = byte = 8bits = 23
– 21 x 220 x 23 = 224 = 16,777,216 bits• Q3
– MAR = 36bits– Total addressable locations = 236 = 68719476736 =
64GB
Register & Memory Title of Slides
Quick Review Questions
Critically assess the four categories of computer data storage in terms of application, performance, speed and cost with an appropriate block diagram.
Register & Memory Title of Slides
Answers
Memory organization in a computer
Register & Memory Title of Slides
Quick Review Questions
Explain the registers below:AX BX CX
DX
Register & Memory Title of Slides
Summary of Main Teaching Points
• Registers– Within the CPU, the most important
components are registers. – Two types of registers are Visible and Invisible
registers.
Register & Memory Title of Slides
Summary of Main Teaching Points
• Memory Organisation The operation of memory is intimately related to two registers in particular, the memory address register and memory data register
Register & Memory Title of Slides
Q & A
Question and Answer Session
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