Transcript
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Introduction to Analog Design
Dr. S. L. Pinjare
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What is Analog VLSI Design?
• Implementation of analog circuits and systems using integrated circuit technology.
• Unique Features of Analog IC Design– Geometry
• an important part of the design
– Usually implemented as a mixed analog-digital circuit
• Typically Analog is 20% and digital 80% of the chip area
– Designed at the circuit level
– Customized design– Analog requires 80% of the design time
– Passes for success: 2-3 for analog, 1 for digital.
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Analog Design Flow
• Electrical Design• Physical Design• Fabrication and Testing • Product
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Analog Design FlowElectrical Design
Physical Design
Idea Concept
Define the Design
Implementation
Simulation
RedesignComparison with the Design Specification
Fabrication
Testing and Product Development
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Analog Design FlowElectrical Design
Physical Design
Idea Concept
Define the Design
Implementation
Simulation
RedesignComparison with the Design Specification
Physical Implementation-Layout
Physical Verification-DRC,ERC,LVS,Antenna
Parasitic Extraction and Back Annotation
Fabrication
Testing and Product Development
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Analog Design FlowElectrical Design
Physical Design
Idea Concept
Define the Design
Implementation
Simulation
RedesignComparison with the Design Specification
Fabrication Fabrication
Testing and Product Development
Physical Implementation-Layout
Physical Verification-DRC,ERC,LVS,Antenna
Parasitic Extraction and Back Annotation
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Analog Design FlowElectrical Design
Physical Design
Idea Concept
Define the Design
Implementation
Simulation
RedesignComparison with the Design Specification
Fabrication Fabrication
TestingTesting and Product Development PRODUCT
Physical Implementation-Layout
Physical Verification-DRC,ERC,LVS,Antenna
Parasitic Extraction and Back Annotation
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Skills Required for Analog IC Design
• In general, analog circuits are more complex than digital.– Requires an ability to use multiple concepts simultaneously.
– Must be able to make appropriate simplifications and assumptions.
– Must have good knowledge of both modeling and technology.
– Be able to learn from failure.
– Be able to use simulation correctly.• (Usage of a simulator)x(Common sense)=Constant
• Simulators are only as good as the models and the knowledge of those models.
– “all models are wrong, some are useful"
– Simulators are only good if you already know the answers.
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Implications of Technology Advancement on IC Design
• The good:– Smaller geometries– Smaller parasitics– Higher transconductance– Higher bandwidths
• The bad:– Reduced voltages– Smaller channel resistances (lower gain)– More nonlinearity– Deviation from square-law behavior
• The ugly:– Increased substrate noise in mixed signal applications– Threshold voltages are not scaling with power supply– Reduced dynamic range– Suitable models for analog design
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Analog Design components
• Active devices– Transistors
• Nmos and pmos
• Passives – Resistors
– Capacitors
– Inductors
• Using existing layers and masks and possibly adding a few extra layers
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Layout consideration
• Design rules– Allowance Errors in patterning and etching
• Minimum width
• Minimum spacing
• Minimum enclosure
• Minimum extension
• Process variability– Parameter variation across the chip
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Design rules
• Minimum width – The minimum width of polygon defines the limits of a fabrication process.
– A violation of the minimum width rules potentially results in an open circuit in the offending layer.
– An open circuit may be created during fabrication.
– A narrow path may be created during fabrication - large currents passing through a narrow path cause the path to act like a fuse.
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Design rules
• Minimum spacing:– To avoid an unwanted short circuit between two polygons
during fabrication,
• S1 > Smin, where Smin is set by process.
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Design rules
• Minimum enclosure:– Apply to polygons on different layers.
– Misalignment between polygons may result in either unwanted open or short circuit connections.
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Design rules
• Minimum extension:– Some geometries must extend beyond the edge of others by a
minimum value.
• Eg. Gate poly must have a minimum extension beyond the active area to ensure proper transistor action at the edge.
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Design Rules• Example of the design rules applying to the POLY layerC3.4 POLY: Gate Structures and resistors are defined by the poly layer. Minimum design rules are used for the polylayer. i.e. this is the minimum feature size for this process.• A ≥ 1.5 µm,(minimum polywidth /Length). • B ≥ 1.5 µm,(minimum poly to poly distance).• C ≥ 1.5 µm,(minimum poly-over-oxide overlap).
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Layout - Matching
• In analog electronics it is often necessary to have matched pairs of devices with identical electrical properties, e.g. input transistors of a differential stage, and current mirror– In theory two device with the same size have the same
electrical properties.
• In reality there is always process variations
• Matching:– Layout techniques to minimize the errors introduced by these
process variations.
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Unit Matching
• Two electrically equivalent components.• Draw them identically
– both item and surrounding
– A and B have same shape in area and perimeter
– identical item?
– Do they have the same surrounding?
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Unit Matching
• Two electrically equivalent components.• Draw them identically
– both item and surrounding
– A and B have same shape in area and perimeter
– identical item?
– Do they have the same surrounding?-No
– Use Dummies to have identical surroundings
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Common-centroid layout
• Process variations can locally be approximated with a linear gradient.(a): A1 + A2 < B1 + B2
(b): A1 + A2 = B1 + B2 (common-centroid)
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Resistors
• All materials have a resistivity• Typical resistivities
– Metal layer : 0.1 Ohm/square
– n/p-plus contacts and polysilicon: 10-100 Ohm/square
– n-well: 1000 Ohm/square
– low doped poly silicon: 10 k Ohm/square
• more well defined than n-well, i.e. higher accuracy
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Poly-Resistors
• Poly Resistors– Silicidated poly resistors: 1 − 10 Ohm/sq.
• ≈±30%
– Non-silicidated poly resistors: 50-1000 Ohms per unit area .
• Small parasitic capacitances to substrate.
• Superior linearity.
• High cost due to the extra mask needed to block silicide layer.
• ≈±20%
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Diffusion Resistors
• 1k Ohm/sq– N-well
• Large parasitic capacitance between n-well and substrate.
• Resistance is strongly terminal voltage-dependent and highly nonlinear.
– Depletion width varies with terminal voltages.The cross-section area varies with terminal voltages
• Large error : ≈±40%
• noisy as all disturbances/noise from substrate can be coupled directly onto the resistors
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Resistor Layout• Standard Resistors: Avoid 90 degree angle. 45 degree is recommended
Recommended resistor layout
1. Resistance at the corners cannot be estimated accurately
2. Current flow at the corner is not uniform
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Resistor Layout
• Dummy resistors are added to minimizes the effect of process variation
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Shielded Resistors
• Shielding resistors are connected to a constant voltage source to prevent self-coupling of the resistor R/inter-coupling with others.
• Widely used in analog/RF design.
• Caution - a mutual capacitance between the resistor and its shield exist.
Layout of shielded resistors
(S = shielding resistors)
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Layout of Large Resistors
• Use n-well resistors – have a large sheet resistance.
• Enclosed by a substrate shielding ring, also known as guard ring, to isolate the resistors from neighboring devices.
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Layout of Matched Resistors
• Inter-Digitized Layout – minimizes the effect of process variation in x-direction.
• Dummy resistors are added to ensure both resistors have the exactly same environment.
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Matched Resistors with Temperature Consideration
• Keep away from power devices
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Resistor layout guidelines-Matched resistors
• Use same material• Identical geometry, same orientation• Close proximity, interdigitate arrayed resistors• Use dummy elements• Place resistors in Low stress area• Place resistors away from power devices• Use electrostatic shielding• Use proper endings
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Capacitors
• Between each layer of metal, poly silicon or silicon there are naturally capacitors.
• Dielectrics between different metal layers have a thickness of 0.5-1 micron, which gives a rather large area for a given capacitance.
• Key Parameters– Linearity
– Parasitic capacitance to substrate
– Series resistance - resistance of capacitor plates
– Capacitance per unit area
• Larger specific capacitance (capacitance per unit area) gives smaller area
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Types of IC Capacitors• Poly-diffusion capacitors
– Nonlinear bottom-plate parasitic capacitance.≈20% of inter-plate capacitance.– .6-.8 fF/µm2(≈±5%). Matching 0.2%
• MOS capacitors – stable capacitance in strong inversion – Non-negligible channel resistance lowers the quality factor (Q) of the capacitor– 0.6 - 0.8 fF/µm2; (≈±5%). Matching 0.5%
• Poly-poly capacitors– Not available in standard CMOS processes– 0.3 - 0.5 fF/µm2; (≈±10%). Matching 0.5%
• Metal-poly capacitors – Capacitance is small, area consuming. – 0.03-0.05 fF/µm2. (≈±25%). Matching 0.5%
• Metal-metal capacitors – Capacitance is small, area consuming – 0.02-0.04 fF/µm2; (≈±25%). Matching 0.1%
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NON-IDEAL EFFECTS- UNDER-CUT
• Non-uniform undercut &/or edge fringing field effects change the value of designed capacitors.
• The area and perimeter ratio is preserved if we use layout using unit capacitors.
Case 1
Case 2
Ideal case: no undercut
Case 1 Case 2
Area 1:4 1:4
Perimeter 1:2 1:4
Typical case: 0.05 undercut
Case 1 Case 2
Area 1:4.46 1:4
P erimeter 1:2.1 1:4
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NON-IDEAL EFFECTS-Corner Rounding
• Etching always causes corner rounding to some extent.
• This means that– 90° corners will be eroded and
– 270° corners will be have incomplete removal of material
• In order to overcome this effect use an equal number of 90° & 270° corners
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Layout of MOS Capacitors
• Single finger structure – Large source/substrate & drain/substrate capacitances
– Large gate series resistance
Minimize Gate Series Resistance & Channel Resistance
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Layout of MOS Capacitors
• Minimize Gate Series Resistance & Channel Resistance
• Use Multi-Finger Structure
Multi-finger structure minimizes source/substrate & drain/substrate parasitic capacitances.
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Layout of Matched Capacitors
• Minimize the Effect of Oxide Thickness in both x and y-directions.– Common Centroid Structure.
– Dummy capacitors are needed to ensure the same environment for C1 and C2.
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Layout of Matched Capacitors
• C1 and C2 are 2-poly capacitors.
• n-well is employed as a charge collector to shield the interaction between the bottom plate and substrate.
• n-well is biased at multiple points and connected to a constant voltage source.
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Layout of MOS Transistors
• Criteria for MOS Transistor Layout– Minimize gate series resistance.
– Minimize source/drain resistances.
– Minimize source/substrate & drain/substrate parasitic capacitances.
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Layout of MOS Transistors• Large gate series resistance
– 7.8±2.5Ohm/sq for typical 0.18μ CMOS processes.
• Large distributed resistance of source/drain
– 6.8±2.5Ohm/sq for n+ and 7.2±2.5Ohm/sq for p+ in typical 0.18μ CMOS processes.
• Large source/substrate and drain/substrate parasitic capacitances.
• Non-uniform gate/source/drain voltages.
• Non-uniform current flow
– M1 carries the most current and Mn carries the least current).
Most of the current will be shrunk to this side
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Layout of MOS Transistors• Minimize Source/Drain Resistances
– Multiple contacts at source/drain• Better contact at source/drain → high reliability & smaller contact resistance (R
= Rc/N, where N=number of contacts).– Smaller source/drain resistances (series resistance is negligible but lateral
resistance still exists).– Large source/substrate and drain/substrate parasitic capacitances.
– Large gate series resistance- Gate is too long.• Contacts are not allowed on the gate above the channel (high temperature
required to form contacts may destroy the thin gate oxide).
Current is spread
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Layout of MOS Transistors
Folding reduces gate resistance
No of fingers: Gate resistance < 0.1 to .5(1/gm)
Results in increase of parasitic capacitance
Poly contact at both ends
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Layout of MOS Transistors
• Minimize Source/Substrate and Drain/Substrate Parasitic Capacitances – Shared sources/drains.
– Reduced silicon area.
Another layout
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Antenna Effect
There will be charge accumulation on Metal1 during plasma etching (of metal1) causing damage to thin gate oxide (Large metal area)
Avoids antenna effect
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Layout of a Cascode circuit
a.
b. c.
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Layout of Wide transistors • Wide transistors need to be split• Parallel connection of n elements (n = 4 for this example)• Contact space is shared among transistors• Parasitic capacitances are reduced (important for high speed )
Note that parasitic capacitors are lesser at the drain
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Layout of Matched Transistors
• Matched transistors are used extensively in both analog and digital CMOS circuits.
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Photo-lithographic invariance (PLI)
• Lithography effects different in different direction• C and D are better
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Photo-lithographic invariance (PLI)
• Effect of shadowing – S/D implant often has an angle.
– Drain/Source can be mirrored
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Photo-lithographic invariance (PLI)
• Effect of shadowing :– Gate aligned
– Parallel gate:
• Two drains have different surroundings
• Two sources have different surroundings
Orientation is important in analog circuits for matching purposes
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Layout of Matched Transistors
• Add dummy transistors to improve symmetry
• Presence of Metal line over M2 destroys symmetry • Replicate Metal line over
M1 improves symmetry
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Layout of Matched Transistors
• Gradient along x-axis destroys symmetry
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Matching - Summary
• To achieve both common-centroid and PLI matched transistors has to be split into 4 fingers.
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Effect of wiring resistance
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Matched Transistors• Matched transistors require elaborated layout techniques• Use inter-digitized layout style• Averages the process variations among transistors• Common terminal is like a serpentine• Uneven total drain area between M1 and M2.
– This is undesirable for ac conditions: capacitors and other parameters may not be equal • A more robust approach is needed (Use dummies if needed
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Common Centroid Layouts
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Common Centroid Layouts
• Split into parallel connections of even parts
• Half of them will have the drain at the right side and half at the left
• Be careful how you route the common terminal
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Analog layout Issues
• Issues that are important in digital circuits are still important in analog layout. – Eg. parasitic aware layout.
• It is important to minimize series resistance in digital circuits because it slows switching speed.
– Series resistance also slows analog circuits, plus it introduces unwanted noise.
• Parasitic capacitance is avoided in digital circuits because it slows switching speed and/or increases dynamic power dissipation.
– Stray capacitance has the same effect in analog circuits
» Bias current must be increased to maintain bandwidth and/or slew rate when extra load capacitance is present .
» Extra load capacitance can lead to instability in high gain feedback systems.
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Analog layout Issues
• Matching of Devices:Matching is important because most analog circuit designs use a ratio based design technique(e.g. current mirrors). Some common techniques that help improve device matching are – MULTI-GATE FINGER LAYOUT and
– COMMON-CENTROID LAYOUT.
• Noise:Noise is important in all analog circuits because it limits dynamic range.
• In general there are two types of noise, – random noise and
– environmental noise.
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Analog layout Issues
• Random noise refers to noise generated by resistors and active devices in an integrated circuit;
• MULTI-GATE FINGER LAYOUT
– reduces the gate resistance of the poly-silicon and the neutral body region, which are both random noise sources.
• Generous use of SUBSTRATE PLUGS
– will help to reduce the resistance of the neutral body region, and thus will minimize the noise contributed by this resistance.
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Analog layout Issues• Enivironmental noise
– Crosstalk; Ground bounce etc.– Generally appears as a common-mode signal.
• Use ‘fully-differential’ circuit design, – Substrate noise occurs when a large amount digital circuits are
present on a chip. The switching of a large number of circuits discharges large dynamic currents to the substrate, which cause the substrate voltage to ‘bounce’.
• The modulation of the substrate voltage can then couple into analog circuits via the body effect or parasitic capacitances.
• SUBSTRATE PLUGGING – minimizes substrate noise because it provides a low
impedance path to ground for the noise current.
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Summary
• Use large area to reduce random error• Common Centroid layout to reduce linear gradient
errors• Use unit element arrays• Interdigitize for matching• Use of symmetry (photolithographic invariance)• Dummy device for similar vicinity• Guard rings for isolation
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• References• A. Hastings, The Art of Analog Layout, Prentice-
Hall,2002.• B. Razavi, Design of Analog CMOS Integrated Circuits,• McGraw-Hill, 2001.
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Thank You
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