Transcript
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Ali Karim Sir1
Intel 80386-
32bit
- 30Marks
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Ali Karim Sir2
Q. List the salient features of 80386. Any 8 features [1 mark each] (S-13)
1. It is a 32-bit microprocessor i.e. all the registers are 32-
bitin size.
2. It can operateon 8-bit, 16-bit or 32-bit ata.
3. It has 32-bit ata bus.
!. It has 32-bit aress bus. "hus it can access 2#32 i.e.!"#
of ph$sical memor$an 2$!%b$2#13& 6! %# of &irtual
memor$.
'. "he memor$ management of 80386 su((orts )irtual
memory, (a%in% an four le)el (rotection. "he a)ailable
(hysical memory is i)ie into pages of !'# each.
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Ali Karim Sir3
6. It su((orts 8038 math coprocessor. "he 8*38+
su((orts hi%her (recision 32-bit numerical o(erations.
+. It has 8 ebug registers (*0-*) hich (ro)ies
harare ebu%%in% an control.
8. It is esi%ne in full$ pipeline architecture/ has
three 0ueues for fetch+ ecoe , eecute.
. It has on-chi( aress translation cache.
1*. It is upar compatible all the (re)ious members of8*86 family.
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Ali Karim Sir4
11. It runs at 2*4z an 334z.
12. It su((orts three operating moes5 eal, 7rotecte
irtual 7A an irtual 8*86.
13. It is also a)ailable in 3 &ersions 5
i. 8*386 9: ; 16 bit u( 286
ii. 8*386 on chi(
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Q. ra an eplain the internal architecture of 80386.
(!/ for iag+ !/ for epln.) (-13)
Q. ra the internal architecture of 80386. lso eplain the
folloing pin of 80386 #0 to #3 4 L54'
#S7(rchitecture ith label ! / each pin functionalit$ 1/ 9 !/) (S-1!)
Ali Karim Sir6
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Architecture
6 functional units #us :nterface unit
;refetch unit
ecoe unit
/emor$ /anagement nit+ consisting of
Segmentation unit
;aging unit
ecution unit
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The figure shows the architecture of 80386.
It is divided i 3 sectios
1! ""#2! $%#
3! &I#
1) 4entral ;rocessing nit
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2) //
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3) #:
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%I( )IA*+A" ,- 80386Ali Karim Sir11
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Ali Karim Sir12
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80386
PROCESSOR
CLK 22 X CLOCK
DATA
BSD 0 ! D 3"
32 BIT
DATA
BS
CO#TROL
ADS $
#A $
BS "6 $
READ%
&OLD
&LDA
I#TR
#MI
RESET
BS
ARBITRATIO#
I#TERRPTS'#D
( CC
PO)ER
CO##ECTIO
#S
ERROR $
BS% $
PERE*
LOCK $
M + IO
D + C $
ADDRESS
BSA 2 ! A 3"
BE 3 $
BE 2 $
BE " $
BE 0 $
) + R $
COPROCESS
OR
SI'#ALLI#'
BS C%CLEDE,I#ATIO#
B%TE
E#ABLI
#ES
32 ! BIT
ADDRESS
Ali Karim Sir13
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Sigal )escritios of 80386
Ali Karim Sir14
CLK2 - The iut i rovides the/asic sstem cloc timigfor the oeratio of 80386.
D0! D3"- These32 lies act as/idirectioal data /us durig
differet access ccles.
A3"! A2- These are uer 30 /it of the 32 /it address /us. BE0 t. BE3- ,utut It selects the access of/te word dou/le
word of data. These sigals are geerated / A0 A1 used to
validate the data
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Ali Karim Sir1
)+R$-The write 7 read outut distiguishes the write ad readcclesfrom oe aother.
D+C$-,utut heever it is 91: it idicates the data /uscotais data whe 90: u is i halt state or e5ecutesiterrut acowledgemet.
M+IO$-This outut i differetiates /etwee the memor adI7, ccles.
LOCK$-The ;,$K< outut i ea/les the $%# to revetthe other /us masters from gaiig the cotrol of the sstem
/us.
#A$-The e5t address iut i if activated allows address
ieliig durig 80386 /us ccles.
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ADS$-The address status outut i idicates that the address
/us ad /us ccle defiitio is= 7+
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BS"6$-The /us sie B 16 iut i allows the iterfacig of 16
/it devices with the 32 /it wide 80386 data /us. Successive 16
/it /us ccles ma /e e5ecuted to read a 32 /it data from a
eriheral.
&OLD? The /us hold iut i ea/les the other /us masters
to gai cotrol of the sstem /us if it is asserted.
&LDA? The /us hold acowledge outut idicates that a valid
/us hold reCuest has /ee receivedad the /us has /ee
reliCuished / the $%#.
BS%$-The /us iut sigal idicates to the $%# that the
corocessor is /us with the allocated tas. Iut This sigal
is set / co B rocessor. It is active low sigal causig 80286
to wait or escae istructio
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Ali Karim Sir18
ERROR$-The error iut i idicates to the $%# that the
corocessor has ecoutered a error while e5ecutig its
istructio.
PERE*? The rocessor e5tesio reCuest outut sigal
idicates to the $%# to fetch a data word for the corocessor.
I#TR? This iterrut i is a masa/le iterrut that ca /e
mased usig the I- of the flag register.
#MI-A valid reCuest sigal at the omasa/le iterrut
reCuest iut i iterall geerates a o masa/le iterrut
of te2.
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RESET? A high at this iut i suseds the curret oeratio
ad restart the e5ecutio from the startig locatio.
# + C? (o coectio is are e5ected to /e left oe while
coectig the 80386 i the circuit.
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With labeled neat diagram explain memory organization of80386. (1 marks for interfacing 3 marks for description)
Ali Karim Sir20
The 80386 processor address 4GB memory withthe help of BE 0 to BE3 and A2 to A31 addresslines.
The A0 and A1 are enclosed with the !s enale
BE si"nal BE 0 to BE3 . #t selects the access of yte$ word$ do!le wordof
data. These si"nals are "enerated y A0 % A1!sed to &alidate the data.
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Ali Karim Sir21
Memory Organization:
The memory is di&ided into fo!r 8 it widememory an's$ each containin" !pto 16 ytes ofmemory.
This 32 it wide memory or"ani(ation allowsytes$ words or do!le words of memory to eaccessed directly.
)emory location ran"e from 00000000* to++++++++*.
The fo!r memory an's are accessed &ia an'Enale si"nals BE3,-BE0,.
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Ali Karim Sir22
This arran"ement allows
1/ A yte to e accessed when one an' enalesi"nal is acti&ated y microprocessor.
2/ A word can e accessed when two an' enalesi"nals are acti&ated.
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+egister ,rgaisatio
Ali Karim Sir23
The 80386 has eight 32 /it geeral urose registers whichma /e used as either 8 /it or 16 /it registers.
A 32 /it register ow as a e5teded register is rereseted/ the register ame with refi5 >.
>5amle ? A 32 /it register corresodig to AD is >AD
similarl &D is >&D etc. The 16 /it registers &% S% SI ad )I i 8086 are ow
availa/le with their e5teded sie of 32 /it ad are ames as>&%>S%>SI ad >)I.
AD reresets the lower 16 /it of the 32 /it register >AD. &% S% SI )I reresets the lower 16 /it of their 32 /it
couterarts ad ca /e used as ideedet 16 /it registers.
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'E#ERAL DATA A#D ADDRESS RE'ISTERS
I#STRCTIO# POI#TER A#D ,LA' RE'ISTER
SE'ME#T SELECTOR RE'ISTERS
CODE SE'ME#T
DATA SE'ME#T
CS
SS
DS
ES
,S
'S
EIP
E,LA'S
IP
,LA'S
0"63" "/
ESP
EBP
EDI
ESI
EDX
ECX
EBX
EAX
SP
BP
DI
SI
DX
CX
BX
AX
0"63" "/
STACK SE'ME#T
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The si5 segmet registers availa/le i 80386 are $S SS )S
>S -S ad *S. The $S ad SS are the code ad the stac segmet registers
resectivel while )S >S -S *S are 4 data segmetregisters.
A 16 /it istructio oiter I% is availa/le alog with 32 /itcouterart >I%.
Flag Register of 80386? The -lag register of 80386 is a 32 /itregister. ,ut of the 32 /its Itel has reserved /its )18to )31 )
ad )3 while )1is alwas set at 1.Two e5tra ew flags are
added to the 80286 flag to derive the flag register of 80386.The are E" ad +- flags.
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C,(M R, 0 #T IOPL O, I, T, S, , 0 A, 0 P, "
0"231/68"0"""2"3"1"/
D,
"6""83"
RESER(ED ,ORI#TEL
,LA'S
-;A* +>*IST>+ ,- 80386
,
L
A
'
S
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(M 4 Virtual Mode Flag? If this flag is set the 80386 etersthe virtual 8086 mode withi the rotectio mode. This is to /e
set ol whe the 80386 is i rotected mode. I this mode ifa rivileged istructio is e5ecuted a e5cetio 13 is
geerated. This /it ca /e set usig I+>T istructio or a
tas switch oeratio ol i the rotected mode. RF- Resume Flag? This flag is used with the de/ug register
/reaoits. It is checed at the startig of ever istructioccle ad if it is set a de/ug fault is igored durig the
istructio ccle. The +- is automaticall reset after successfule5ecutio of ever istructio e5cet for I+>T ad %,%-
istructios.
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Ali Karim Sir28
Control Registers? The 80386 has three 32 /it cotrol registers
$+0 $+2ad $+3to hold glo/al machie status ideedet
of the e5ecuted tas. ;oad ad store istructios are availa/leto access these registers.
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PG- Paging Enable
#f G is et to enale n hip a"in" nit.
#f G is reset to disale n hip a"in" nit.R- Reserved
This it is reser&ed and when loadin" 50 caresho!ld e ta'en to not alter the &al!e of this it.
TS- Task Switch ag #f this a" is set to 1$ it will indicate the ne7t
instr!ction !sin" the processor e7tension and will"enerate the e7ception .
#t allows the to test whether the c!rrentprocessor e7tension is for c!rrent tas'.
EM- Em!late "rocessor e#tension ag
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EM- Em!late "rocessor e#tension ag
#f this a" is set to 1$ it allows the "eneration of e7ception 9processor e7tension not present / and will permit theem!lation of the processor e7tension y the .
9#f this a" is set and the processor e7tension is asent it willallow the to wor' as a coprocessor/
MP- Monitor Processor e#tension ag
#f this a" is set to 1$ it allows the :ait instr!ction to"enerate a processor e7tension asent e7ception i.e.
e7ception n!mer . #n short when this a" is set to 1 it indicates the asence of
coprocessor 9processor e7tension/
if its not present and permits the em!lation of the processore7tension y the .
PE- Protection Enable
The E it is !sed to switch etween 5eal and rotected)ode.
#f it is set$ 80386 operates in the rotected )ode and if E is
reset$ processor in 5eal )ode. E it can e set or reset onl loadin ): or 50.
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Ali Karim Sir31
E#"lain $!nctions o$ %eb!g register o$ &'(&)
*+-,.*diagram: marks/ e#"lanation marks.
%eb!g registers :
There is a set of 8 de!" re"isters for hardwarede!""in".
The ;50 to ;53 are !sed to store pro"ramcontrollale rea'point addresses.
;54 and ;5< are not !sed and are reser&ed y#ntel.
The ;56 A=; ;5 are !sed to hold the rea'pointstat!s and rea'point control information
respecti&ely.
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Deb5 reister .7 80386
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E#"lain test register $ormat o$ &'(&) withs!itable diagram0 1M 2M $or diag/ M $ore#"ln03
Test Register:- TR) 4 TR5 6
sed to test translation loo' aside !>er 9T?B/!sed with pa"in".
T56 % T5 are !sed for translation loo' aside!>er 9T?B/.
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Ali Karim Sir34
E F G1 H Ealid T;& etr
) F G1 H T;& etr ivalid or dirt.
# F A /it for T;&.
F Idicates that area addressed / T;& etr is
writa/le.
$ F G0 H rite or immediate loo u =1! for T;&.
%; F hit of logic 1.+>% F Selects which /loc of T;& is writte.
it rate ? if the age is matched.
"iss rate ? if the age is missed.
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Ali Karim Sir3
E#"lain the system address register o$micro"rocessor &'(&)7*%iagram M 4E#"lain M.
80386 has 32re"isters reso!rces in di>erentcate"ories$ system address re"ister is one ofthem.
System 8ddress Registers +o!r special
re"isters are de@ned to refer to the descriptortales s!pported y 80386.
The 80386 s!pports fo!r types of descriptor tales
Gloal descriptor tale 9G;T/$ #nterr!pt descriptor tale 9#;T/$
?ocal descriptor tale 9?;T/ and
Tas' tate e"ment9T/
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Ali Karim Sir36
The addresses of these tales and se"ments arestored in special re"isters 'nown as ystemAddress and ystem 5e"isters namely as.
G%TR Global %escri"tor Table Register: 9%TR 9nterr!"t %escri"tor Table Register
This re"ister points to a tale of entry pointsfor interr!pt handler so These re"isters point to
the se"ment descriptor talesi.e. they hold linearase address %16it limit of G;T and #;Trespecti&ely.
Task State Register
This re"ister points to the information neededy the processor to de@ne ?ocal ;escriptor Tale5e"ister Ao&e the c!rrent tas' ?;T5 twore"isters hold 16 it selector for ?;T % T
descriptor respecti&ely.
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Ali Karim Sir38
ADDRESSIN M!DES? The 80386 suorts overall eleve
addressig modes to facilitate efficiet e5ecutio of higher
level laguage rograms.
I case of all those modes the 80386 ca ow have 32/it
immediate or 32 /it register oerads or dislacemets. The 80386 has a famil of scaled modes. I case of scaled
modes a of the ide5 register values ca /e multilied / a
valid scale factor to o/tai the dislacemet.
The valid scale factor are 1 2 4 ad 8.
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0 E#"lain Real Mode o$ &'(&) *S-,(.
2) Marks $or %escri"tion and Marks $or%iagram3
0 +ith s!itable ;g!re/ e#"lain 8ddress translational inReal 8ddressing mode o$ &'(&)micro"rocessor0 *+-,.
9'1 marks $or diagram/ '1 marks $ore#"lanation.
After reset$ the 80386 starts from memory location+++++++0* !nder the real address mode.
#n the real mode$ 80386 wor's as a fast 8086 with32-it re"isters and data types.
#n real mode$ the defa!lt operand si(e is 16 it !t32- it operands and addressin" modes may e!sed with the help of o&erride pre@7es.
The se"ment si(e in real mode is 64'$ hence the
32-it e>ecti&e addressin" m!st e less than0000+++++*.
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Ali Karim Sir41
Memory 8ddressing in Real Mode:
#n the real mode$ the 80386 can address at the
most 1)ytes of physical memory !sin" addresslines A0-A1.
a"in" !nit is disaled in real addressin" mode$and hence the real addresses are the same as thephysical addresses.
To form a physical memory address$ appropriatese"ment re"isters contents 916-its/are shiftedleft y fo!r positions and then added to the 16-ito>set address formed !sin" one of the addressin"
modes$ in the same way as in the 80386 realaddress mode.
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Ali Karim Sir42
The se"ment in 80386 real mode can e read$
write or e7ec!ted$ i.e. no protection is a&ailale. Any fetch or access past the end of the se"ment
limit "enerates e7ception 13 in real addressmode.
The se"ments in 80386 real mode may eo&erlapped or non-o&erlapped.
The interr!pt &ector tale of 80386 has eenallocated 1Cyte space startin" from 00000* to
003++*.
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Ali Karim Sir43
E#"lain "rotected virt!al addressing mode o$&'(&)
*+-,(. 2%iagram M/ %escri"tion M3
#n this mode 80386 can address 4 GB of physicalmemory.
#n this mode contents of se"ment re"ister are!sed as selectoraddress descriptor containin"
se"ment ase address % access ri"htytes of ase"ment.
The o>set is added within se"ment ase addressto calc!late linear address % feat!re !sed as
physical address.The pa"in" !nit wor's in this.
The lar"e se"ment of a memory is di&ided into 4' si(e pa"es$ the pa"in" !nit con&erts linear
address into physical address.
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SELECTOR O,,SET
MEMOR% OPERA#D
SE'ME#T BASE ADDRESS
SE'ME#T LIMIT
P TO
1 'B
SELECTED
SE'ME#T
%rotected "ode Addressig ithout %agig #it
18 + 32 ! BIT POI#TER
03" + "/1 + 3"
SELECTOR O,,SET
ACCESS RI'&T
LIMIT
BASE ADDRESS
SE'ME#T DESCRIPTOR
9
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Ali Karim Sir4
*: C.;
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E
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Pain O
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>ach tas has three comoets ?
1! %age )irector 2! %age Ta/le 3! %age
Pae Diret.r-4
The sie of age director is 4 / each director etr has 4/tes therefore total 1024 etries are ossi/le i director.The ta/le shows the etr format for age director.
Pae Table-4
>achage ta/le is also of 4 / ma5imum 1024 etries are
ossi/le similar to age director.It cotais the startig address of age the uer 20 /it )31 B
)12 use age frame addresscom/ied with lower 12 /its of
liear address A12 B A21 are used to select 1024 age ta/leetries.
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Desribe Enablin an= Disablin .7 Pain in 80386:
?)4"3@?1M@The cotrol register $+0 to $+3 cotrols the agig oeratio of
80386.$+0 holds the "S cotaiig %* /it i.e. 31th /it. If %* F 1
age traslatio for liear address ito hsical addressi.e.
agig oeratio is ea/led.
Similarl if %* F 0 i.e. reset rovides disa/lig or disa/le agigoeratio.
After the %* /it is set age traslatio taes effect o the te5t
istructioad
if the liear addresses from which ou are e5ecutig are ot at
the same hsical addressthe were /efore age traslatio too
effect ou are goig to wid u somewhere ue5ected.
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-or this reaso tae followig stes? )isa/le iterrut icludig ("I.
>a/le agig ol from aage that is idetified maed -lush the istructio refetch Cueue immediate after the ",E
istructio that ea/les agig.
)isa/lig agig ivolves the same haards that ea/lig it does.
&e sure that our code will /e maed the same hsical sace
after the age traslatio is tured off ad flush the refetch Cueue
afterward.
Ali Karim Sir0
)at =. .5 ;eant b TLB &. =.es it el< te a==ress
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)at =. .5 ;eant b TLB &. =.es it el< te a==ress
al5lati.n
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The agig uit receives 32 /it liear address from segmetatio
uit.The uer 20 /it =a31 B a12! gives age director ath ta/le
address /its the are comared with all 32 /it etries i T;&.If it matches hsical address is calculated from match T;&
etries lace o address /us.To seed u the coversio rocess of liear address to hsical
address.
$ache of 32 D 4 /te is rovided to store a 32 /it age ta/le etrthat is ow as T;& =Traslatio ;oo aside &uffer!.
If age ta/le etr is ot i T;& 80386 reads to aroriate age
director etr set or reset 9%: 9A: /it.
Ali Karim Sir2
E
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E
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,l a few ages of the segmets which are reCuired curretl for
the e5ecutio eed to /e availa/le i the hsical memor.Thus the memor reCuiremet of the tas is su/statiall reduced
reliCuishig the availa/le memor for other tass.heever the other ages of tas are reCuired for e5ecutio the
ma /e fetched from the secodar storage.The revious age which are e5ecuted eed ot /e availa/le i the
memor ad hece the sace occuied / them ma /e
reliCuished for other tass.Thus agig mechaism rovides a effective techiCue to maage
the hsical memor for multitasig
sstems.
Ali Karim Sir4
Pain nit-
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Pain nit-
The agig uit of 80386 uses a two level ta/le mechaism to
covert a liear address rovided / segmetatio uit itohsical addresses.The agig uit coverts the comlete ma of a tas ito
ages each of sie 4K.The tas is further hadled i terms of its age rather tha
segmets.The agig uit hadles ever tas i terms of three
comoets amel age director age ta/les ad age
itself.
Ali Karim Sir
Pain Desri
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<
The cotrol register $+2 is used to store the 32/it liear address at
which the revious age fault was detected.
The $+3 is used as age director hsical /ase address register tostore the hsical startig address of the age director.
The lower 12 /it of the $+3 are alwas ero to esure the age sie
aliged director.
A move oeratio to $+3 automaticall loads the age ta/le etrcaches ad a tas switch oeratio to load $+0 suita/l.
Ali Karim Sir6
Pae Diret.r -
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Pae Diret.r -This is at the most 4K/tes i sie.>ach director etr is of 4 /tes thus a total of 1024etries are allowed i a director.The uer 10 /its of the liear address are used as a ide5 to thecorresodig age director etr.The age director etries oit to age ta/les.
Pae Tables->ach age ta/le is of 4K/tes i sie ad ma cotai a ma5imum
of 1024 etries.The age ta/le etries cotai the startig address of the age ad
the statistical iformatio a/out the age.The uer 20 /it age frame address is com/ied with the lower 12
/it of the liear address.The address /its A12 A21 are used to select the 1024 age ta/le
etries.
The age ta/le ca /e shared /etwee the tass. Ali Karim Sir@
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+hat is "aging7 E#"lain enabling and disabling"aging o$ &'(&)0
*"aging :de;nition : , marks/ enabling and
disabling e#"lanation : 1 marks/ diagram o$
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The effective address =offset! is added with segmet /ase
address to calculate liear address. This liear address is
further used as hsical address if the agig uit is disa/led
otherwise the agig uit coverts the liear address ito
hsical address.
The agig uit is a memor maagemet uit ea/led ol i
rotected mode. The agig mechaism allows hadlig of
large segmets of memor i terms of ages of 4K/te sie.
The agig uit oerates uder the cotrol of segmetatio
uit. The agig uit if ea/led coverts liear addresses ito
hsical address i rotected mode.
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