abc

Computer Architecture and Organization

Unit I

Architecture & Organization Architecture is those attributes visible to the programmer

Instruction set, number of bits used for data representation, I/O

mechanisms, addressing techniques.

Organization is how features are implemented (Transparent to the

programmer)

Control signals, interfaces, memory technology.

Architecture & Organization Conti... All Intel x86 family share the same basic architecture

The IBM System/370 family share the same basic architecture(1970)

Organization differs between different versions

Structure & Function

A computer is a complex system: contemporary computers contains

millions of elementary electronic components.

The hierarchical nature of complex system is essential for both their

design and description.

The designer need only deal with a particular level of the system at a time.

at each level, the system consists of a set of components and their

interrelationships.

Structure & Function

At each level, the designer is concerned with

structure and function .

Structure is the way in which components relate to

each other

Functions All computer functions are:

Data processing: (must be able to process data)

Data storage: (short time and long term Ex: files)

Data movement: (when data are received from or delivered to a device

that directly connected to the computer ,the process known as input-

output (I/O) and the device is referred to as a peripheral.

Control: ( above 3 functions and manages the resources)

Function is the operation of individual components as part of the structure

Functional View

Operations (a) Data movement

Operations (a) Data movement conti… Simple transferring data from one peripheral or communications line to

another.

when data are moved over longer distance ,to or from a remote device, the

process is known as data communication.

the computer must be able to move data between itself and the outside

world.

Operations (b) Storage

Operations (b) Storage conti…. Data transferred from the External environment to computer storage (read)

and vice versa (write).

Short-term storage used to store data temporarily.

long-term storage used to store data permanently (files of data are stored

on the computer for subsequent retrieval and update.

Operation (c) Processing from/to storage

Operation (d)Processing from storage to I/O

Structure - Top Level

Computer

Main Memory

InputOutput

SystemsInterconnection

Peripherals

Communicationlines

CentralProcessing Unit

Computer

Structure….• Four main structural components:

- central processing unit(CPU): controls the operation of the computer and perform its data processing functions: often simply referred to as processor.- Main memory: stores data- I/O: moves data between computer and its external environment.- system interconnections: some mechanism that provides for communication among CPU,mainmemory, and I/O.

Structure - The CPU

Computer Arithmeticand Login Unit

ControlUnit

Internal CPUInterconnection

Registers

CPU

I/O

Memory

SystemBus

CPU

Structure - The CPU( components) • Four main components:- control unit : controls the operation of CPU and hence the computer.- Arithmetic and logic unit(ALU): perform the computer’s data processing function (addition ,subtraction etc)- Registers: provides storage internal to the CPU.- CPU interconnection: some mechanism that provides for communication among the control unit,ALU, and registers.

Structure - The Control Unit

CPU

ControlMemory

Control Unit Registers and Decoders

SequencingLogin

ControlUnit

ALU

Registers

InternalBus

Control Unit

First-Generation Computers• Late 1940s and 1950s• Stored-program computers• Programmed in machine level language• Examples: IAS, ENIAC, EDVAC, UNIVAC,

Mark I, IBM 701• UNIVAC ( Universal Automatic computer )• ENIAC (Electronic numerical integrator

and computer)• EDVAC ( Electronic Discrete Variable

computer)

ENIAC - background• Electronic Numerical Integrator And

Computer• Eckert and Mauchly• University of Pennsylvania• Trajectory tables for weapons • Started 1943• Finished 1946

—Too late for war effort

• Used until 1955.

ENIAC – details:• Decimal (not binary)• 20 accumulators of 10 digits• Programmed manually by switches• 18,000 vacuum tubes• 30 tons• 15,000 square feet• 140 kW power consumption• 5,000 additions per second

von Neumann/Turing• Stored Program concept• Main memory storing programs and data• ALU operating on binary data• Control unit interpreting instructions from

memory and executing• Input and output equipment operated by

control unit• Princeton Institute for Advanced Studies

—IAS

• Completed 1952

John von Neumann (1903-1957)

Structure of von Neumann machine

IAS Computer Machine Language• 40-bit word, two machine instructions per

word.

Left instruction Right instruction

7 8bit 0

8-bit opcode 12-bit memory address(operand)

19 20 27 28 39

IAS - details• 1000 x 40 bit words

—Binary number—2 x 20 bit instructions

• Set of registers (storage in CPU)—Memory Buffer Register—Memory Address Register—Instruction Register—Instruction Buffer Register—Program Counter—Accumulator—Multiplier Quotient

Structure of IAS –detail

Registers

• Memory buffer Register(MBR):contains a word to be stored in memory ,or is used to receive a word from memory.

• Memory Address Register (MAR):specifies address in memory or the word to be written from or read into the MBR.

• Instruction Register(IR):contains the 8 bit opcode instruction being executed.

• Instruction Buffer Register (IBR):employed to hold temporarily the right hand instruction from a word in memory.

• Program Counter (PC):contains the address of the next instruction-pair to be fetched from memory.

• Multiplier Quotient ( MQ): (for multiply and divide instruction)used to store the remainder.

IAS Instructions • The IAS computer had a total of 21 instructions

and grouped as follows:― Data Transfer: Move data between memory and ALU

registers or between ALU Registers.― Unconditional branch:

Normally, the control unit executes instruction in sequence from memory .This sequence can be changed by a branch instruction.Conditional Branch: depends on condition.― Arithmetic: Operations performed by the ALU.― Address modify:

Address to be computed in the ALU and then inserted into instructions stored in memory.

Data Transfer InstructionsInstruction

TypeOpcode SYBOLIC Description

Data transfer

00001010 LOAD MQ AC‹― MQ

00001001 LOAD MQ M(X) MQ‹― Memory (X)

00100001 STOR M(X) Memory(X) ‹― AC

00000001 LOAD M(X) AC ‹― Memory(X)

00000010 LOAD –M(X) AC ‹― -M(X)

00000011 LOAD IM(X) AC ‹― Absolute of M(X)

Unconditional BranchInstruction

TypeOpcode Symbolic Description

Unconditional Branch

00001101 JUMP M(X,0:19) Take next instruction from left half of M(x)

00001110 JUMP M(X,20:39)

Take the instruction from

right half of M(x)

Conditional BranchInstruction Type

Opcode Symbolic Description

Conditional Branch

00001111 JUMP+M(X,0:19)

If no in AC is +ve take the next instruction from left half of M(X)

00010000 JUMP+M(X,20:39)

If no in the AC is +ve take next instruction from right half of M(X)

Arithmetic Instruction

Type Opcode Symbolic Description

Arithmetic

00000101 ADD M(X) AC+M(X)AC ‹― result

00000110 SUB M(X) AC-M(X) AC ‹― Result

00001011 MUL M(X) Multiply M(X) by MQ

AC ‹― MSBMQ ‹― LSB

00001100 DIV Divide AC by MQMQ ‹― quotient

AC ‹― REMAINDER

00010100 LSH Left shit 1 Bit position(Multiply)

00010101 RSH Shift Right bit one position (DIVIDE)

Von Neumann Bottleneck• Von Neumann architecture uses the same

memory for instructions (program) and data.

• The time spent in memory accesses can limit the performance. This phenomenon is sometimes referred to as von Neumann bottleneck.

• To avoid the bottleneck, later architectures restrict most operands to registers.

Second Generation Computers• 1955 to 1964• Transistor replaced vacuum tubes.• Magnetic core memories.• Floating-point arithmetic.• Assembly level languages • Example: IBM 7094

DEC – 1957 (Digital Equipment corporation)—Produced PDP-1 ( Programmed data

processor)

Transistors• Replaced vacuum tubes• Smaller• Cheaper• Less heat dissipation• Solid State device• Made from Silicon (Sand)• Invented 1947 at Bell Labs• William Shockley et al.

Third Generation Computers

• Beyond 1965• Integrated circuit (IC) technology.• Semiconductor memories.• Memory hierarchy, virtual memories and

caches.• Time-sharing.• Parallel processing and pipelining.• Microprogramming.• Examples: IBM 360 and 370, CYBER,

ILLIAC IV, DEC PDP and VAX, Amdahl 470

The Now Generation

• Personal computers• Laptops and Palmtops• Networking and wireless• And the future!

– Nanotechnology– Optical computing– Quantum computing– Molecular computing

Program Concept• Hardwired systems are inflexible• General purpose hardware can do

different tasks, given correct control signals

• Instead of re-wiring, supply a new set of control signals

What is a program?• A sequence of steps• For each step, an arithmetic or logical

operation is done• For each operation, a different set of

control signals is needed

Function of Control Unit• For each operation a unique code is

provided—e.g. ADD, MOVE

• A hardware segment accepts the code and issues the control signals

• We have a computer!

• You can think of a computer as a data processor.• Is it a specific-purpose machine or a general-purpose

machine?

Data processor model

• A program is a set of instructions that tells the computer what to do with data.

• A program is a set of instructions written in a computer language.

• The output data depend on the combination of two factors: the input data and the program.

Programmable data processor model

Same program, different data

Same data, different programs

Components• The Control Unit and the Arithmetic and

Logic Unit constitute the Central Processing Unit

• Data and instructions need to get into the system and results out—Input/output

• Temporary storage of code and results is needed—Main memory

Computer Components:Top Level View

Instruction Cycle• Two steps:

—Fetch—Execute

Fetch Cycle• Program Counter (PC) holds address of

next instruction to fetch• Processor fetches instruction from

memory location pointed to by PC• Increment PC

—Unless told otherwise

• Instruction loaded into Instruction Register (IR)

• Processor interprets instruction and performs required actions

Execute Cycle• Processor-memory

—data transfer between CPU and main memory

• Processor I/O—Data transfer between CPU and I/O module

• Data processing—Some arithmetic or logical operation on data

• Control—Alteration of sequence of operations—e.g. jump

• Combination of above

Example of Program Execution

Explanation • Step 1:

The PC contains the 300, the address of the first instruction. This instruction (the value 1940 in Hex) is loaded into the IR and PC Incremented.

• step 2:The first 4 bits( First Hex digit) in IR

indicate that AC is to be loaded.the remaining 12 bits (3 Hex digits) specify the address (940) from which data are to be loaded.

Explanation • Step 3:

The next instruction (5941) is fectched frunited way that you have everything om location 301 and the pc incremented.

• Step 4:The old contents of the AC and the

contents of location 941 are added and the result is stored in the AC.

• Step 5:The next instruction (2941) is fetched from location 302 and PC is incremented.

Explanation• Step 6:

The contents of the AC are stored in location 941.

Example: (PDP-11 Instruction Expressed Symbolically)

• ADD B,A stores the sum of contents of the

memory location B and A into memory location A.

A single instruction cycle with the following steps occurs

— Fetch the ADD instruction.— Read the content of memory location A

into the processor.— Read the content of memory location B

into the processor.

Conti……..• Add the Two values• Write the result from the processor to

memory location A.

Instruction Cycle State Diagram

Explanation• IAC :

Determine the Address of the next instruction to be executed .(if each instruction is 16 bits long and memory is organized into 16 bit words, then add 1 to the previous address.if,instead,memory is organized as individually addressable 8-bit bytes, then add 2 to the previous address.

• Instruction fetch (IF):Read instruction from its memory

location into the processor.

Explanation conti……• Instruction operation decoding (IOD):

Analyze instruction to determine type of operation to be performed and operands to be used.

• Operand address calculation (OAC):if the operation involves reference to an

operand in memory or available via I/O ,then determine the address of operand.

• Operand Fetch (OF):Fetch the operand from memory or ead it

from I/O.• Data Operation ( DO):

Perform the operation indicated in the instruction .

• Operand Store (OS):write the result into memory or put to

I/O. (Example PDP-11 ADD A,B results in the following sequence of states:IAC,IF,IOD,OAC,OF,OAC,OF,DO,OAC,OS.

Interrupts• Mechanism by which other modules (e.g.

I/O) may interrupt normal sequence of processing

• Program—e.g. overflow, division by zero

• Timer—Generated by internal processor timer—Used in pre-emptive multi-tasking

• I/O—from I/O controller

• Hardware failure—e.g. memory parity error

Interrupts conti……• primarily as a way to improve processing

efficiency.• For Example, most external devices are

much slower than the processor.

Interrupt Cycle• Added to instruction cycle• Processor checks for interrupt

—Indicated by an interrupt signal

• If no interrupt, fetch next instruction• If interrupt pending:

—Suspend execution of current program —Save context—Set PC to start address of interrupt handler

routine—Process interrupt—Restore context and continue interrupted

program

Transfer of Control via Interrupts

Instruction Cycle with Interrupts

Instruction Cycle (with Interrupts) -State Diagram

Multiple Interrupts• Disable interrupts

—Processor will ignore further interrupts while processing one interrupt

—Interrupts remain pending and are checked after first interrupt has been processed

—Interrupts handled in sequence as they occur

• Define priorities—Low priority interrupts can be interrupted by

higher priority interrupts—When higher priority interrupt has been

processed, processor returns to previous interrupt

Multiple Interrupts - Sequential

Multiple Interrupts – Nested

Time Sequence of Multiple Interrupts

What is an Instruction Set?• The complete collection of instructions

that are understood by a CPU.• each instruction must contains the

information required by the CPU for execution.

• Machine Code• Binary• Usually represented by assembly codes

Elements of an Instruction• Operation code (Op code)

— specifies the operation to be performed (ADD,SUB etc)

• Source Operand reference— may involve one or more source operands (input for

the operation)

• Result Operand reference—Put the answer here

• Next Instruction Reference ( Main or virtual or secondary memory)—When you have done that, do this...

Tells the CPU where to fetch the next instruction after the execution of this instruction complete.

Instruction Cycle State Diagram

Instruction Representation• In machine code each instruction has a

unique bit pattern.• In computer ,each instruction is

represented by a sequence of bits. (Difficult for programmer and reader)

• For human consumption (well, programmers anyway) a symbolic representation is used—e.g. ADD, SUB, LOAD

• Operands can also be represented in this way—ADD A,B

Mnemonics (opcode)…..• Opcodes are represented by abbreviations

called mnemonics.• Examples:

— ADD Addition— SUB Subtract— MPY Multiply— DIV Divide— LOAD Load data from memory— STOR store data to memory

Simple Instruction Format

Example • X=X+Y (X location 513 and Y

location 514 ).• 3 machine instruction are required.

— Load a register with the contents of memory location 513.

— Add the contents of memory location 514 to the register.

— Store the content of the register in memory location 513.

Instruction Types• Data processing (Arithmetic and logic

instructions).• Data storage (main memory instructions)• Data movement (I/O Instructions)• Program flow control (Test and Branch

Instructions).

Types of Operation• Data Transfer• Arithmetic• Logical• Conversion• I/O• System Control• Transfer of Control

Data Transfer• Specify

—Source—Destination—Amount of data

• May be different instructions for different movements—e.g. IBM 370

• Or one instruction and different addresses—e.g. VAX

DATA Transfer Instructions:Type Operation Name Description

Data Transfer

MOVE Transfer word or block from source to destination

Store Transfer word from processor to memory

Load(fetch) Transfer word from memory to processor

Exchange Swap contents of source and destination

Clear(reset) Transfer word of 0s to destination

Set Transfer word Transfer of 1s destination

Push Transfer word from source to top stack

Pop Transfer word from top of stack to destination

Arithmetic Instructions:Type Operation Name Description

Arithmetic

Add Computes sum of two operands

Subtract Difference bw 2 operands

Multiply Product of 2 operands

Divide Compute quotient of 2 operands

Absolute Replace operand by its absolute value

Negate Change sign of operand

Increment Add 1 to operand

Decrement Subtract 1 from operand

Arithmetic• Add, Subtract, Multiply, Divide• Signed Integer• Floating point ?• May include

—Increment (a++)—Decrement (a--)—Negate (-a)

Logical Instructions

Type Operation Name Description

Logical

AND,OR,NOT,Ex-OR Logical operation bitwise

Test Test specified condition

Compare Compares 2 operands

Set control variable Protection purpose, Interrupt handling ,timer control

Shift Left (Right) shift operand

Rotate Left (right) shift operand

Logical• Bitwise operations• AND, OR, NOT

Shift and Rotate Operations

Examples of shift and rotate operationsInput Operation Result

10100110 Logical right shift ( 3 bits)

00010100

10100110 Logical left shift( 3 bits)

00110000

10100110 Arithmetic right shift ( 3 bits)

11110100

10100110 Arithmetic left shift ( 3 bits)

10110000

10100110 Right rotate (3bits)

11010100

10100110 Left rotate 00110101

Transfer of controlType Operation Name Description

Transfer of control

Jump Unconditional Unconditional transfer

Jump Test specified condition

Jump to subroutine Jump to specified address

Return Replace the content of PC

Execute Execute instructions

Skip Increment PC to skip next Instruction

Skip condti Test conditon for skip

Halt Stop program execution

Wait (hold) Stop program execution and resume when condition satisfied

No operation No operation performed but program execution continued

Transfer of Control• Branch

—e.g. branch to x if result is zero

• Skip—e.g. increment and skip if zero—ISZ Register1—Branch xxxx—ADD A

• Subroutine call—c.f. interrupt call

Input and output:•

Type Operation Name

Description

Input (read) Transfer data from specified I/O port to destination

Output (write) Transfer data from specified from source to I/O port or device

Start I/O Transfer instruction to I/O processor to initiate I/O operation

Test I/O Transfer status information from I/O system to specified destination

Input/Output• May be specific instructions• May be done using data movement

instructions (memory mapped)• May be done by a separate controller

(DMA)

conversionType Operation name Description

Conversion

Translate Translate values in a section of memory based

on a table of correspondence

Convert Convert the contents of word a from one form to

another.

Conversion• E.g. Binary to Decimal

Systems Control• Privileged instructions• CPU needs to be in specific state

—Ring 0 on 80386+—Kernel mode

• For operating systems use

Number of Addresses (a)• 3 addresses

—Operand 1, Operand 2, Result—a = b + c;—May be a forth - next instruction (usually

implicit)—Not common—Needs very long words to hold everything

Number of Addresses (b)• 2 addresses

—One address doubles as operand and result—a = a + b—Reduces length of instruction—Requires some extra work

– Temporary storage to hold some results

Number of Addresses (c)• 1 address

—Implicit second address—Usually a register (accumulator)—Common on early machines

Number of Addresses (d)• 0 (zero) addresses

—All addresses implicit—Uses a stack—e.g. push a— push b— add— pop c

—c = a + b

Example: Y=(A-B)%(C+D*E)Instruction comment

SUB Y,A,B Y‹— A-B

MPY T,D,E T‹— D*E

ADD T,T,C T ‹— T+C

DIV Y,Y,T Y ‹— Y%T

Two-Address Instructions:Y=(A-B)%(C+D*E)

Instruction Comment

MOVE Y,A Y ‹— A

SUB Y,B Y ‹— Y-B

MOVE T,D T ‹— D

MPY T,E T ‹— T*E

ADD T,C T ‹— T+C

DIV Y,T Y ‹— Y%T

1 Address Instructions:Y=(A-B)%(C+D*E)Instruction comment

LOAD D AC ‹— D

MPY E AC ‹— AC*E

ADD C AC ‹— AC+C

STOR Y Y ‹— AC

LOAD A AC ‹— A

SUB B AC ‹— AC-B

DIV Y AC ‹— AC%Y

STOR Y Y ‹— AC

Assignment• compare one-two-three address

instructions for the following expressionX=(A+B*C)/(D-E*F)

How Many Addresses• More addresses

—More complex (powerful?) instructions—More registers

– Inter-register operations are quicker

—Fewer instructions per program

• Fewer addresses—Less complex (powerful?) instructions—More instructions per program—Faster fetch/execution of instructions

Instruction Design Decisions (1)• Operation repertoire

—How many ops?—What can they do?—How complex are they?

• Data types( The various types of data upon which operation to be performed)

• Instruction formats—Length of op code field—Number of addresses

Instruction Design Decisions (2)• Registers

—Number of CPU registers available—Which operations can be performed on which

registers?

• Addressing modes (later…)The mode or modes by which the

address of an operand is specified.• RISC v CISC

Types of Operand• Addresses• Numbers

—Integer/floating point

• Characters—ASCII etc.

• Logical Data—Bits or flags

• (Aside: Is there any difference between numbers and characters? Ask a C programmer!)

Addressing Modes:• An operand reference in an instruction

either contains the actual value of the operand (Immediate) or a reference to the address of the operand.

• The address field or fields in a typical instruction format are relatively small.

• we would like to be able to reference a large range of locations in main memory or for systems, virtual memory .To achieve this objective, a variety of addressing modes.

Addressing Modes• Immediate• Direct• Indirect• Register• Register Indirect• Displacement (Indexed) • Stack

Immediate Addressing• Operand is part of instruction• Operand = address field• e.g. ADD 5

—Add 5 to contents of accumulator—5 is operand

• Advantages:― No memory reference to fetch data― Fast

• Disadvantage:― Limited range

Immediate Addressing Diagram

OperandOpcode

Instruction

Direct Addressing• Address field contains address of operand• Effective address (EA) = address field (A)• e.g. ADD A

—Add contents of cell A to accumulator—Look in memory at address A for operand

• Advantage: ― Single memory reference to access data― No additional calculations to work out

effective address

• Disadvantage:― Limited address space

Direct Addressing Diagram

Address AOpcode

Instruction

Memory

Operand

Indirect Addressing (1)• Memory cell pointed to by address field

contains the address of (pointer to) the operand

• EA = (A)—Look in A, find address (A) and look there for

operand• e.g. ADD (A)

—Add contents of cell pointed to by contents of A to accumulator

Indirect Addressing (2)• Large address space • 2n where n = word length• May be nested, multilevel, cascaded

—e.g. EA = (((A)))– Draw the diagram yourself

• Multiple memory accesses to find operand( two memory to fetch the operand : one to get its address and second to get its value.)

• Hence slower

Indirect Addressing Diagram

Address AOpcode

Instruction

Memory

Operand

Pointer to operand

Register Addressing (1)• Operand is held in register named in

address filed• EA = R• Limited number of registers• Very small address field needed• No memory reference are required

—Shorter instructions—Faster instruction fetch

Register Addressing (2)• No memory access• Very fast execution• Very limited address space• Multiple registers helps performance

—Requires good assembly programming or compiler writing

—N.B. C programming – register int a;

• c.f. Direct addressing

Register Addressing Diagram

Register Address ROpcode

Instruction

Registers

Operand

Register Indirect Addressing

• C.f. indirect addressing• EA = (R)• Operand is in memory cell pointed to by

contents of register R• Large address space (2n)• One fewer memory access than indirect

addressing

Register Indirect Addressing Diagram

Register Address ROpcode

Instruction

Memory

OperandPointer to Operand

Registers

Displacement Addressing• EA = A + (R)• Address field hold two values• combination of direct addressing and

register indirect addressing.—A = base value—R = register that holds displacement—or vice versa

Displacement Addressing Diagram

Register ROpcode

Instruction

Memory

OperandPointer to Operand

Registers

Address A

+

Relative Addressing• A version of displacement addressing• R = Program counter, PC• EA = A + (PC)• i.e. get operand from A cells from current

location pointed to by PC• c.f locality of reference & cache usage

Base-Register Addressing• A holds displacement• R holds pointer to base address• R may be explicit or implicit• e.g. segment registers in 80x86

Indexed Addressing• A = base• R = displacement• EA = A + R• Good for accessing arrays

—EA = A + R—R++

Stack Addressing• Operand is (implicitly) on top of stack• e.g.

—ADD Pop top two items from stackand add

Basic addressing modesMode Algorithm Advantage disadvantage

Immediate Operand=A No memory reference

Limited operand magnitude

Direct EA=A Simple Limited address space

Indirect EA=(A) Large address space Multiple memory references

Register EA=R No memory reference

Limited address space

Register indirect EA=(R) Large address space Extra memory refernce

Displacement EA=A+(R) Flexibility Complexity

Stack EA=top of stack No memory reference

Limited applicability

Pentium Addressing Modes• Virtual or effective address is offset into segment

—Starting address plus offset gives linear address—This goes through page translation if paging enabled

• 12 addressing modes available—Immediate—Register operand—Displacement—Base—Base with displacement—Scaled index with displacement—Base with index and displacement—Base scaled index with displacement—Relative

Pentium Addressing Mode Calculation

PowerPC Addressing Modes• Load/store architecture

—Indirect– Instruction includes 16 bit displacement to be added to

base register (may be GP register)– Can replace base register content with new address

—Indirect indexed– Instruction references base register and index register

(both may be GP)– EA is sum of contents

• Branch address—Absolute—Relative—Indirect

• Arithmetic—Operands in registers or part of instruction—Floating point is register only

Thank you