A Primer on Simulation, Modeling, and Design of the ...ecee.colorado.edu/~ecen5807/course_material/Simulation/Spice1/...A Primer on Simulation, Modeling, and Design of the Control
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A Primer on Simulation,Modeling, and Designof the Control Loops
of Switching Regulators
Bob Erickson and Dragan MaksimovicColorado Power Electronics Center
University of Colorado, Boulder
IEEE APEC ‘03 Tutorial seminar
Introduction
+–
+
v(t)
–
vg(t)
Switching converterPowerinput
Load
–+
R
compensator
Gc(s)
vrefvoltage
reference
v
feedbackconnection
pulse-widthmodulator
vc
transistorgate driver
δ(t)
δ(t)
TsdTs t t
vc(t)
Controller
A simple dc-dc regulator system, employing a buck converter
Objective: maintain v(t)equal to an accurate, constant value V.
There are disturbances:
• in vg(t)
• in R
There are uncertainties:
• in element values
• in Vg
• in R
Objective of Seminar
Develop tools for modeling, analysis, and design of converter control systems
Need dynamic models of converters:
How do ac variations in vg(t), R, or d(t) affect the output voltage v(t)?
What are the small-signal transfer functions of the converter?
• Averaged switch modeling approach for ac modelingand simulation
• Construction of converter small-signal transfer functions
• Design of converter control systems
• Design of input EMI filters that don't disrupt control loops
• Current-programmed control of converters
Averaged switch modeling
+–
Switching converter circuit
Switchingnetwork +
–+–
Large-signal averaged circuit model
Averagedswitchmodel
d
+–
+–
DC and small-signal averaged circuit model
D+d
2)/(/)/1(1
/1)(
oo
scoc wswsQ
wsGsG
++−=
1D
2S
3K
4A
5
duty
ccm-dcm1+
-
DC, AC and Transient simulation
Model implementation for simulation
simulationmodel
linearization
Analytical results:steady-state characteristicsand small-signal dynamics
averaging
+
v1(t)
–
+–
D1
L1
C2
Q1
C1
L2 R
iL1(t)
vg(t)
Switch network
iL2(t)
+ vC1(t) –+
vC2(t)
–
–
v2(t)
+
i1(t) i2(t)
Dutycycle
d(t)
• Define a switchnetwork,containing all ofthe converterswitchingelements.
• The remainder ofthe converter islinear and time-invariant.
• The terminalvoltages andcurrents of theswitch networkcan be arbitrarilydefined.
+
v1(t)
–
+–
D1
L1
C2
Q1
C1
L2 R
iL1(t)
vg(t)
Switch network
iL2(t)
+ vC1(t) –+
vC2(t)
–
–
v2(t)
+
i1(t) i2(t)
Dutycycle
d(t)
t
v2(t)
dTs Ts
00
v2(t) T2
0
vC1 + vC2
t
i1(t)
dTs Ts
00
i1(t) T2
0
iL1 + iL2
t
v1(t)
dTs Ts
00
v1(t) Ts
0
vC1 + vC2
t
i2(t)
dTs Ts
00
i2(t) Ts
0
iL1 + iL2
The basic assumption is made that the natural time constants of theconverter are much longer than the switching period, so that theconverter contains low-pass filtering of the switching harmonics:
One may average the waveforms over an interval that is shortcompared to the system natural time constants, withoutsignificantly altering the system response.
In particular, averaging over the switching period Ts removes theswitching harmonics, while preserving the low-frequencycomponents of the waveforms.
This step removes the small but mathematically-complicatedswitching harmonics, leading to a relatively simple and tractableconverter model.
In practice, the only work needed for this step is to average the switchdependent waveforms.
v1(t) Ts= d'(t) vC1(t) Ts
+ vC2(t) Ts
i1(t) Ts= d(t) iL1(t) Ts
+ iL2(t) Ts
v2(t) Ts= d(t) vC1(t) Ts
+ vC2(t) Ts
i2(t) Ts= d'(t) iL1(t) Ts
+ iL2(t) Ts
(small switching ripple is neglected)
t
v1(t)
dTs Ts
00
v1(t) Ts
0
vC1 + vC2
t
v2(t)
dTs Ts
00
v2(t) T2
0
vC1 + vC2
t
i1(t)
dTs Ts
00
i1(t) T2
0
iL1 + iL2
t
i2(t)
dTs Ts
00
i2(t) Ts
0
iL1 + iL2
iL1(t) Ts+ iL2(t) Ts
=i1(t) Ts
d(t)
vC1(t) Ts+ vC2(t) Ts
=v2(t) Ts
d(t)
We can write
Hence
v1(t) Ts=
d'(t)d(t)
v2(t) Ts
i2(t) Ts=
d'(t)d(t)
i1(t) Ts
+–
–
⟨v2(t)⟩Ts
+
⟨i1(t)⟩Ts
Averaged switch network
+
⟨v1(t)⟩Ts
– ⟨i2(t)⟩Ts
d'(t)d(t)
v2(t) Ts
d'(t)d(t)
i1(t) Ts
Result
Modeling the switch network viaaveraged dependent sources
D' : DI1
I2
+
V1
–
–
V2
+
+
v1(t)
– D1Q1
Switch network
–
v2(t)
+
i1(t) i2(t)
Dutycycle
d(t)
Original switch network
Averaged steady-state model:“DC transformer”
• Correctly represents therelationships between the dcand low-frequencycomponents of the terminalwaveforms of the switchnetwork
Replace switch network with dc transformer model
+–
L1
C2
C1
L2 R
IL1
Vg
IL2
+ VC1 –+
VC2
–
D' : DI1
I2
+
V1
–
–
V2
+
• Can now let inductorsbecome short circuits,capacitors become opencircuits, and solve for dcconditions.
• Can simulate this modelusing PSPICE, to findtransient waveforms
+– D' : DI1 + i1
I2 + i2
I2
DD'dV1 + v1
V1
DD'd
V2 + v2
+
–
–
+
When duty cycle varies, the transformer becomes a nonlinear element.Linearization of the model about a quiescent operating point yields:
A general small-signal ac model for the PWM switch networkoperating in CCM.
Transistor port Diode port
+–
L1
C2
C1
L2 R
+– D' : D
I2
DD'd
V1
DD'd
Vg + vg
IL1 + i L1
IL2 + i L2
VC1 + vC1
VC2 + vC2
+
–
Replace switch network with small-signal ac model:
Can now solve thismodel to determine actransfer functions
+
v2(t)
–
i1(t) i2(t)
+
v1(t)
–
+–1 : DI1 + i1 I2 + i2
I2 dV1 + v1
V1 d
V2 + v2
+
–
+
–
+– D' : 1I1 + i1 I2 + i2
I1 dV1 + v1
V2 d
V2 + v2
+
–
+
–
+
v2(t)
–
i1(t) i2(t)
+
v1(t)
–
+
v2(t)
–
i1(t) i2(t)
+
v1(t)
–
+– D' : DI1 + i1 I2 + i2
I2
DD'dV1 + v1
V1
DD'd
V2 + v2
+
–
+
–
Converter Gg0 Gd0 ω 0 Q ω z
buck DVD
1LC R C
L ∞
boost1D'
VD'
D'LC D'R C
LD' 2R
L
buck-boost – DD'
VD D' 2
D'LC D'R C
LD' 2 RD L
where the transfer functions are written in the standard forms
Gvd(s) = Gd0
1 – sωz
1 + sQω0
+ sω0
2
Gvg(s) = Gg01
1 + sQω0
+ sω0
2
Control-to-output and line-to-output transfer functions Gvd(s) and Gvg(s)
ccm1
averagingswitch
network1
2
3
4
D
S
K
A
+
_
v1(t)
+
_
v2(t)
i1(t) i2(t)
+–
1
2
3
4
D
S
K
A
Et Gd
5
duty
averaged-switchmodel
(sub-circuit)
d
1-dd
v21-dd
i1
+
_
v2
+
_
v1
i2i1
• Controlled voltage source Et replaces the transistor, controlledcurrent source Gd replaces the diode
• Duty ratio d is input to the subcircuit
• Large-signal, nonlinear model suitable for DC, AC or Transientsimulation
• The same model can be applied in any two-switch PWM converter(the transistor and the diode need not have a common node)
• Limitations: ideal switches, CCM only, valid for two-switchconverters without isolation transformer
CCM Averaged-Switch ModelPSpice Implementation: ccm1
*********************************************************** MODEL: ccm1* Application: two-switch PWM converters* Limitations: ideal switches, CCM only, no transformer*********************************************************** Parameters: none*********************************************************** Nodes:* 1: transistor+ (D)* 2: transistor- (S)* 3: diode cathode (K)* 4: diode anode (A)* 5: duty ratio (duty)**********************************************************.subckt ccm1 1 2 3 4 5Et 1 2 value=(1-v(5))*v(3,4)/v(5)Gd 4 3 value=(1-v(5))*i(Et)/v(5).ends**********************************************************
+–
1
2
3
4
D
S
K
A
Et Gd
5
duty
averaged-switchnetwork
(sub-circuit)
1D
2S
3K
4A
5
duty
ccm1
U1
Comments
• Subcircuit ccm1 is implementation of a large-signal, nonlinearaveraged model of the switch network
• Averaged circuit model of the converter is obtained simply by replacingswitching devices with the averaged-switch subcircuit model
• Linearization and AC small-signal analysis are performed by thesimulator
• Small-signal dynamic responses can be easily generated for differentoperating points or different sets of parameter values
1T
he buck converter illustrated in Fig. 1 operates in the continuous conduction mode, and supplies 5 V
at10 A
to load R. T
he element values are L =
6 µH, C
= 200 µF. A
ll elements are ideal.
(a)U
se averaged switch m
odeling and computer sim
ulation to plot the magnitude and phase of the
control-to-output transfer function Gvd (s). Y
ou should turn in: the plots of
||Gvd
|| and
∠G
vd , andyour netlist or schem
atic.
(b)A
n input filter is now added, as illustrated in Fig. 2. R
epeat Part (a): use averaged switch m
odel-ing and com
puter simulation to plot the m
agnitude and phase of the control-to-output transferfunction
Gvd (s). Y
ou should again turn in the plots of
||Gvd
|| and
∠G
vd , and your netlist or sche-m
atic. Does the input filter substantially change the m
agnitude of Gvd ? the phase? H
ow m
anypoles and zeroes does G
vd (s) now contain?
(c)In the circuit of Fig. 2, the load takes a step change from
10 A to 2 A
(i.e., the value of Rchanges). U
se computer sim
ulation to plot the output voltage response to this change in loadcurrent. H
ow long is the settling tim
e (i.e., the time from
the step until the output voltagerem
ains within 1%
of 5 V)?
+–R
+v–
C
L
D1
Q1
Vg
6µ
H200µ
F12 V
Fig. 1
CC
M buck converter.
R
+v–
+–C
LL
f
Cf
D1
Q1
Vg
6µ
H200µ
F100
µF
300µ
H
Fig. 2
Addition of an input filter to the C
CM
buck converter of Fig. 1.
Basic CCM Buck Example (Part a)Netlist
CCM Simulation Problem, part (a)Vg 1 0 dc 12Rg 1 1a 1uXswitch 1a 2 2 0 4 CCM1.lib switch.libL1 2 2a 6uRL1 2a 3 1uC 3 0 200uR 3 0 0.5vd 4 0 dc 0.4166667 ac 1.probe.ac DEC 201 10 100k.end
+– R
+
v
–
C
L
Vg
1
2
3
45
CCM1
Rg RL1
Xswitch
+–Vd
1
0
1a
2
4
2a3
Probe output: part (a)Control-to-output transfer function
Buck with input filter: Part (b)Netlist
CCM Simulation Problem, part (b)
Vg 1 0 dc 12Rg 1 1a 1u
Lf 1a 1b 300uCf 1b 0 100u
Xswitch 1b 2 2 0 4 CCM1.lib switch.lib
L1 2 2a 6u
RL1 2a 3 1uC 3 0 200u
R 3 0 0.5vd 4 0 dc 0.4166667 ac 1
.probe
.ac DEC 201 10 100k
.end
+– R
+
v
–
C
L
Vg
1
2
3
45
CCM1
Rg RL1
Xswitch
+–Vd
1
0
1a
2
4
2a3
Lf
Cf
1b
Buck with input filter: Part (b)Probe output, control-to-output transfer function
Buck with input filter: Part (c)Transient response: netlist
CCM Simulation Problem, part (c)Vg 1 0 dc 12Rg 1 1a 1uLf 1a 1b 300u IC=4.167Cf 1b 0 100u IC=12Xswitch 1b 2 2 0 4 CCM1.lib switch.libL1 2 2a 6u IC=10RL1 2a 3 1uC 3 0 200u IC=5Sload 3 0 5 0 load.model load VSWITCH Ron=0.5 Roff=2.5VLC 5 0 PULSE(-2 2 0 0 0 50M 101M)RLC 5 0 1Megvd 4 0 dc 0.4166667Rd 4 0 1Meg.probe.tran 5u 100m uic.end
+– C
L
Vg
1
2
3
45
CCM1
Rg RL1
Xswitch
+–Vd
1
0
1a
2
4
2a3
Lf
Cf
1b
Rd
SloadRon = 0.5Roff = 2.5
+–VLC
5
RLCPulse
Part (c): Probe outputOutput voltage transient response to step change in load
Discontinuous Conduction Mode (DCM)
Occurs at light load, when inductor current ripple causesdiode current to reach zero before end of switchingperiod
Leads to major change in switch networkcharacteristics:–Steady-state output voltage becomes load dependent–Dynamics become simpler: one pole (and possibly right half-
plane zero) are moved to very high frequency, and cannormally be ignored
We need to incorporate DCM into our averaged switchmodel
d1Ts
Ts
t
i1(t)ipkArea q1
i1(t) Ts
v1(t)
0
vg – v
v1(t) Tsvg
i2(t)ipk Area q2
v2(t)
0
vg – v
– v
i2(t) Ts
v2(t) Ts
d2Ts d3Ts
DCM waveformsBuck-Boost example
t
iL(t)
0
ipk
vg
L
vL
vL(t)vg
v
0
+–
L
C R
+
v
–
vg
iL
+vL–
Switch network
+
v1
–
–
v2
+
i1 i2
i1(t) Ts=
d 12(t) Ts
2Lv1(t) Ts
i1(t) Ts=
v1(t) Ts
Re(d1)
Re(d1) = 2Ld 1
2 Ts
v1(t) Ts
i1(t) Ts
Re(d1)
+
–
Low-frequency components of input port waveformsobey Ohm’s law
i2(t) Ts=
d 12(t) Ts
2L
v1(t) Ts
2
v2(t) Ts
i2(t) Tsv2(t) Ts
=v1(t) Ts
2
Re(d1)= p(t)
Ts
p(t)
+
v(t)
–
i(t)
• Output port is a source of power p(t)
• Power p(t) is independent of load characteristics
• Power p(t) is dependent on (equal to) the power apparentlyconsumed by the switch network input port
+–
L
C R
+
v
–
vg
iL
+vL–
Switch network
+
v1
–
–
v2
+
i1 i2
i2(t) Ts
v2(t) Tsv1(t) Ts
i1(t) Ts
Re(d)
+–
L
C R
+
–
+
–
–
+ v(t)Ts
vg(t) Ts
p(t)Ts
Original circuit
Averaged model
• Determine averaged terminal waveforms of switch network
• In each case, averaged transistor waveforms obey Ohm’s law, whileaveraged diode waveforms behave as dependent power source
• Can simply replace transistor and diode with the averagedmodel as follows:
i2(t) Ts
+
–
v2(t) Tsv1(t) Ts
i1(t) Ts
Re(d1)
+
–
+
v2(t)
–
+
v1(t)
–
i1(t) i2(t)p(t)
Ts
Re(d)
+–
L
C R
+
–
v(t)Ts
vg(t) Ts
Re(d)+–
L
C R
+
–
v(t)Ts
vg(t) Ts
Buck
Boost
p(t)Ts
p(t)Ts
Re = 2Ld 2Ts
+
v2(t)
–
i1(t) i2(t)
+
v1(t)
–
+
v2(t)
–
i1(t) i2(t)
+
v1(t)
–
+
–
+
–
v1 r1 j1d g1v2
i1
g2v1 j2d r2
i2
v2
In any event, a small-signal two-port model is used, of the form
Small-signal DCM switch model parameters
–
+
+–v1 r1 j1d g1v2
i1
g2v1 j2d r2
i2
v2
Small-signal DCM switch model parameters
Switch network g1 j1 r1 g2 j2 r2
Generaltwo-switch
0
Buck
Boost
2V1
DRe
Re2
MRe
2V1
DMRe
M 2Re
1Re
2(1 – M)V1
DRe
Re2 – MMRe
2(1 – M)V1
DMRe
M 2Re
1(M – 1)2 Re
2MV1
D(M – 1)Re
(M – 1)2
M 2 Re2M – 1
(M – 1)2 Re
2V1
D(M – 1)Re(M – 1)2Re
→
Buck, boost, and buck-boost converter models all reduce to
+
–
+– r1 j1d g1v2 g2v1 j2d r2 C R
DCM switch network small-signal ac model
vg v
Transfer functions
Gvd(s) =v
dvg = 0
=Gd0
1 + sωp
Gd0 = j2 R || r2
ωp = 1R || r2 C
Gvg(s) =v
vg d = 0
=Gg0
1 + sωp
Gg0 = g2 R || r2 = M
withcontrol-to-output
line-to-output
Converter Gd0 Gg0 ω p
Buck 2VD
1 – M2 – M M
2 – M(1 – M)RC
Boost 2VD
M – 12M – 1 M
2M – 1(M– 1)RC
Buck-boost VD M
2RC
v1(t)
d
+
v1
1
2
3
45
dutyd
+
_
v2
_
i2i1
Re(d)p(t)
switchnetwork
1
2
3
4
+
_
+
_
v2(t)
i1(t) i2(t)
1
2
3
45
dutyd
+
_
v2
_
i2i1
averaged-switchmodel
CCM
+–
1
2
3
4
Et Gd
5
duty
1-dd
v21-dd
i1
+
_
v2
+
_
v1
i2i1
?
averaged-switchmodel
DCM
averaged-switchmodel
CCM/DCM
Combined CCM/DCMAveraged Switch Model
3
4
K
A
Et Gd
5
duty
averaged-switchmodel
CCM/DCM
d
1-uu
i1
+
_
v2
i2
+–
1
2
D
S
1-uu
v2
+
_
v1
i1
+
=DCM
v
iLfd
d
CCMd
u
s
,2
,
2
12
2
CCM/DCM boundary:
+=
2
12
2
2,
vi
Lfd
ddMAXu
s
u = equivalent switch duty ratio
CCM/DCM Averaged-Switch ModelPSpice Implementation: ccm-dcm1
*************************************************************************************** MODEL: ccm-dcm1* Application: two-switch PWM converters, CCM or DCM* Limitations: ideal switches, no transformer*************************************************************************************** Parameters:* L=equivalent inductance (relevant for DCM)* fs=switching frequency*************************************************************************************** Nodes: (same as in ccm1)**************************************************************************************.subckt ccm-dcm1 1 2 3 4 5 params: L=1 fs=1E6Et 1 2 value=(1-v(u))*v(3,4)/v(u)Gd 4 3 value=(1-v(u))*i(Et)/v(u)Ga 0 a value=MAX(i(Et),0)Va a bRdummy b 0 10Eu u 0 table MAX(v(5), v(5)*v(5)/(v(5)*v(5)+2*L*fs*i(Va)/v(3,4))) (0 0) (1 1).ends**************************************************************************************
1T
he flyback converter illustrated in Fig. 1 can operate open-loop with the follow
ing conditions:
In all three cases, the terminal voltages are V
g = 48 V
and V =
5 V. T
he switching frequency is 150 kH
z. T
he transformer has negligible leakage inductance, and its m
agnetizing inductance is 200 µH referred to
the primary. A
ll elements are ideal.
(a)D
etermine the operating m
ode (CC
M or D
CM
) and duty cycle for each operating point listed inTable 1.
For parts (b) to (d), use the switch.lib m
odel “CC
M-D
CM
2.” You m
ay also find the switch.lib subcircuit
“transformer” to be useful. It is suggested that you plot the operating point A
, B, and C
data on the same
chart. For each of these parts, you should turn in: (i) your netlist or schematic, and (ii) your plots.
(b)U
se computer sim
ulation to plot the magnitude and phase of the control-to-output transfer func-
tionG
vd , at operating points A, B
, and C. C
ompare.
(c)U
se computer sim
ulation to plot the magnitude and phase of the line-to-output transfer function
Gvg , at operating points A
, B, and C
. Com
pare.
(d)U
se computer sim
ulation to plot the magnitude and phase of the output im
pedance Zout (as
defined in Fig. 1) at operating points A, B
, and C. C
ompare.
Table 1C
onverter operating points
Operating point
Load resistance R
A1
ΩB
2
ΩC
3
Ω
+–
C680
µF
R
+v(t)
–
10 :1
vg (t)
L200
µH
Zout
fs = 150 kH
z
Fig. 1
Flyback converter.
Solution to DCM/CCM simulation problemCalculations
Part (a)
Operating Point Load Resistance Mode Duty Cycle
A 1 Ohm CCM 0.510
B 2 Ohms CCM 0.510
C 3 Ohms DCM 0.466
Part (b): Gvd
Green: A, Red: B (higher Q-factor), Blue: C (DCM)
Part (c): Gvg
Comments similar to Gvd above, but no RHP zero.
Part (d): Zout
Note low-frequency asymptote is inductive in CCM and resistive in DCM.
Simulation of control-output transfer functionNetlist
DCM-CCM Gvd Simulation Problem, point A. Change R for points B and CVg 1 0 dc 48Rg 1 1a 1uXfmr 1a 2 0 3 transformer+PARAMS: Lm=200u n=0.1Rdum 3 0 1MegXswitch 2 0 4 3 5 CCM-DCM2+PARAMS: L=200u fs=150k n=0.1.lib switch.libC 4 0 680uR 4 0 1vd 5 0 dc 0.51 ac 1.probe.ac DEC 201 10 100k.end
+–
C R
Vg
1
2
3
45
CCM-DCM2
Rg
0
1 1aXfmr
02
3
Rdum
4
+–Vd
5
1
2 3
4
Uses Xfmr model: dependentsources plus magnetizinginductance. Must account for turnsratio in averaged switch model aswell as transformer model.
Part (b): Probe outputControl-to-output transfer function
Simulation of line-output transfer functionNetlist
DCM-CCM Gvg Simulation Problem, point AVg 1 0 dc 48 ac 1Rg 1 1a 1uXfmr 1a 2 0 3 transformer+PARAMS: Lm=200u n=0.1Rdum 3 0 1MegXswitch 2 0 4 3 5 CCM-DCM2+PARAMS: L=200u fs=150k n=0.1.lib switch.libC 4 0 680uR 4 0 1vd 5 0 dc 0.51.probe.ac DEC 201 10 100k.end
+–
C R
Vg
1
2
3
45
CCM-DCM2
Rg
0
1 1aXfmr
02
3
Rdum
4
+–Vd
5
1
2 3
4
Similar to Gvd simulation, butmove ac component out ofindependent source vd and intoindependent source Vg.
Part (c): Probe outputLine-to-output transfer function
Simulation of output impedanceNetlist
DCM-CCM Zout Simulation Problem, point AVg 1 0 dc 48Rg 1 1a 1uXfmr 1a 2 0 3 transformer+PARAMS: Lm=200u n=0.1Rdum 3 0 1MegXswitch 2 0 4 3 5 CCM-DCM2+PARAMS: L=200u fs=150k n=0.1.lib switch.libC 4 0 680uR 4 0 1Iload 0 4 ac 1vd 5 0 dc 0.51.probe.ac DEC 201 10 100k.end
Remove ac components from vd and Vg.Introduce ac current source Iload atoutput. Zout = V(4)/Iload.
+–
C R
Vg
1
2
3
45
CCM-DCM2
Rg
0
1 1aXfmr
02
3
Rdum
4
+–Vd
5
1
2 3
4 Iload
Part (d ): Probe outputOutput impedance
vg(s)
v(s)
i load(s)
referenceinput
errorsignal
+–
pulse-widthmodulatorcompensator
d(s)ve(s) vc(s)vref(s)
sensorgain
H(s)
1VM
H(s) v(s)
duty cyclevariation
Gc(s) Gvd(s)
Gvg(s)Zout(s)
ac linevariation
load currentvariation
+
–+
output voltagevariation
converter power stage
v = vref
GcGvd / VM
1 + HGcGvd / VM
+ vg
Gvg
1 + HGcGvd / VM
– i load
Zout
1 + HGcGvd / VM
Manipulate block diagram to solve for . Result isv(s)
which is of the form
v = vref1H
T1 + T
+ vg
Gvg
1 + T– i load
Zout
1 + T
with T(s) = H(s) Gc(s) Gvd(s) / VM = "loop gain"
Loop gain T(s) = products of the gains around the negativefeedback loop.
Closed-loop transfer function from to is:
which is independent of the gains in the forward path of the loop.
This result applies equally well to dc values:
v(s)vref
v(s)vref(s) vg = 0
i load = 0
= 1H(s)
T(s)1 + T(s)
If the loop gain is large in magnitude, i.e., || T || >> 1, then (1+T) ≈ T andT/(1+T) ≈ T/T = 1. The transfer function then becomes
v(s)vref(s)
≈ 1H(s)
VVref
= 1H(0)
T(0)1 + T(0)
≈ 1H(0)
fp1
fzfc
fp2
– 20 dB/decade
– 40 dB/decade
Crossoverfrequency
f
|| T ||
0 dB
–20 dB
–40 dB
20 dB
40 dB
60 dB
80 dB
T1 + T
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
T1 + T
≈ 1 for || T || >> 1T for || T || << 1
Original (open-loop) line-to-output transfer function:
Gvg(s) =v(s)vg(s) d = 0
i load = 0
With addition of negative feedback, the line-to-output transfer functionbecomes:
v(s)vg(s) vref = 0
i load = 0
=Gvg(s)
1 + T(s)
Feedback reduces the line-to-output transfer function by a factor of1
1 + T(s)
If T(s) is large in magnitude, then the line-to-output transfer functionbecomes small.
Original (open-loop) output impedance:
With addition of negative feedback, the output impedance becomes:
Feedback reduces the output impedance by a factor of
11 + T(s)
If T(s) is large in magnitude, then the output impedance is greatlyreduced in magnitude.
Zout(s) = –v(s)
i load(s) d = 0vg = 0
v(s)– i load(s) vref = 0
vg = 0
=Zout(s)
1 + T(s)
fp1
QdB
– 40 dB/decade
| T0 |dB
fz
fc fp2Crossoverfrequency
|| T ||
0 dB
–20 dB
–40 dB
20 dB
40 dB
60 dB
80 dB
–60 dB
–80 dB
f
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
QdB
– | T0 |dBfp1
fz
11 + T
– 40 dB/decade+ 40 dB/decade
+ 20 dB/decade
– 20 dB/decade
11+T(s)
≈
1T(s)
for || T || >> 1
1 for || T || << 1
fc
crossoverfrequency
0dB
–20dB
–40dB
20dB
40dB
60dB
f
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
fp1
fz
|| T ||
0˚
–90˚
–180˚
–270˚
ϕm
∠ T
∠ T|| T ||
∠T(j2πfc) = –112˚
ϕm = 180˚ – 112˚ = +68˚
Closed-loopsystem isstable if phasemargin ispositive
Phase marginaffects Q-factorof poles at fc inclosed-looptransferfunctions.
Closed-loop Q vs. ϕm
0 10 20 30 40 50 60 70 80 90
m
Q
Q = 1 0dB
Q = 0.5 –6dBm = 52˚
m = 76˚
-20dB
-15dB
-10dB
-5dB
0dB
5dB
10dB
15dB
20dB
Q-factorof closed-looppoles (inT/(1+T))
Phase margin
Closed-loop transient response vs. Q-factor
0
0.5
1
1.5
2
0 5 10 15
ct, radians
v(t)Q=10
Q=50
Q=4
Q=2
Q=1
Q=0.75
Q=0.5
Q=0.3
Q=0.2
Q=0.1
Q=0.05Q=0.01
+–
+
v(t)
–
vg(t)
28V
–+
compensator
Hvpulse-widthmodulator
vc
transistorgate driver
δ Gc(s)
H(s)
ve
errorsignal
sensorgain
iload
L50µH
C500µF
R3Ω
fs = 100kHz
VM = 4V vref
5V
0dB
–20dB
–40dB
20dB
40dB
f
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
|| Tu ||
0˚
–90˚
–180˚
–270˚
∠ Tu
|| Tu || ∠ Tu
Tu0 2.33 ⇒ 7.4dB
f01kHz
0˚ 10– 12Q f0 = 900Hz
101
2Q f0 = 1.1kHz
Q0 = 9.5 ⇒ 19.5dB
– 40 dB/decadeWith Gc = 1, theloop gain is
Tu(s) = Tu01
1 + sQ0ω0
+ sω0
2
Tu0 = H VD VM
= 2.33 ⇒ 7.4dB
fc = 1.8kHz, ϕm = 5˚
• Obtain a crossoverfrequency of 5kHz,with phase marginof 52˚
• Tu has phase ofapproximately -180˚at 5kHz, hence lead(PD) compensatoris needed toincrease phasemargin
• Lead compensator should have phase of +52˚ at 5kHz
• Tu has magnitude of -20.6dB at 5kHz
• Lead compensator gain should have magnitude of +20.6dB at 5kHz
fc= fz fp0dB
–20dB
–40dB
20dB
40dB
f
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
|| Gc ||
∠ Gc
|| Gc || ∠ Gc
Gc0
fz
0˚
fpGc0
fp
fz
90˚
0˚
–90˚
–180˚
fz/10fp/10 10fz
0dB
–20dB
–40dB
20dB
40dB
f
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
|| T ||
0˚
–90˚
–180˚
–270˚
∠ T
|| T || ∠ TT0 = 8.6 ⇒ 18.7dB
f01kHz
0˚
Q0 = 9.5 ⇒ 19.5dB
fz
fp
1.7kHz
14kHz
fc5kHz
170Hz
1.1kHz
1.4kHz
900Hz
17kHz
ϕm=52˚
T(s) = Tu0 Gc0
1 + sωz
1 + sωp
1 + sQ0ω0
+ sω0
2
• Good phasemargin
• Widebandwidth
• Low-frequencyloop gain islow — hencenot muchrejection ofdisturbances
0dB
–20dB
–40dB
20dB
40dB
f
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
|| T || T0 = 8.6 ⇒ 18.7dB
f0
Q0 = 9.5 ⇒ 19.5dB
fz
fp
fc
Q0
1 / T0 = 0.12 ⇒ – 18.7dB1
1 + T
• need morelow-frequencyloop gain
• hence, addinverted zero(PID controller)
0dB
–20dB
–40dB
20dB
40dB
f
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
|| Gc ||
∠ Gc
|| Gc || ∠ Gc
Gcmfz
– 90˚
fp
90˚
0˚
–90˚
–180˚
fz/10
fp/10
10fz
fL
fc
fL/10
10fL
90˚/dec
45˚/dec – 45˚/dec
Gc(s) = Gcm
1 + sωz
1 +ωLs
1 + sωp
• add invertedzero to PDcompensator,withoutchanging dcgain or cornerfrequencies
• choose fL to befc/10, so thatphase marginis unchanged
f
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
|| T ||
f0fz
fp
fc
Q011 + T
fL
Q0
0dB
–20dB
–40dB
20dB
40dB
60dB
–60dB
–80dB
DTu0Gcm
f
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
fzfc
fL
vvg
open-loop || Gvg ||
closed-loopGvg
1 + T
–40dB
–60dB
–80dB
–20dB
0dB
20dB
–100dB
f0
Q0Gvg(0) = D
– 40dB/dec
20dB/dec
G2(s) vx(s) = v(s)+–ve(s)vref(s)
H(s)
+–
Z1(s)
Z2(s)
A
+
–
vx(s)G1(s) ve(s)
T(s)
Block 1 Block 2
Objective: experimentally determine loop gain T(s), by makingmeasurements at point A
Correct result isT(s) = G1(s)
Z2(s)Z1(s) + Z2(s)
G2(s) H(s)
G2(s) vx(s) = v(s)+–ve(s)vref(s)
H(s)
+–
Z1(s)
Z2(s)
+
–
vx(s)G1(s) ve(s)
Block 1 Block 2
–
+
vy(s)
vz
dc bias
VCC
0
Tm(s)
Tm(s) =vy(s)vx(s) vref = 0
vg = 0
measured gain is
Tm(s) = G1(s) G2(s) H(s)
Tm(s) ≈ T(s) provided that Z2 >> Z1
–
+
G2(s) vx(s) = v(s)+–ve(s)vref(s)
H(s)
+–
Z2(s)G1(s) ve(s)
Block 1 Block 2
vy(s)
0
Tv(s)
Z1(s)+
–
vx(s)
i(s)Zs(s)
– +vz
Ac injection source vz is connectedbetween blocks 1 and 2
Dc bias is determined by biasingcircuits of the system itself
Injection source does modify loadingof block 2 on block 1
(i) Z1(s) << Z2(s) , and
(ii) T(s) >>Z1(s)Z2(s)
Tv(s) ≈ T(s) provided
G2(s) vx(s) = v(s)+–ve(s)vref(s)
H(s)
+–
Z2(s)G1(s) ve(s)
Block 1 Block 2
0
Ti(s)
Z1(s)i xi y
i z
Zs(s)
Ti(s) =i y(s)
i x(s) vref = 0
vg = 0
(i) Z2(s) << Z1(s) , and
(ii) T(s) >>Z2(s)Z1(s)
Now require:21
345
CC
M-D
CM
1
+–
+
–
+–
C2
50 µH
11 kΩ500 µF
Vg
28 V
L
CR
vref
5 V
+12 V
LM324
R1
R2
R3 C3
R4
85 kΩ
1.1 nF2.7 nF
47 kΩ
120 kΩ
vz
–vyvx
Epwm
VM = 4 V
value = LIMIT(0.25 vx, 0.1, 0.9)
+
v
–
iLOAD1 2 3
4
5678
.nodeset v(3)=15 v(5)=5 v(6)=4.144 v(8)=0.536
XswitchL = 50 µΗfs = 100 kΗz
Example: voltageinjection aftererror amplifier
PSPICE issues
Divergence!
1. Use.nodeset
to improveconvergence
2. Limit maximumand minimum dutycycles
Buck voltage regulator, closed-loop
.param R=10
.param L=50uH fs=100KHz
.step PARAM R LIST 3,10,25
.ac dec 101 5 50KHz
.nodeset v(3)=15 v(5)=5 v(6)=4.144 v(8)=0.536
.lib switch.lib
.lib nom.lib
Vg 1 0 28V
Xswitch 1 2 2 0 8 CCM-DCM1 PARAMS: L=L fs=fs
L1 2 3 L
C1 3 0 500uF
Rload 3 0 R
Vcc p 0 12V
Vref ref 0 5V
Xopamp ref 5 p 0 6 LM324
R1 3 4 11K
R2 4 5 85K
C2 4 5 1.1nF
R4 5 0 47K
R3 6 6x 120K
C3 6x 5 2.7nF
Vz 6 7 dc 2 ac 1
Epwm 8 0 value=LIMIT(V(7)*0.25,0.1,0.9)
.probe
.end
Plotting the loop gain viainjection vz
Use PROBE to plot vy/vx
Loop gain is plotted at threevalues of load resistance
File included on website alsoplots transient response
If .nodeset is omitted,PSPICE diverges
f
0˚
–90˚
–180˚
|| T || ∠ T
–20 dB
–40 dB
0 dB
20 dB
40 dB
5 Hz 50 Hz 5 kHz 50 kHz500 Hz
60 dB
R = 3 Ω
|| T ||
∠ T
R = 25 Ω
R = 3 ΩR = 25 Ω
ϕm = 55˚ ϕm = 47˚
fc = 5.3 kHzfc = 390 Hz
• Results at full load(nominal designpoint, R = 3 Ω) areclose to designgoals
• Very differentresults at light load(in DCM atR = 25 Ω)!
• As load current isreduced: Q at firstincreases becauseof reduceddamping. Then Qdecreases in DCM
f
|| Gvg ||
–60 dB
–80 dB
0 dB
20 dB
5 Hz 50 Hz 5 kHz 50 kHz500 Hz
R = 3 Ω
R = 25 Ω
–40 dB
–20 dB
Open loop, d(t) = constant
Closed loop
0 0.2 ms 0.4 ms 0.6 ms 0.8 ms 1.0 ms 1.2 ms 1.4 ms 1.6 ms 1.8 ms 2.0 ms
0 0.2 ms 0.4 ms 0.6 ms 0.8 ms 1.0 ms 1.2 ms 1.4 ms 1.6 ms 1.8 ms 2.0 ms
0
2 A
4 A
6 A
14 V
15 V
16 V
v
iLOAD
t
Closed loop
Open loopd(t) = constant
PSPICE-generated transient response, same closed-loop buck example
A typical design approach:
1. Engineer designs switching regulator that meets specifications(stability, transient response, output impedance, etc.). Inperforming this design, a basic converter model is employed, suchas the one below:
+–
L
C R
+–1 : D
+
–
Converter model
Vg
Ig
(no input filter)
(buckconverterexample)
2. Later, the problem of conducted EMI is addressed. An input filter isadded, that attenuates harmonics sufficiently to meet regulations.
3. A new problem arises: the controller no longer meets dynamicresponse specifications. The controller may even become unstable.
Reason: input filter changes converter transfer functions
+–
L
C R
+–1 : D
+
–
Converter model
Vg
Ig
Lf
Input filter
Cf
Converterac model ismodified byinput filter
f
|| Gvd || ∠ Gvd
0˚
– 360˚
– 540˚
0 dB
– 10 dB
20 dB
30 dB
100 Hz
40 dB
1 kHz 10 kHz
– 180˚
10 dB
|| Gvd ||
∠ Gvd
Effect of L-C inputfilter on control-to-output transferfunction Gvd (s),buck converterexample.
Dashed lines:original magnitudeand phase
Solid lines: withaddition of inputfilter
Gvd(s) = Gvd(s)Zo(s) = 0
1 +Zo(s)ZN(s)
1 +Zo(s)ZD(s)
Gvd(s)Zo(s) = 0 is the original transfer function, before addition of input filter
ZD(s) = Zi(s)(s) = 0
is the converter input impedance, with set to zero
ZN(s) = Zi(s)(s) 0 is the converter input impedance, with the output
nulled to zero
(Proof using Middlebrook's extra element theorem)
Input filter design criteria for basic converters
Converter ZN(s) ZD(s) Ze(s)
Buck
Boost
Buck–boost
– RD2 R
D2
1 + s LR + s2LC
1 + sRC
sLD2
– D′2R 1 – sLD′2R D′2R
1 + s LD′2R
+ s2 LCD′2
1 + sRC
sL
– D′2RD2 1 – sDL
D′2RD′2RD2
1 + s LD′2R
+ s2 LCD′2
1 + sRC
sLD2
Gvd(s) = Gvd(s)Zo(s) = 0
1 +Zo(s)ZN(s)
1 +Zo(s)ZD(s)
The correction factor
Zo ZN , and
Zo ZD
1 +Zo(s)ZN(s)
1 +Zo(s)ZD(s)
shows how the input filter modifies thetransfer function Gvd (s).
The correction factor has a magnitude of approximately unity providedthat the following inequalities are satisfied:
These provide design criteria, which are relatively easy to apply.
+–
C R
+
v
–
L i1
2Vg
Lf
Cf
Input filter Converter
30 V
330 µH
470 µF
100 µH
100 µF 3 Ω
D = 0.5
+–
L
C R
+–1 : D
+
–
Converter model
Vg
Ig
Lf
Input filter
Cf
Zo(s) Zi(s)
330 µH
470 µF
100 µH
100 µF 3 Ω
Buck converterwith input filter
Small-signal model
L
C R
1 : D
+
–
ZD(s)
ZD(s) = 1D2 sL + R || 1
sC
100 Hz 1 kHz 10 kHz
40 dBΩ
0 dBΩ
20 dBΩ || ZN ||
|| ZD ||
f
RD2 = 12 Ω
f1 = 12πRC
530 Hz
fo = 12π LC
1.59 kHz
Q = R CL =
fof1
= 3 → 9.5 dB
1ωD2C
ωLD2
10 dBΩ
30 dBΩ
R0/D2
L
C R
+–1 : D
+
–
Vg
I
0
0ZN(s)
+
–
s 0test test
+
–
ZN(s) = test(s)
test(s)0
test(s) = I (s)
test(s) = –Vg (s)
D
ZN(s) =–
Vg (s)D
I (s)= – R
D2
Solution: Hence,
Lf
Cf
Zo(s)
Zo(s) = sL f || 1sC f
100 Hz 1 kHz
40 dBΩ
0 dBΩ
– 20 dBΩ
20 dBΩ
f
|| Zo ||
– 10 dBΩ
10 dBΩ
30 dBΩ
1ωC f
ωL f
ff = 12π L fC f
= 400 Hz
Q f → ∞
R0 f =L f
C f= 0.84 Ω
No resistance, hence poles are undamped (infinite Q-factor).
In practice, losses limit Q-factor; nonetheless, Qf may be very large.
100 Hz 1 kHz 10 kHz
40 dBΩ
0 dBΩ
– 20 dBΩ
20 dBΩ || ZN ||
|| ZD ||
f
|| Zo ||
ωL f 1ωC f
12 Ω
Q f → ∞
1ωD2C
fo = 1.59 kHz
f1 = 530 Hz
Q = 3
ωLD2
R0f
10 dBΩ
30 dBΩ
– 10 dBΩ ff = 400 Hz
R0/D2
Zo ZN , and
Zo ZD
Can meetinequalitieseverywhereexcept atresonantfrequency ff.
Need to dampinput filter!
f
0˚
– 360˚
0 dB
– 10 dB
100 Hz 1 kHz 10 kHz
– 180˚
10 dB
∠1 +
Zo
ZN
1 +Zo
ZD
1 +Zo
ZN
1 +Zo
ZD
f
|| Gvd || ∠ Gvd
0˚
– 360˚
– 540˚
0 dB
– 10 dB
20 dB
30 dB
100 Hz
40 dB
1 kHz 10 kHz
– 180˚
10 dB
|| Gvd ||
∠ Gvd
Dashed lines: noinput filter
Solid lines:including effect ofinput filter
1ωC f
ωL fff
Rf
R0f
Cb
Lf
Cf
Rf
|| Zo ||, with large Cb
100 Hz 1 kHz 10 kHz
40 dBΩ
0 dBΩ
– 20 dBΩ
20 dBΩ || ZN ||
|| ZD ||
f
|| Zo ||
ωL f 1ωC f
12 Ω
1ωD2C
fo = 1.59 kHzf1 = 530 Hz
Q = 3
ωLD2
R0f
10 dBΩ
30 dBΩ
– 10 dBΩ ff = 400 Hz
Rf = 1 Ω
R0/D2
f
|| Gvd || ∠ Gvd
0˚0 dB
– 10 dB
20 dB
30 dB
100 Hz
40 dB
1 kHz 10 kHz– 180˚
10 dB
|| Gvd ||
∠ Gvd
– 90˚
Dashed lines: noinput filter
Solid lines:including effect ofinput filter
+–v1
+
v2
–
Cb
Rf
Cf
Lf
+–v1
+
v2
–
LbRf
Cf
Lf
+–v1
+
v2
–
Lb
Rf
Cf
Lf
Rf –Lb Parallel Damping
Rf –Lb Series DampingRf –Cb Parallel Damping
• Size of Cb or Lb can becomevery large
• Need to optimize design
Basic results
with
R0 = LC
• Does not degrade HF attenuation• No limit on || Z ||mm
• Cd is typically larger than C
+–
L
Cv1
+
v2
–
Cd
R
Qopt = RR0
=2 + n 4 + 3n
2n2 4 + n
Zmm
R0=
2 2 + nn
n =Cd
C
0.1
1
10
100
0.1 1 10
n =CdC
Zo mmRo
• Cascade connection of multiple L-C filter sections can achieve agiven high-frequency attenuation with much smaller volume andweight
• Need to damp each section of the filter
• One approach: add new filter section to an existing filter, using newdesign criteria
• Stagger-tuning of filter sections
+–
Existingfilter
Additionalfilter
sectionZoZa
testgZi1
+
test
–
How the additional filter section changes the output impedance of theexisting filter:
modified Zo(s) = Zo(s)Za(s) = 0
1 +Za(s)
ZN1(s)
1 +Za(s)ZD1(s)
ZN1(s) = Zi1(s)test(s) 0
ZD1(s) = Zi1(s)test(s) = 0
+–
Existingfilter
Additionalfilter
sectionZoZa
testgZi1
+
test
–
Za ZN1 and
Za ZD1
The presence of the additional filter section does not substantiallyalter the output impedance Zo of the existing filter provided that
ZN1(s) = Zi1(s)test(s) 0
ZD1(s) = Zi1(s)test(s) = 0
(with filter output port short-circuited)
(with filter output port open-circuited)
+–g
L1
n1L1R1
C1
L2
n2L2R2
C2
Section 2 Section 1
Zo
Requirements: For the samebuck converter example,achieve the following:
• 80 dB of attenuation at 250 kHz
• Section 1 to satisfy Zoimpedance inequalities asbefore:
100 Hz 1 kHz 10 kHz
40 dBΩ
0 dBΩ
20 dBΩ || ZN ||
|| ZD ||
f
RD2 = 12 Ω
f1 = 12πRC
530 Hz
fo = 12π LC
1.59 kHz
Q = R CL =
fof1
= 3 → 9.5 dB
1ωD2C
ωLD2
10 dBΩ
30 dBΩ
R0/D2
To avoid disrupting the output impedance Zo of section 1, section 2should satisfy the following inequalities:
+–g
L1
n1L1R1
C1
L2
n2L2R2
C2
Section 2 Section 1
Za testZi1
+
test
–
Za ZN1 = Zi1 output shorted= R1 + sn1L 1 ||sL 1
Za ZD1 = Zi1 output open-circuited= 1
sC1+ R1 + sn1L 1 ||sL 1
1 kHz 10 kHz 100 kHz 1 MHz
–20 dBΩ
0 dBΩ
20 dBΩ
–90˚
–45˚
0˚
45˚
90˚
|| ZN1 ||
|| ZD1 ||
∠ZN1
|| Za ||
∠Za
∠ZD1
-20 dBΩ
-10 dBΩ
0 dBΩ
10 dBΩ
20 dBΩ
1 kHz 10 kHz 100 kHz
Section 1alone
Cascadedsections 1 and 2
30 dBΩ
|| ZN |||| ZD ||
fo
1 kHz 10 kHz 100 kHz 1 MHz
-120 dB
-100 dB
-80 dB
-60 dB
-40 dB
-20 dB
0 dB
20 dB
|| H ||
– 80 dBat 250 kHz
f
+–g
Cb
Rf
Cf
Lf
330 µH
470 µF
1200 µF
0.67 Ω
+–g
L1
n1L1R1
C1
L2
n2L2R2
C2
6.9 µF
31.2 µH
15.6 µH1.9 Ω0.65 Ω 2.9 µH
5.8 µH
11.7 µF
+–
Buck converter
Current-programmed controller
Rvg(t)
is(t)
+
v(t)
–
iL(t)
Q1
L
CD1
+
–
Analogcomparator
Latch
Ts0
S
R
Q
Clock
is(t)
Rf
Measureswitch
current
is(t)Rf
Controlinput
ic(t)Rf
–+
vref
v(t)Compensator
Conventional output voltage controller
Switchcurrentis(t)
Control signalic(t)
m1
t0 dTs Ts
on offTransistor
status:
Clock turnstransistor on
Comparator turnstransistor off
The peak transistor currentreplaces the duty cycle as theconverter control input.
iL(t) Ts= ic(t)
• Neglects switching ripple and artificial ramp (slope compensation)
• Yields physical insight and simple first-order model
• Accurate when converter operates well into CCM (so that switchingripple is small) and when the magnitude of the artificial ramp is nottoo large
• Well-accepted by practicing engineers
• Resulting small-signal relation:
iL(s) ≈ ic(s)
+–
L
C R
+
v(t)
–
vg(t)
iL(t)
+
v2(t)
–
i1(t) i2(t)
Switch network
+
v1(t)
–
v2(t) Ts= d(t) v1(t) Ts
i1(t) Ts= d(t) i2(t) Ts
Averaged terminal waveforms,CCM:
The simple approximation:
i2(t) Ts≈ ic(t) Ts
Buck converter example
CPM averaged switch model
+–
L
C R
+
⟨v(t)⟩Ts
–
⟨vg(t)⟩Ts
⟨iL(t)⟩Ts
+
⟨v2(t)⟩Ts
–
⟨i1(t)⟩Ts⟨i2(t)⟩Ts
Averaged switch network
+
⟨v1(t)⟩Ts
–
⟨ic(t)⟩Ts
⟨ p(t)⟩Ts
Eliminate duty cycle:
i1(t) Ts= d(t) ic(t) Ts
=v2(t) Ts
v1(t) Ts
ic(t) Tsi1(t) Ts
v1(t) Ts= ic(t) Ts
v2(t) Ts= p(t)
Ts
• Output port is a current source
• Input port is a dependent power sink
+–
L
C R
+
–
+
–
Switch network small-signal ac model
+
–
vg –V1
I1
i1 i2
i cV2
V1i c
v1 v2Ic
V1
v2 v
i1(t) = ic(t)V2
V1
+ v2(t)Ic
V1
– v1(t)I1
V1
+–
L
C R
+
–
vg ic v– D2
RDR
vic D 1 + sLR
ig iL
Gvc(s) =v(s)ic(s)
vg = 0
= R || 1sC
Gvg(s) =v(s)vg(s)
i c = 0
= 0
+–
ig
vg RCr1f1(s) i c g1 v g2 vg f2(s) i c r2 v
+
–
Converter g1 f1 r1 g2 f2 r2
BuckDR D 1 + sL
R– R
D2 0 1 ∞
Boost 0 1 ∞1
D'R D' 1 – sLD' 2R R
Buck-boost – DR D 1 + sL
D'R– D'R
D2 – D2
D'R– D' 1 – sDL
D' 2RRD
Simulation of Current Mode Controllers
21
345
CC
M-D
CM
1
+–
+–
35 µH
100 µF
Vg
12 V
L
C R
vc
+
v
–
iLOAD
CPM
control current 1 2
d
+–
+–
+–
iL RL1 2 3 4
d
Rf iL v(1)–v(3) v(3)
0.05 Ω
10 Ω
Rf = 1 Ωfs = 200 kHzL = 35 µΗVa = 0.6 V
Xcpm
Xswitch
fs = 200 kHzL = 35 µΗ
EiE1 E2
• Develop a modelof the current-programmedcontroller, whichcan be combinedwith existing CCM-DCM averagedswitch models
• Controller modeloutputs a dutycycle, in responseto control input ic(or vc ) and thesensed convertervoltages andcurrents
Averaged controller waveforms
t
iL(t)
ipk
vL(t)
0
v1(t) Ts
ic– ma
– m2
m1
t
d2Ts=(1 – d)Ts
v2(t) Ts–
Ts
dTst
iL(t)
0
ipk
vL(t)
0
v1(t) Ts
v2(t) Ts
ic– ma
– m2m1
t–
Ts
dTs d2Ts
CCM DCM
Equations
i pk = ic – madTsm1 =v1(t) Ts
L m2 =v2(t) Ts
L
iL(t)Ts
= d i pk –m1dTs
2+ d2 i pk –
m2d2Ts
2
d =2ic(d + d2) – 2 iL(t)
Ts– m2d 2
2Ts
2ma(d + d2)Ts + m1dTs
d2 = 1 – d
d2 =i pk
m2Ts
Need to write large-signal equations of controller, in a form that leadsto convergence of simulator and that works for both CCM and DCM
Basic equations: (CCM)
(DCM)
Average inductor current: d2 = MIN 1 – d,i pk
m2Ts
(CCM and DCM)
Artificial ramp amplitude:Va = maTsR f
Substitute and solve (partially) for d:
CPM controller subcircuit model
.subckt CPM control current 1 2 d+params: L=100e-6 fs=1e5 Va=0.5 Rf=1* generate d2 for CCM or DCMEd2 d2 0 table+ MIN(L*fs*(v(control)-va*v(d))/Rf/(v(2)),1-v(d)) (0,0)(1,1)* generate inductor current slopes, see Eqs.(B.24) and (B.26)Em1 m1 0 value=Rf*v(1)/L/fsEm2 m2 0 value=Rf*v(2)/L/fs* compute duty cycle d, see Eq.(B.32)Eduty d 0 table+ 2*(v(control)*(v(d)+v(d2))-v(current)-v(m2)*v(d2)*v(d2)/2)+ /(v(m1)*v(d)+2*va*(v(d)+v(d2))) (0.01,0.01) (0.99,0.99).ends
CPM
control current 1 2
d
Rf iL(t)Ts
v1(t) Tsv2(t) Ts
vc(t) TsInputs:
Output: duty cycle d
CPM buck example
21
345
CC
M-D
CM
1
+–
+–
35 H
100 F
Vg
12 V
L
C R
vc
+
v
–
iLOAD
CPM
control current 1 2
d
+–
+–
+–
iL RL1 2 3 4
d
Rf iL v(1)–v(3) v(3)
0.05
10
Rf = 1fs = 200 kHzL = 35Va = 0.6 V
Xcpm
Xswitch
fs = 200 kHzL = 35
EiE1 E2
CPM buck converter.param Va=0.6.param fs=200KHz.param L=35uH.ac DEC 101 10 100KHziout 0 4 ac 0.lib switch.libVg 1 0 12V ac 0Xswitch 1 2 2 0 5 CCM-DCM1+PARAMS: L=L fs=fsL1 2 3 LRL1 3 4 0.05C1 4 0 100uFRload 4 0 10Xcpm ctr ni nm1 nm2 5 CPM+PARAMS: L=L fs=fs va=Va Rf=1Ei ni 0 value=i(L1)Em1 nm1 0 value=V(1)-V(3)Em2 nm2 0 value=V(3)Vic ctr 0 dc 1.4V ac 1.probe.end
Control-to-output frequency responseDuty cycle control vs current programmed control
Gvd
Gvd
f
0˚
–90˚
–180˚
G
–20 dB
–40 dB
0 dB
20 dB
40 dB
10 Hz 100 Hz 10 kHz 100 kHz1 kHz
G
–60 dB
Gvc
Gvc
In both cases:
V = 8.1 V
D = 0.676
For CPM:
Vc = 1.4 V
Va = 0.6 V
Line-to-output frequency responseDuty cycle control vs current programmed control
|| Gvg ||
f
–20 dB
–40 dB
0 dB
20 dB
10 Hz 100 Hz 10 kHz 100 kHz1 kHz
–60 dB
–80 dB
–100 dB
Duty cycle controld(t) = constant
Current programmed modevc(t) = constant
In both cases:
V = 8.1 V
D = 0.676
For CPM:
Vc = 1.4 V
Va = 0.6 V
Output impedanceDuty cycle control vs current programmed control
|| Zout ||
f
–20 dBΩ
–40 dBΩ
0 dBΩ
20 dBΩ
10 Hz 100 Hz 10 kHz 100 kHz1 kHz
Duty cycle controld(t) = constant
Current programmed modevc(t) = constant
In both cases:
V = 8.1 V
D = 0.676
For CPM:
Vc = 1.4 V
Va = 0.6 V
Example: comparison of current-mode controlled and duty-cycle controlled regulators
Design specs:
• Output voltage regulated at V = 5 V• Output power: 2.5 W (R = 10 Ω) to 50 W (R = 0.5 Ω)
• Both current-mode and duty-cycle controlled regulators have the voltage-loop compensator designed for the cross-over frequency of 25 kHz and the phase margin of 60o (at the load of R = 0.5 Ω)
!
!
µ Ω
µ
Open-loop responses and compensators
+
+
+=
p
z
I
mdcds
s
sGsG
ω
ωω
1
11
)(
kHz2=If
kHz6.5=zf
kHz118=pf
+=
sGsG Ic
mccc
ω1)(
Hz235=Icf
Duty-cycle controlled regulator Current-mode controlled regulator
PID compensator: PI compensator:
Open-loop control-to-output response
21
1
1)(
++
=
oo
odvcdss
Q
GsG
ωω
5.2kHz,8 == Qfo
+
+=
21
11
1)(
ωωss
GsG ocvcc
kHz51kHz,3.4 21 == ff
Duty-cycle controlled regulator Current-mode controlled regulator
Compensators
Summary of results obtained by simulation
kHz6.25=cfo69=mϕ o68=mϕ
kHz2.24=cf
Duty-cycle controlled regulator
Current-mode controlled regulator
Load
Ω= 5.0R
Full load, CCM
Ω= 2R
Reduced load, but still CCM
Ω=10R
Light load, DCM
kHz26=cfo63=mϕ
kHz8.1=cfo73=mϕ
o68=mϕkHz2.24=cf
o73=mϕkHz6.6=cf
• Both approaches maintain good phase margins at all loads and approximately the same bandwidth as long as the converter is in CCM
• Bandwidth is severely reduced at light loads when the converter operates in DCM. This effect is more severe for duty-cycle control than for current-mode control.
Resources
For further reading:Erickson and Maksimovic, Fundamentals of Power Electronics,
second edition, Kluwer Academic Publishers, 2001, ISBN 0-7923-7270-0.
Website:http://ece.colorado.edu/~pwrelect/book/Includes downloadable PSPICE libraries
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