Transcript
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EE 215E
u a ar amar ,University of California, Los Angeles
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References
F. M. Gardner, Phaselock Techniques, Wiley Interscience
F. M. Gardner, Charge Pump Phase Locked Loops, IEEETransactions on Communications, vol. COM-28, no. 11, Nov
, .
J. Hein, J. Scott, z-Domain Model for Discrete-Time PLLsIEEE Trans on Circuits and Systems, Nov 1988
- -. , ,frequency synthesizers allowing straightforward noise
analysis, IEEE JSSC, August 2002, pp. 1028-1038
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Lec t u re Topic s
Basic operation
Type I vs. Type II PLLs
Charge pump PLL
Continuous time model ,
Control voltage ripple
Linear, time-variant charge pump PLL models
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Lec t u re Topic s
Basic operation
Type I vs. Type II PLLs
Charge pump PLL
Continuous time model ,
Control voltage ripple
Linear, time-variant charge pump PLL models
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Basic Operat ion
Negative feedback loop
In steady state, Out and Ref have a well-defined phase
relationship E.g., they have the same frequency and same phase
Many applications
Frequency synthesis
Synchronization of clocks
Fre uenc discrimination
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Vol t age Cont ro l Osc i l la tor
Ring/LC, differential/single-ended oscillators
More on VCOs later
VCO
KVCO
,
( ) ( )
VCO VCO ctrl
t
VCO VCO ctrl
F t K V t rad s
t K V d radians
==
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Frequenc y Div ider
Synchronous or asynchronous implementations
Many implementations
a c , ynam c og c, curren mo e og c
1( ) ( )div VCO t t =
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Phase Com parat or /Det ec t or
err
err ref div =
err0
Generates a voltage proportional to phase difference of
inputs
A PD gain can be defined, on average:
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( )0( ) ( ) ( )avg PD ref div V t K t t
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Loop Fi l t er, F(s)
Many implementations
Passive, active, sampled
Filter classification Based on number of integrators in F(s)
ype : no n egra ors
Type II: one integrator
Based on number of poles in F(s) or er, or er, or er, e c.
21: 1s
T e I F s F s +
= =1
2 2
11 1
: ( ) , ( ) .(1 )
ss s
Type II F s F s s s s
++ +
= =+
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A Sim ple PLL Model
( )ref t K F s VCOK
t
( )err t0
( )avgV t ( )ctrlV t
1N
s
( )div t
Negative feedback loop tries to force err(t) = 0 In steady state i.e. in lock FVCO = N*Fref
More accurate models are required
Many components have discrete time operation
Reference: See Floyd Gardners Phaselock Techniques, Wiley
Interscience for more details
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Lec t u re Topic s
Basic operation
Type I vs. Type II PLLs
Charge pump PLL
Continuous time model ,
Control voltage ripple
Linear, time-variant charge pump PLL models
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Ex am ple Type I PLL
( )ref t
1
2CPI
( )F s VCO
K
s( )VCO t
t
( )err t( )CTRLV t( )avgI t
Example Type I loop filter
N
1.F =
Non-zero values of Vctrl require that err0
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Type I , 1st Order PLL
( )ref t K F s VCOK
t
( )err t0
( ) 1F s =( )avgV t ( )ctrlV t
1N
s
( )div t
( ) 1VCOs N
Follows from standard linear systems theory that
,( ) 1
PD VCO
ref s s K N +
1s N
It has 1st order settling behavior
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,( ) 1
PD VCO
ref
ra ss s K N
= =+
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Type I , 1st Order PLL
( )ref t K F s VCOK
t
( )err t0
( ) 1F s =( )avgV t ( )ctrlV t
1N
s
( )div t
Ktinitial
A frequency step, initialwill result in
errK
=
. . err
The filter can not remember the required Vctrlvalue
So, Vavg 0 is required
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Not good for many applications
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Ot her Type I PLL Problem s
Ref
Vavg
err
Gain > 0Gain < 0
PLL may go out of lock for large err
0
Cycle slipping
Suppose Ref and Div have a frequency difference errcan change in large jumps
Remember: the frequency error accumulates as err Phase detector gain changes frequently
Could be +ve or ve So, frequency of Div could show wild variations
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Problems due to an inability to detect frequency error
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Ex am ple Type I I PLL : Charge Pum p PLL
ICP
Ref
VctrlVCO
UpUp
Div
ICP
R
C2
nDn
V
difference into a capacitor, C2
The capacitor, C2, stores/remembers Vctrl
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, err
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Lec t u re Topic s
Component description
Type I vs. Type II PLLs
Type II, charge pump PLL
Continuous time model
,
Control voltage ripple
Linear, time-variant charge pump PLL model
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Phase Frequenc y Det ec t or
2
Up and Dn together contain the phase error information
Their time difference is ro ortional to the hase error
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Phase Frequenc y Det ec t or
2
err
err ref div =
Up and Dn together contain the phase error information
Their time difference is ro ortional to the hase error
A proportional voltage or current can be generated forF(s)
A charge pump is best suited for this purpose
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Charge Pum p Int eger -N PLLs: LTI Model
( )ref t
1
2CPI
( )F s VCO
K
s( )VCO t
t
( )err t( )CTRLV t( )avgI t
N
refT refT
errAssumption: CP
produces an average
current durin each
err
av
CPI
CPI
reference period.
Linear, time-invariant model Ignores the non-linearity of the PFD 2
err err CP CP
ref
I IT
=
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Reasonable approximation for low bandwidth PLLs
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Com m on Charge Pum p Int eger-N PLLs
( )ref t
1
2CPI
( )F s VCO
K
s( )VCO t
t
( )err t( )CTRLV t( )avgI t
Loop filter is usually of Type II
N
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Com m on Charge Pum p Int eger-N PLLs
( )ref t
1
2CPI
( )F s VCO
K
s( )VCO t
t
( )err t( )CTRLV t( )avgI t
Loop filter is usually of Type II
N
21( )s
F s R + =
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2
2 2,RC
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Com m on Charge Pum p Int eger-N PLLs
( )ref t
1
2CPI
( )F s VCO
K
s( )VCO t
t
( )err t( )CTRLV t( )avgI t
Loop filter is usually of Type II
N
21( )s
F s R + =
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2
2 2,RC
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Com m on Charge Pum p Int eger-N PLLs
( )ref t
1
2CPI
( )F s VCO
K
s( )VCO t
t
( )err t( )CTRLV t( )avgI t
Loop filter is usually of Type II
N
21( )s
F s R + =
21 1( )b s
F s R + =
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2 2 p
2 2,RC 2 1 2 21 1 2
1 , pC C Cb RC C C b
+ =+
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Com m on Charge Pum p PLLs: St abi l i t y
20log10|T(j)|
( )
( )2
22
1
( ) ,1 p
K s
T s s s
+
= +
1 1
,2
tan tan
CP VCO Kb N
PM K K b
=
K1/2
1/
p = b/
2
0 dB
Unity gain freq.
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Com m on Charge Pum p PLLs: St abi l i t y
20log10|T j) Angle T j)
90
( )
( )2
22
1
( ) ,1 p
K s
T s s s
+
= +PM
1 1
,2
tan tan
CP VCO Kb N
PM K K b
=
K1/2
1/
p = b/
2
0 dB180
Unity gain freq.
The zero provides phase margin (PM)
Large K2 values give better PM
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Com m on Charge Pum p PLLs: St abi l i t y
20log10|T(j)| Angle{T(j)}
90
Decreasing
b
( )
( )2
22
1
( ) ,1 p
K s
T s s s
+
= +
K1/2 1/
p= b/
2
0 dB180
1 1
,2
tan tan
CP VCO Kb N
PM K K b
=
Decreasing b
The zero provides phase margin
Large K2 values give better PM
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Large b gives better PM: typically, b > 16 is used
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Com m on CP PLLs: Closed LoopResponse
21N s+2 3
2 2 2
,1
1where ,
p
CP VCO
ss s K s K
b I K RK
=+ + +
=
-
Magnitude response ofA(s) rises at the doublet
Doublet slows down settling response
Decreasing b or K2 increases peaking
Frequency where peaking occurs is not necessarily K
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Com m on CP PLLs : Closed Loop Response
21N s+2 3
2 2 2
,1
1where ,
p
CP VCO
ss s K s K
b I K RK
=+ + +
=
-
Magnitude response ofA(s) rises at the doublet
Doublet slows down settling response
Frequency where peaking occurs is not necessarily K
F. M. Gardner, Char e Pum Phase Locked Loo s, IEEE Transactions
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on Communications, vol. COM-28, no. 11, Nov 1980, pp. 18491858.
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Sim ple Design Proc edure
Given quantities Fref, N, KVCO (Hz/V), minimum phase margin, PMrequired required closed loop bandwidth, fBW(Hz)
1 1tan2
requiredb bPM
Calculate b:
2b N b
Calculate ICP, R, C2 such that
2an1 2
CP
VCO BW b K f= =
Calculate C1 such that
211C b=
Note: Multiple choices for (ICP, R, C2) are possible
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,
More later
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Int eger -N PLL Design Issues
Sophisticated filter design is possible
Implementation concerns
Not much room to play with
Mainly choose the components of a chosen filter structure
Good example: Michael Perrotts PLL Design tool
The challenging problems in PLL design are usually
Dealing with component variability
How much phase margin is enough phase margin ?
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2nd Order Vs 3rd Order Type I I CP PLLs
2nd order PLL is a special case of the 3rd order PLL b = infinit
However, analysis has been application specific
Digital, wired communication analyses focus on 2nd order PLL
( )1 2tan
1 2
PM K
N s
=
+
2 20 0( ) 1 2
1 1where ,CP VCO
A s s s
I KRC
= + +
= =
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2
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2nd Order Vs 3rd Order Type I I CP PLLs
2nd order PLL is a special case of the 3rd order PLL b = infinit
However, analysis has been application specific
Digital, wired communication analyses focus on 2nd order PLL
( )1 2tan
1 2
PM K
N s
=
+
20log10|A(j)| Decreasing
2 20 0( ) 1 2
1 1where ,CP VCO
A s s s
I KRC
= + +
= =
20log10|N| dBPrediction from
3rd
order PLL
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2
K1/2
0
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Cont ro l Vo l t age Ripp le
CP
VctrlVCO
Up
Up
Dn
ICPC1
R
C2
Dn
Vctrl
C1 = 0
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Cont ro l Vo l t age Ripp le
CP
VctrlVCO
Up
Up
Dn
ICPC1
R
C2
Dn
Vctrl
C1 = 0
C1 0
The ripple on Vctrl causes periodic jumps in VCO phase
S. Pamarti
Bad for both wireless and wire-line communications
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Ef fec t o f 3 rd Loop Fi l t er Pole on Ripple
po e a enua es e r pp e an s e ec s
Small b is desired for more attenuation
Recall: small b reduces phase margin
Often choose K to be the geometric mean of 1/2, and 1/p
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Lec t u re Topic s
Component description
Problems with Type I PLL Continuous time model
Charge pump PLL
Linear analysis stability, closed loop phase transfer function
Control voltage ripple
Linear, time-variant charge pump PLL models
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Prob lem s w i t h Cont inuous T im e Model
So, only samples of the VCO phase are fed back
Also causes delay in the phase feedback
The charge pump, and loop filter operation depends on the
,
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Sam pl ing i n Charge Pum p PLLs
( )0sin 2 f tn
0T
( )0sin 2 ( ) f t t +th th
Assumptions
The excess hase is small: t
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Charge Pum p Im pulse Approx im at ion
( )ref t2
refT
( )F s VCO
K
s( )VCO t
[ ]err n( )ctrlV t( )errI t[ ]ref n
[ ]err n
1N[ ]div nREFf
Charge pumps current pulses
CPI
[ ]err nCPI
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Charge Pum p Im pulse Approx im at ion
( )ref t2
refT
( )F s VCO
K
s( )VCO t
[ ]err n( )ctrlV t( )errI t[ ]ref n ITM
[ ]err n
CPI
1
N[ ]div nREFf
REFf
Charge pumps current pulses approximated as impulses
( )( ) [ ]err CP err ref n
I t I n t nT
=
= CPI
[ ]err nCPI
S. Pamarti
. , , - -
allowing straightforward noise analysis, IEEE JSSC, August 2002, pp. 1028-1038
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Link s t o t he Cont inuous-Tim e Model
( )ref t2
refT
( )F s VCO
K
s( )VCO t
( )ctrlV t( )errI tCPI1 refT
1 refT
1N
REFf
Two assumptions
Signal replicas are aggressively filtered by F(s) and the VCO
Sampling aliases are negligible
Reasonable because VCO phase does not jump sharply
ssump ons naccura e as BW ref
Same as the continuous-time model under these
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assumptions
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Bet t er Models for Charge Pum p PLLs
( )ref t2
refT
( )F s VCO
K
s( )VCO t
[ ]err n( )ctrlV t( )errI t[ ]ref n ITM
[ ]err n
CPI
1
N[ ]div nREFf
REFf
How to analyze the PLL ?
,
Approach #1: linear, discrete-time model
Inaccurate as bandwidth increases relative to fref
-
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Linear , Disc ret e-Tim e Model
2
refT
( )eqF z 1
VCOK
[ ]VCO n
[ ]err n
[ ]ref n
[ ]err n
CPI
1N[ ]div n
Replace the analog portions of the PLL with discrete time
equivalents
eq
Implicit sampling at fs = fref
Higherfs can be used: fs = m*fref, m is a +ve integer
Stability: T(z) instead ofT(s)
S. Pamarti
F. M. Gardner, Charge Pump Phase Locked Loops, IEEE Transactions on
Communications, vol. COM-28, no. 11, Nov 1980, pp. 18491858.
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Linear , Disc ret e-Tim e Model
e er pre c on o e av or an e con nuous me
model
S. Pamarti
F. M. Gardner, Charge Pump Phase Locked Loops, IEEE Transactions on
Communications, vol. COM-28, no. 11, Nov 1980, pp. 18491858.
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St ab i l i t y o f t he 2 nd order Type I I CP PLL
1
2
1ref
ref
K
< +
Overload limit: too large a Vctrlripple will put the VCO out of range Depends on the VCO implementation
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