1 Computer System Overview OS-1 Course AA 2000-2001.

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Computer System Overview

OS-1 CourseAA 2000-2001

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Operating Systems - Making computing power available to users by controlling the hardware

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Basic Elements

Processor Main Memory

referred to as real memory or primary memoryvolatile

I/O modulessecondary memory devicescommunications equipment terminals

System interconnectioncommunication among processors, memory,

and I/O modules

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Registers

Memory that is faster and smaller than main memory

Temporarily stores data during processing

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Top-level Components (Registers)

MAR - Memory Address Registeraddress for next read or write

MBR - Memory Buffer Registerdata to be written into memory receives data read from memory

I/OAR - I/O Addressspecifies a particular I/O device

I/OBR - I/O Bufferexchange of data between an I/O module

and the processor

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Computer Components:top-level view

IR

MAR

MBR

I/O AR

I/O BR

PC

CPU

Buffers

I/O Module

Memory

InstructionInstruction

Instruction

Data

Data

DataData

...

..

...

..

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Processor Registers

User-visible registersMay be referenced by machine

languageAvailable to all programs - application

programs and system programsTypes of registers

• Data • Address• Condition Code

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User-Visible Registers

Data Registerscan be assigned by the programmer

Address Registerscontain main memory address of data and

instructionsmay contain a portion of an address that is

used to calculate the complete address• index register• segment pointer• stack pointer

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User-Visible Registers

Address RegistersIndex

• involves adding an index to a base value to get an address

Segment pointer• when memory is divided into segments,

memory is referenced by a segment and an offset

Stack pointer• points to top of stack

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User-Visible Registers

Condition Codes or FlagsBits set by the processor hardware as a result

of operationsCan be accessed by a program but not

changedExamples

• positive result• negative result• zero• overflow

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Control and Status Registers

Program Counter (PC)Contains the address of an instruction to be

fetched

Instruction Register (IR)Contains the instruction most recently fetched

Program Status Word (PSW)condition codes Interrupt enable/disableSupervisor

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Instruction Execution

Processor executes instructions in a program

Instructions are fetched from memory on at a time

STARTSTART HALTHALTFetch NextInstruction

Fetch NextInstruction

ExecuteInstruction

ExecuteInstruction

Fetch Cycle Execute Cycle

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Instruction Fetch and Execute

The processor fetches the instruction from memory

Program counter (PC) holds address of the instruction to be fetched next

Program counter is incremented after each fetch

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Instruction Register

Fetched instruction is placed hereTypes of instructions

Processor-memory• transfer data between processor and memory

Processor-I/O• data transferred to or from a peripheral device

Data processing• arithmetic or logic operation on data

Control• alter sequence of execution

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3 0 2

Example of Program Execution

Memory CPU Registers CPU Registers

CPU Registers CPU Registers

CPU Registers CPU Registers

Memory

Memory Memory

Memory

Memory

300301302

940941Step 1

PCACIR

301302

940941

300

300301302

940941

300301302

940941

300301302

940941

300301302

940941

Step 3

Step 5

Step 2

Step 4

Step 6

1 9 4 05 9 4 1

0 0 0 30 0 0 2

1 9 4 02 9 4 1

PC

PC

PC

PC

PC

AC

AC

AC

AC

AC

IR

IR IR

IR IR

1 9 4 0

1 9 4 0

1 9 4 0

1 9 4 0

1 9 4 0

2 9 4 1

2 9 4 1

2 9 4 1

2 9 4 1

2 9 4 1

5 9 4 1

5 9 4 1

5 9 4 1

5 9 4 1

5 9 4 1

0 0 0 3

0 0 0 3

0 0 0 3

0 0 0 3

0 0 0 3

0 0 0 2

0 0 0 2

0 0 0 2

0 0 0 2

0 0 0 2

1 9 4 00 0 0 3

0 0 0 35 9 4 1

0 0 0 52 9 4 1

0 0 0 5

5 9 4 1

0 0 0 52 9 4 1

3 + 2 = 5

3 0 2

3 0 0

3 0 1

3 0 2

3 0 0

3 0 1

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Direct Memory Access (DMA)

I/O exchanges occur directly with memory

Processor grants I/O module authority to read from or write to memory

Relieves the processor from the taskProcessor is free to do other things

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Interrupts

An interruption of the normal processing of processor

Improves processing efficiencyAllows the processor to execute other

instructions while an I/O operation is in progress

A suspension of a process caused by an event external to that process and performed in such a way that the process can be resumed

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Classes of Interrupts

Programarithmetic overflowdivision by zeroexecute illegal instructionreference outside user’s memory space

TimerI/OHardware failure

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Instruction Cycle with Interrupts

STARTSTART

HALT

Fetch NextInstruction

Fetch NextInstruction

ExecuteInstruction

ExecuteInstruction

Check forInterrupt:

Process Interrupt

Check forInterrupt:

Process Interrupt

Fetch Cycle Execute Cycle Interrupt Cycle

InterruptsDisabled

InterruptsEnabled

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Interrupt Handler

A program that determines nature of the interrupt and performs whatever actions are needed

Control is transferred to this programGenerally part of the operating

system

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Interrupt Cycle

Processor checks for interruptsIf no interrupts fetch the next

instruction for the current programIf an interrupt is pending, suspend

execution of the current program, and execute the interrupt handler

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Simple Interrupt Processing

Device controller orother system hardwareissues an interrupt

Processor finishesexecution of currentinstruction

Processor signalsacknowledgmentof interrupt

Processor pushes PSWand PC onto controlstack

Processor loads newPC value based oninterrupt

Save remainder ofprocess stateinformation

Process interrupt

Restore process stateinformation

Restore old PSWand PC

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Multiple InterruptsSequential Order

Disable interrupts so processor can complete task

Interrupts remain pending until the processor enables interrupts

After interrupt handler routine completes, the processor checks for additional interrupts

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Multiple InterruptsPriorities

Higher priority interrupts cause lower-priority interrupts to wait

Causes a lower-priority interrupt handler to be interrupted

Example when input arrives from communication line, it needs to be absorbed quickly to make room for more input

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Memory Hierarchy

Registers

Cache

Main Memory

Disk Cache

Magnetic Disk

Magnetic Tape Optical Disk

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Going Down the Hierarchy

Decreasing cost per bitIncreasing capacityIncreasing access timeDecreasing frequency of access of

the memory by the processorlocality of reference

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Disk Cache

A portion of main memory used as a buffer to temporarily to hold data for the disk

Disk writes are clusteredSome data written out may be

referenced again. The data are retrieved rapidly from the software cache instead of slowly from disk

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Cache Memory

Invisible to operating systemUsed similar to virtual memoryIncrease the speed of memoryProcessor speed is faster than

memory speed

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Cache Memory

Contains a portion of main memoryProcessor first checks cacheIf not found in cache, the block of

memory containing the needed information is moved to the cache

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Cache/Main-Memory Structure

MemoryAddress

1

3

0

2

2n - 1

Block

Block(k words)

WordLength

SlotNumber Tag Block

0

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C - 1Block Length(k words)

(a) Main Memory

(b) Cache

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Cache Design

Cache sizesmall caches have a significant impact on

performanceBlock size

the unit of data exchanged between cache and main memory

hit means the information was found in the cachelarger block size more hits until probability of

using newly fetched data becomes less than the probability of reusing data that has been moved out of cache

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Cache Design

Mapping functiondetermines which cache location the

block will occupyReplacement algorithm

determines which block to replaceLeast-Recently-Used (LRU) algorithm

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Cache Design

Write policywrite a block of cache back to main

memorymain memory must be current for direct

memory access by I/O modules and multiple processors

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Programmed I/O

I/O module performs the action, not the processor

Sets appropriate bits in the I/O status register

No interrupts occurProcessor is kept busy checking

status

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Programmed I/OInsert Readcommand toI/O Module

Read Statusof I/OModule

CheckStatus

Read wordfrom I/OModule

Write wordinto memory

Done?

Yes

No

Next Instruction

CPU Memory

I/O CPU

ErrorCondition

I/O CPU

CPU I/O

Ready

NotReady

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Interrupt-Driven I/O

Processor is interrupted when I/O module ready to exchange data

Processor is free to do other workNo needless waitingConsumes a lot of processor time

because every word read or written passes through the processor

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Interrupt-Driven I/OInsert Readcommand toI/O Module

Read Statusof I/OModule

CheckStatus

Read wordfrom I/OModule

Write wordinto memory

Done?

Yes

No

Next Instruction

CPU Memory

I/O CPU

ErrorCondition

I/O CPU

CPU I/O

Ready

Do somethingelse

Interrupt

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Direct Memory Access

Transfers a block of data directly to or from memory

An interrupt is sent when the task is complete

The processor is only involved at the beginning and end of the transfer

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Direct Memory Access

Next Instruction

CPU DMA

Interrupt

DMA CPU

Do somethingelse

Issue Readblock commandto I/O module

Read statusof DMAmodule