מבנה מחשב תרגול 2. 2 Boolean AND Operation 10 000 101 Truth Table Equivalent Gate Different notations:

מבנה מחשב

2תרגול

2

Boolean AND Operation

01

000

101

Truth Table Equivalent Gate

Different notations :

3

Boolean OR Operation

01

001

111

Truth Table Equivalent Gate

Different notations :

4

Boolean NOT Operation

01

10

Truth Table Equivalent Gate

Different notations :

5

Boolean NAND Operation

01

011

110

Truth TableEquivalent Gate

6

Boolean NOR Operation

01

010

100

Truth TableEquivalent Gate

7

Boolean XOR Operation

01

001

110

Truth Table Equivalent Gate

Different notations :

yxyxyXORxyx ^||

8

How to implement XOR?

)()( yxyxyx

)()( yxyxyx

Which is Better

?

xy

xy

Example

What does the following combinational circuit decide ?

9

10

Boolean Equalities (1)

Rules of Associativity, Commutation. Other rules:

1

0

11

)(

0

00

1

xx

xxx

xx

x

xx

xx

xxx

x

xx

11

Boolean Equalities (2)

Distribution

deMorgan

yxyxyxyx

xyyxx

xyxx

yxyxx

xyxx

)()(

)(

)(

)(

)(

)()()()()()( zxyxzyxzxyxzyx

12

Example (1):Simplify the expression

xzyxzzzy

zyxzzyzyxzy

zyxxzyzyxxzzy

zyxxzzyzyxxzzxxy

zyxxzzxzxy

)(

)(

)(

)1()]([

)(

Compare number of gates

13

CABC

CABCAABCBCCABABCCABC

CCABCABC

ABCABC

ABCADBC

ABCABCDBC

BDCABCABC

)(

)1(

Example (2):Simplify the expression

14

Evaluating an Expression (1)

Let’s look at the first expression:

zyxxzzxzxy )(

0,0,0 zyx

1 11

1

1

15

Evaluating an Expression (2)

Let’s look at the first expression:

zyxxzzxzxy )(

0,0,0 zyx

1

1

=1

1

1

16

Truth Tablex y z ),,( zyxf

0

0

0

0

0

0

0

0

0

0

0

0

1

1

11

1

1

11

1

1

1

1

1

zyxxzzxzxy )(

1

0

1

1

1

0

0

0

1

2

3

4

5

67

We get Different Notation for ),,( zyxf

)7,5,4,1,0(),,( zyxf

17

Disjunctive Normal Formx y z ),,( zyxf

0

0

0

0

0

0

0

0

1

11 1

1

11

1

1

11

1

0

1

4

57

)7,5,4,1,0(),,( zyxf

zyxzyxzyxzyxzyxzyxf ),,(

It’s easy to transform a DNF

formula to its equivalent gates’ representation

18

Disjunctive Normal Formzyxzyxzyxzyxzyxzyxf ),,(

xyz

19

New Components

Two major components of combinational logic are – multiplexors & decoders.

2-input multiplexor (or selector) is implemented with gates below

a

b

s

c

symbol

a

b

c

s

gate implementation

Multiplexors (MUXes)

A device that selects one of several input signals and forwards it into a single line.

Also called a data selector

20

21

Multiplexors (MUXes) Multiplexors can have any number of inputs (in theory)

Multiplexors can apply to buses multiplied for many lines.– Example: 1 x 2 multiplexor on 32 bits bus.

01234567

s0

c

3 X 8 multiplexors1

s2

a31b31

s

c31

a30b30 c30

.

.

.

.

.

.

a0b0 c0

M

M

M

a

b

s

c

32

32

32

symbol

Encoders

An encoder conv-erts information from one format to another. For the purposes of speed, secrecy, security, or saving space by shrinking size.

22

 2n input lines, and at most only one of them will ever be high, produces n-bit output lines. ( Other options – don’t cares )

Decoders

Reverse operation of an Encoder undoing the encoding so that the original information can be retrieved

Combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.

The same method used to encode is usually just reversed in order to decode.

Results in sending less information !!!

23

24

Decoders

Each combination of the inputs enables exactly one output

01234567

DECODER0

1

2

3 X 8 Decoder

InputsOutputs

I2I1I0O7O6O5O4O3O2O1O0

00000000001

00100000010

01000000100

01100001000

10000010000

10100100000

11001000000

11110000000

Adders

A digital circuit that performs addition of numbers.

The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C).

The carry signal represents an overflow into the next digit of a multi-digit addition.

25

Full Adder from Half AddersHalf adder

Full adder from 2 half adders + or gate

ab

Cout

sum

Cin

ab

Cout

sum

We will look into adders more closely when we examine the ALU

27

Flip-Flops What happens if we create a circle in the logic

gates diagram? a Circuit that has two stable states and can be

used to store state information. Can be made to change state by signals applied

to one or more control inputs.

This is aS-R Flip-Flop

R

S

Q

Q

An S-R flip-flop: S – set. R Reset. Initial state Q=1 and R = 0 S = 1 : Changes Q to 1. R = 1 S = 0 : Changes Q to

0.

R=1

S=0

Q=0

Q=1

R=0

S=1

Q=1

Q=0

R=0

S=0

Q=0

Q=1

R=0

S=0

Q=1

Q=0

Q=0

R = 1 S = 1 : illegal

S-R Latch (Or S-R Flip-Flop) Feedback is the key to memory/state elements. Once a value is fed to the element, it circulates inside

the element and renews itself, even after the input is turned off.

Other memory devices can be built from the basic latch.

R

S

Q

Q

SRQQ

00SaveSave

0101

1010

1100Illegal

Clocked "D" Latch

This latch has one input, called "D". When the clock is low, AND gates force zero on all inputs to the S-R

latch no change in state. When clock is high, the value at D sets the "S" input of the latch;

inverted D sets the "R" input of the latch.

Clock

D

Q

Q

S-R Flip-Flop With a Clock

31

D-Flip-Flop (1)

On each clock pulse the FF should be meaningful Therefore the R and S lines should be opposite If so do we still need both of them?

D

CP

S

RQ

Q

32

D Flip-Flop (2)

D Flip-Flop when the clock is pulsing:

001

110

D Q Q

D

CP

Q

Q

"D" Latch Clocking Waveforms

The output "D" responds to the change in input, a characteristic delay after the clock goes high.

Clock

D

Q

Q

D

C

Q

tdelay

tdelay

t delay

34

Edge Triggered "D" flip-flop

The first latch is called the master, the second latch is called the slave

When the clock goes high, the first D latch (master) accepts the change in input

Because of the inverter, the change is blocked from moving on the second D latch (slave).

When the clock goes low, the slave latch accepts the change in input

D

Clock

Q

Q

D Latch

D

C

QD

Latch

D

C

Q

35

RegistersRegisters can be built from a series of ET D latches connected to the same clock

Clock

ET-D Latch

D

C

QET-D Latch

D

C

QET-D Latch

D

C

Q. . . ET-D

Latch

D

C

Q

D0 D1 D2 D(n-1)

Q0 Q1 Q2 Q(n-1)

The Register File Modern digital systems are based on logic with state variables, which are

changed according to a clock. The system consists of two types of logic -- combinational and sequential. – Combinational logic a change in inputs directly causes a change in

output, after a characteristic delay. Different from sequential logic which only changes on the clock.

– Sequential logic contains state elements or memory elements.

State elemen

t 1

State elemen

t 2

Combinational Logic

The simplest type of clocking system to understand is built with edge triggered state elements. The diagram shows a system which clocks on the leading edge

of the clock.

leadingedge

leadingedge

clock period

37

Register File Implementation

of double read port

register 0register 1

. . .register 6register 7

MUX

MUX

data 1

data 2

readreg 1

readreg 2

3 bits

3 bits

32 bits

32 bits

32 bits

32 bits

32 bits

32 bits

32 bits

read reg 1

read reg 2

write reg

write data

write enable

readdata 1

readdata 2

3 bits

3 bits

3 bits

32 bits

32 bits

32 bits

1 bit

38

Write Port Implementation

n-to-1 decoder

01..67

register 0

register 1

.

.

.

register 6

register 7

C

DC

DC

DC

DC

D

.

.

.

write enable

write data

Reg #

32 bits

1 bit

3 bits

Clock

1 bit

1 bit