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    RANGKAIAN ELEKTRONIKA(ELECTRONIC CIRCUITS)

    oleh: Dr. Ir. Retno Wigajatri Purnamaningsih, MTTomy Abuzairi, ST, MT, M.Sc

    Reference Books:

    1. Robert L. Boylestad and Louis Nashelsky, Electronic Devices and

    Circuit Theory, Pearson Education, Inc., Uppersaddle River, NewJersey 07458, USA, 2006.

    2. Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer,Analysis and Design of Analog Integrated Circuits, John Wiley & Sons,Inc., Singapore, 2003.

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    Reference Books:

    [1] Robert L. Boylestad and Louis Nashelsky, Electronic Devices and Circuit Theory,Pearson Education, Inc., Uppersaddle River, New Jersey 07458, USA, 2006.

    [2] Jacob Millman and Christos C. Halkias, Integrated Electronics: Analog and Digital

    Circuits and Systems, McGraw-Hill International Book Co., 1972.[3] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, Analysis and

    Design of Analog Integrated Circuits, John Wiley & Sons, Inc., Singapore, 2003.

    [4] Jacob Millman dan Arvin Grabel, Microelectronics, McGraw Hill InternationalEditions, Electronic Engineering Series, Singapore, 1988.

    [5] Roger T. Howe dan Charles G. Sodini, Microelectronics An Integrated

    Approach, Prentice Hall Electronics and VLSI Series, Prentice Hall, Inc.,Uppersaddle River, New Jersey 07458, USA, 1997.

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    CHAPTER 1. Semiconductor Diodes CHAPTER 2. Diode Applications

    CHAPTER 3. Bipolar Junction Transistors

    CHAPTER 4. DC Biasing - BJTs

    CHAPTER 5. BJT AC Analysis

    CHAPTER 6. Field-Effect Transistors CHAPTER 7. FET Biasing

    CHAPTER 8. FET Amplifier

    CHAPTER 9. BJT and JFET Frequency Response

    CHAPTER 10. Operational Amplifier

    CHAPTER 11. Op-Amp Applications

    CHAPTER 12. Power Amplifiers

    CHAPTER 13. Linear-Digital ICs

    CHAPTER 14. Feedback and Oscillator Circuits

    CHAPTER 15. Power Supplies (Voltage Regulators)

    DAFTAR BAHAN KULIAH

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    4/89DAFTAR BAHAN KULIAH

    CHAPTER 1. Semiconductor Diodes CHAPTER 2. Diode Applications

    CHAPTER 3. Bipolar Junction Transistors

    CHAPTER 4. DC Biasing - BJTs

    CHAPTER 5. BJT AC Analysis

    CHAPTER 6. Field-Effect Transistors CHAPTER 7. FET Biasing

    CHAPTER 8. FET Amplifier

    CHAPTER 9. BJT and JFET Frequency Response

    CHAPTER 10. Operational Amplifier

    CHAPTER 11. Op-Amp Applications

    CHAPTER 12. Power Amplifiers

    CHAPTER 13. Linear-Digital ICs

    CHAPTER 14. Feedback and Oscillator Circuits

    CHAPTER 15. Power Supplies (Voltage Regulators)

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    1) Introduction

    2) FET Small-Signal Model

    3) JFET Fixed-Bias Configuration

    4) JFET Self-Bias Configuration

    5) JFET Voltage-Divider Configuration

    6) JFET Source-Follower (Common-Drain) Configuration

    7) JFET Common-Gate Configuration

    8) Depletion-Type MOSFETs

    9) Enhancement-Type MOSFETs

    10) E-MOSFET Drain-Feedback Configuration

    11) E-MOSFET Voltage-Divider Configuration

    12) Designing FET Amplifier Networks

    13) Summary Table14) Effect of RL and Rsig

    15) Cascade Configuration

    16) Trouble Shooting

    17) Practical Applications

    FET Amplifiers

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    Review7. FET Biasing

    8.1. Introduction

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    KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI 7/89

    ELECTRONIC CIRCUITCHAPTER 7. FET BIASING

    7.3. SELF-BIAS CONFIGURATION

    The level of VDS can be determined by applying Kirchhoffs

    voltage law to the output circuit, with the result that

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    KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI 8/89

    ELECTRONIC CIRCUITCHAPTER 7. FET BIASING

    7.4. VOLTAGE-DIVIDER

    CONFIGURATION

    Applying Kirchhoggs voltage law in clockwise direction to

    indicate loop of FIG. 7.22 result in

    Substituting

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    KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI 9/89

    ELECTRONIC CIRCUITCHAPTER 7. FET BIASING

    7.6. ENHANCEMENT-TYPE MOSFETs

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    8. FET AMPLIFIERS8.1. Introduction

    8.1. Introduction

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    FET Amplifiers provide an excellent voltage gain with the added feature of a

    high input impedance, low-power consumption configurations with goodfrequency range and minimal size and weight

    JFETs, depletion MOSFETs, and MESFETs can be used to design amplifiers

    having similar voltage gains

    The depletion MOSFET (MESFET) circuit, however, has a much higher input

    impedance than a similar JFET configuration

    Whereas a BJT device controls a large output (collector) current by means

    of a relatively small input (base) current, the FET device controls an output

    (drain) current by means of a small input (gate-voltage)

    In general, therefore, the BJT is a CURRENT-CONTROLLED device and the

    FET is a VOLTAGE-CONTROLLED device

    The FET can be used as a linear amplifier or as a digital device in logiccircuits

    In fact, the enhancement MOSFET is quite popular in digital circuitry,

    especially in CMOS circuits that require very low power consumption

    FET device are also widely used in high-frequency applications and in

    buffering (interfacing) applications

    8.1. Introduction

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    12/898.2. FET Small-Signal Model

    8. FET AMPLIFIERS8.2. FET Small-Signal Model

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    13/898.2. FET Small-Signal Model

    The gate-to-source voltage controls the drain-

    to-source (channel) current of an FET

    And the change in collector current that will

    result from a change in gate-to-source voltage

    can be determined using transconductance

    factorgm as follows

    Graphical determination of gm (see Fig. 8.1)

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    14/898.2. FET Small-Signal Model

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    15/898.2. FET Small-Signal Model

    Mathematical definition of gm (the derivative

    of a function at a point is equal to the slopeof the tangent line drawn at that point)

    The maximum of the slope is happened at VGS = 0 V,

    therefore,

    And the general equation of Eq. (8.4) will be On specification sheets, gm is provided as yfs, where yindicates it is part of an admitance equivalent circuit, thef

    signifies forward transfer parameter, and the s indicates

    that it is connected to the source terminal

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    16/898.2. FET Small-Signal Model

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    17/898.2. FET Small-Signal Model

    Plotting gm versus VGS Effect of ID on gm

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    18/898.2. FET Small-Signal Model

    FET input impedance Zi

    For a JFET a practical value of 109 (1000

    M) is typical, whereas a value of 1012 to

    1015 is typical for MOSFETs and MESFETs.

    FET output impedance Zo

    On FET specification sheets, the output

    impedance will typically appear as yos with the

    unit of S

    The parameter yos is a component of an

    admittance equivalent circuit, with the

    subscript o signifying an output network

    parameter and s ther terminal (source) towhich it is attached in the model

    Yos has a range of 10 to 50 S or 20 to 100 K

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    19/898.2. FET Small-Signal Model

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    20/898.2. FET Small-Signal Model

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    21/898.2. FET Small-Signal Model

    FET AC Equivalent Circuit

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    22/898.2. FET Small-Signal Model

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    8. FET AMPLIFIERS8.3. JFET Fixed-Bias Configuration

    8.3. JFET Fixed-Bias Configuration

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    24/898.3. JFET Fixed-Bias Configuration

    Zi

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    Zo, Setting Vi = 0 V as required by definition of

    Zo will establish VGS = 0 V also

    8.3. JFET Fixed-Bias Configuration

    AvPhase Relationship

    The negative sign in the resulting equation for

    Av clearly reveals a phase shift of 180between input and output voltages

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    26/898.3. JFET Fixed-Bias Configuration

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    8. FET AMPLIFIERS8.4. JFET Self-Bias Configuration

    8.4. JFET Self-Bias Configuration

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    28/898.4. JFET Self-Bias Configuration

    Bypassed RS

    Zi

    Zo

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    Bypassed RS

    Av

    8.4. JFET Self-Bias Configuration

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    Unbypassed RS

    Rd=

    8.4. JFET Self-Bias Configuration

    Zi

    Zo

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    Unbypassed RS

    Rdincluded in the network

    8.4. JFET Self-Bias Configuration

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    32/898.4. JFET Self-Bias Configuration

    Unbypassed RS

    Rdincluded in the network

    Av

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    33/898.4. JFET Self-Bias Configuration

    Unbypassed RS

    Rdincluded in the network

    Phase Relationship

    The negative sign in Eq. (8.26) again reveals a

    180 phase shift will exist between Vi and Vo

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    34/898.4. JFET Self-Bias Configuration

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    35/898.4. JFET Self-Bias Configuration

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    8. FET AMPLIFIERS8.5. JFET Voltage-Divider Configuration

    8.5. JFET Voltage-Divider Configuration

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    37/898.5. JFET Voltage-Divider Configuration

    Zi

    Zo

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    38/898.5. JFET Voltage-Divider Configuration

    Av

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    8. FET AMPLIFIERS8.8. Depletion-type MOSFETs

    8.8. Depletion-Type MOSFETs

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    40/898.8. Depletion-Type MOSFETs

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    41/898.8. Depletion-Type MOSFETs

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    42/898.8. Depletion-Type MOSFETs

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    8. FET AMPLIFIERS

    8.9. Enhancement-type MOSFETs

    8.9. Enhancement-Type MOSFETs

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    44/898.9. Enhancement-Type MOSFETs

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    8. FET AMPLIFIERS

    8.11. E-MOSFET Voltage-Divider Configuration

    8.11. EMOSFET Voltage-Divider Configuration

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    46/898.11. EMOSFET Voltage-Divider Configuration

    Zi

    Zo

    Av

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    8. FET AMPLIFIERS

    8.13. Summary Tables

    8.13. Summary Tables

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    48/898.13. Summary Tables

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    49/898.13. Summary Tables

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    50/898.13. Summary Tables

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    51/898.13. Summary Tables

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    8. FET AMPLIFIERS

    8.14. Effects of RL and Rsig

    8.14. Effects of RL and Rsig

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    53/898.14. Effects of RL and Rsig

    All of the two-port equations developed for

    the BJT transistor apply to FET networks also

    because the quantities of interest are defined

    at the input and output terminals and not the

    components of the system

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    54/898.14. Effects of RL and Rsig

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    55/898.14. Effects of RL and Rsig

    Avs

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    56/898.14. Effects of RL and Rsig

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    57/898.14. Effects of RL and Rsig

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    58/898.14. Effects of RL and Rsig

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    8. FET AMPLIFIERS

    8.15. Cascade Configuration

    8.15. Cascade Configuration

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    60/898.15. Cascade Configuration

    The total gain is the product of the gain of

    each stage including the load effects of the

    following stage

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    61/898.15. Cascade Configuration

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    62/898.15. Cascade Configuration

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    63/898.15. Cascade Configuration

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    8. FET AMPLIFIERS

    8.17. Practical Applications

    8.17. Practical Applications

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    65/898.17. Practical Applications

    A three channel JFET audio mixer which the three

    input signals can come from different sources such

    as a microphone, a musical instrument, background

    sound generators, and so on

    All signals can be applied to the same gate terminal

    because the input impedance of the JFET is so high

    that can be approximated by an open circuit

    In general, the input impedance is 100 M (109

    ) or better for JFETs and 100 millions (1014

    )or better for MOSFETs

    If BJTs were employed instead of JFETs, the lower

    input impedance would require a transistor amplifier

    for each channel or at least an emitter-follower as

    the first stage to provide a higher input impedance

    The 10-F capacitors are there to prevent any dcbiasing levels on the input signal from appearing at

    the gate of the JFET, and the 1-M potentiometersare the volume controls for each channel

    The need for the 100-K resistors for each channelis less obvious. Their purpose is to ensure that one

    channel does not load down the other channels and

    severely reduce or distort the signal at the gate

    THREE CHANNEL AUDIO MIXER

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    66/898.17. Practical Applications

    In general, therefore, the 100-K resistors compensate for any difference

    in signal impedance to ensure that one does not load down the other and

    develop a mixed level of signals at the amplifier. Technically, they are

    often called SIGNAL ISOLATION RESISTORS

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    67/898.17. Practical Applications

    SILENT SWITCHINGAny electronic system that incorporates mechanical switching such

    as shown in Fig. 8.55 is prone to developing noise on the line that

    will reduce the signal-to-noise ratio

    One effective method to essentially eliminate this source of noise is

    to use electronic switching such as shown in Fig. 8.56a for a two-

    channel mixing network

    In Fig. 8.56a, the signals to be mixed are applied to the drain side

    of each JFET, and the dc control is connected directly to the gate

    terminal of each JFET

    With 0 V at each control terminal, both JFETs are heavily ON, and

    the resistance from D1 to S1 and from D2 to S2 is relatively small,

    say, 100 for this discussion

    Both electronic switches can be put in the OFF state by

    applying a voltage that is more negative than the PINCH-OFF

    LEVEL as indicated by the 10 V in Fig. 8.56a

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    68/898.17. Practical Applications

    SILENT SWITCHINGThe level of OFF resistance can approach

    10,000 M, which certainly can be

    approximated by an open circuit for mostapplications

    Since both channels are isolated, one can be ON

    while the other is OFF

    The speed of operation of a JFET switch is

    controlled by the substrate (those due to the

    device construction) and stray capacitance levelsand the low ON resistance of the JFET

    Maximum speeds for JFETs are about 100 MHz,

    with 10 MHz being more typical

    However, this speed is critically reduced by the

    input resistance and capacitance of the design

    In Fig. 8.56a, the 1-M resistor and the 47-nF capacitorshave a time constant of = RC = 47 ms = 0.047 s for the dccharging network that is controlling the voltage at the gate

    If we assume two time constants to charge to the pinch-off

    level, the total time is 0.094 s, or a switching speed of

    1/0.094 s 10.6 per-second

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    69/898.17. Practical Applications

    SILENT SWITCHINGCompared to the typical switching speed of the JFET at 10 million

    times in 1 s, this number is extremely small

    Keep in mind, however, that the application is the important

    consideration, and for a typical mixer, switching is not going at

    speeds greater than 10.6 per-second unless we have some radical

    input signals

    It is necessary to have the RC time constant period of time before

    pinch-off level is reached

    Any spike on the line will not be present long enough to charge thecapacitor and switch the state of the JFET

    It is important to realize that THE JFET SWITCH IS A BILATERAL

    SWITH (signals in the ON state can pass through the drain-source

    region in either direction)

    Compared to the diode which is not a bilateral switch

    because it can conduct current at low voltages in only one

    direction

    It should be noted that because the state of the JFETs can be

    controlled by a dc level

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    70/898.17. Practical Applications

    SILENT SWITCHING

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    71/898.17. Practical Applications

    PHASE-SHIFT NETWORKSUsing the voltage-controlled drain-to-source resistance characteristic of a

    JFET, we can control the phase angle of a signal using the configurations of

    Fig. 8.58a

    Fig. 5.58a is a PHASE-ADVANCE NETWORK which adds an angle to the signal,

    while Fig. 5.58b is a PHASE-RETARD CONFIGURATION, which creates a negative

    phase shift

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    72/898.17. Practical Applications

    PHASE-SHIFT NETWORKSFor example, let us consider the effect of RDS on an input signal having a

    frequency such as 10 KHz if we apply it to the network of Fig. 5.58a with the

    drain-to-source resistance of 2 K due to an applied gate-to-source voltage of-3V

    An output signal that is 78.2% of its

    applied signal but with a phase shift of

    38.52

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    73/898.17. Practical Applications

    PHASE-SHIFT NETWORKSFor the network of Fig. 8.58b,

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    TUGAS RANGKAIAN ELEKTRONIKA

    Chapter 8. FET Amplifier

    1. 8.3 JFET Fixed-Bias Configuration (no. 18)

    2. 8.4 Self-Bias Configuration (no. 20)3. 8.5 JFET Voltage-Divider Configuration

    (no. 23)

    4. 8.8 Depletion-Type Mosfet (no. 37)5. 8.15 Cascade Configuration (no. 50)


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