IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
VLSI &
MATLAB
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IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
IEEE PROJECT TITLES 2013-14 - VLSI
DIGITAL SIGNAL PROCESSING
Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic
Efficient Implementation of Reconfigurable Warped Digital Filters with Variable Low-Pass, High-Pass, Band pass, and Band stop
Responses
A survey of FPGA based Interference cancellation architectures for biomedical signals
Low Power VLSI Implementation of Adaptive Noise Canceller Based on Least Mean Square Algorithm
Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation
VLSI implementation of low-power cost-efficient lossless ECG encoder design for wireless healthcare monitoring application
High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation
of Block LMS Algorithm
WIRELESS COMMUNICATION
FFT Architectures for Real-Valued Signals Based on Radix- and Radix- Algorithms
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
A High-Speed Low-Complexity Modified FFT radix-25 Processor for High Rate WPAN Applications
BER Analysis and MAI Cancellation in CDMA Communication System
Time-Multiplexed Offset-Carrier QPSK for GNSS
GF(q) LDPC decoder design for FPGA implementation Efficient implementation of Convolution Encoder and Viterbi
Decoder
FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
A Memory-Efficient and Modular Approach for Large-Scale String Pattern Matching
AUDIO & VIDEO PROCESSING
Color Management for Future Video Systems
A real-time video denoising implementation on FPGA using
contourlet transform
The Electronic Piano Design Based on FPGA and PS2 Interface
Hardware Implementation of a Digital Watermarking System for
Video Authentication
Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB
Audio Decoding
FPGA Implementation for Real-time Chroma-key Effect Using
Coarse and Fine Filter
Adaptive Computationally Scalable Motion Estimation for the
Hardware H.264/AVC Encoder
Control Strategy for Power Flow Management in a PV System
Supplying DC Loads
ASIC and FPGA Implementation of the Gaussian Mixture Model
Algorithm for Real-Time Segmentation of High Definition video
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
ARITHMETIC UNITS
Implementation of High Speed and Low Power Hybrid Adder Based Novel Radix 4 Booth Multiplier
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit
Comparative analysis for hardware circuit architecture of Wallace tree multiplier
8912-Bit Montgomery Multipliers Using Radix-8 Booth Encoding and Coded-Digit
Generic modified Baugh Wooley multiplier Design of high performance 64 bit MAC unit Design of high speed hybrid carry select adder Implementation of binary to floating point converter using HDL Reconfigurable architecture for FIR filter with low power
consumption
Design and implementation of truncated multipliers for precision improvement
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
Design and implementation of 32 bit unsigned multiplier using CLAA and CSLA
Low-Power Digital Signal Processing Using Approximate Adders
Optimized architecture for Floating Point computation Unit
An efficient high speed Wallace tree multiplier
Enhanced high speed modular multiplier using karatsuba algorithm An FPGA based high speed IEEE-754 double precision floating
point multiplier using Verilog
Low power multiply accumulate unit (MAC) for future Wireless Sensor Networks
Development of optimum addition algorithm using modified parallel hybrid signed digit (MPHSD) technique
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
IMAGE PROCESSING
VLSI Implementation of Enhanced Edge Preserving Impulse Noise Removal Technique
High density impulse noise removal based on linear mean-median filter
Least significant bit matching steganalysis based on feature analysis
Satellite image enhancement using discrete wavelet transform and threshold decomposition driven morphological filter
An Efficient Denoising Architecture for Removal of Impulse Noise in Images
Improved low-cost FPGA image processor architecture with external line memory
Fuzzy logic-based implementation of color image processing techniques in FPGA
CORDIC Based Fast Radix-2 DCT Algorithm
VLSI TESTING
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
Adaptive test clock scheme for low transition LFSR and external scan based testing
LFSR-reseeding scheme for achieving test coverage Implementation of a novel architecture for VLSI testing Efficiency improvement in RNG using a simplified algorithm The LUT-SR Family of Uniform Random Number Generators for
FPGA Architectures
Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs
Adaptive Low Power RTPG for BIST based test applications Hardware Trojan Insertion by Direct Modification of FPGA
Configuration Bitstream
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
TRANSISTOR LEVEL DESIGN
Efficient Multi-Ternary Digit Adder Design in CNTFET Technology
Performance analysis and simulation of two different architectures of (6:3) and (7:3) compressors based on carbon Nano-Tube Field
Effect Transistors
A Wide Range CMOS VCO for PLL Applications
QCA Systolic Array Design
Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology
A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology
A novel high-performance CMOS 1 bit full-adder cell
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs.
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
IEEE PROJECT TITLES 2013-14 -
MATLAB
IMAGE PROCESSING
Per-Colorant-Channel Color Barcodes for Mobile Applications: An Interference Cancellation Framework
Optical Image Encryption Based on Chaotic Baker Map and Double Random Phase Encoding
(n, k, p)-Gray Code for Image Systems Reversible Watermarking Based on Invariant Image Classification
and Dynamic Histogram Shifting
A Novel QR Code Guided Image Stenographic Technique Image Compression by Learning to Minimize the Total Error A new filter for removal of salt and pepper noise Novel Algorithms for 2-D FFT and its Inverse for Image
Compression
Comparison of Wavelet Filters in Image Coding using Hybrid Compression Technique
Separable Reversible Encrypted Data Hiding in Encrypted Image Using AES algorithm and Lossy Technique
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
Dual Transform Based Steganography Using Wavelet Families and Statistical Methods
Thumbnail Selection: Delivering Digital Signage Contents to Mobile Phone
Single Remote Sensing Image Dehazing Effective Watermarking Algorithm To Protect Electronic Patient
Record Using Image Transform
WIRELESS COMMUNICATION
Multirate Schemes for WH-spread-CI/MC-CDMA Over Correlated Frequency Selective Channel
Overlay Cognitive Radio OFDM System For 4G Cellular Networks A General Framework for BER Analysis of OFDMA and Zero-
Forcing Interleaved SC-FDMA over Nakagami-m Fading Channels
with Arbitrary m
Partial Transmit Sequence PAPR Reduction Method for LTE OFDM Systems
Performance Analysis of OSTBC for Partial Relay Selection withCorrelated Antennas over Nakagami-m Fading
Design and Implementation of Computationally Efficient MC-CDMA Transceiver and Performance Analysis in Fading hannels
IEEE PROJECT TITLES 2013-14E-mail id : [email protected]
Mobile no : 90951 88016, 978958 6561
An Adaptive Conditional Zero-Forcing Decoder With Full-Diversity, Least Complexity and Essentially-ML Performance for
STBCs
Carrier Frequency Offset Estimation in OFDMA using Digital Filtering
On Higher Order Modulations for OFDM in Frequency-Selective Fading Channels
A Weighted OFDM Signal Scheme for Peak-to-Average Power Ratio Reduction of OFDM Signals
Audio Watermarking Via EMD Volterra Neural Analysis of Fetal Cardiotocographic Signals A New Suboptimal Selection Combining With Enhanced
Performance for BPSK Over Rayleigh Fading Channels
Adaptive Wavelet Wiener Filtering of ECG Signals Adaptive Pixel Pair Matching based Steganography for Audio files.
