ELCT 912:Advanced Embedded Systems
Lecture 2: Memory and Programmable Logic
Dr. Mohamed Abd El Ghany, Department of Electronics and Electrical Engineering
Memory
Random Access Memory (RAM)
Read-Only Memory (ROM)
�Can be read and written�Static Random Access Memory (SRAM)
�A memory device in which permanent binary information is stored�Mask ROM: The programming is done by the semiconductor company during the
2Dr. Mohamed Abd el Ghany Department of Electronics and Electrical Engineering
(SRAM)�Data stored so long as vddis applied �6-transistors per cell�Faster
�Dynamic Random Access Memory (DRAM)
�Require periodic refresh�Smaller (can be implemented by 1 or 3 transistors)�slower
the semiconductor company during the last fabrication process of the unit�PROM: Once the PROM is programmed, it cannot be reversed�EPROM: An erasable PROM and can be erased by exposure to UV light�EEPROM: Can be erased and programmed with electrical pulses�Flash memory: High-density read/write memories that are nonvolatile. They have the ability to retain charge for years with no applied power
ELCT 912: Advanced embedded Systems Winter 2011
Block Diagram of Memory
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Example: 2MB memory, byte-addressable-N =8 (because of byte-addressability)-K= 21 (1 word= 8-bit)
ELCT 912: Advanced embedded Systems Winter 2011
Static Random Access Memory (SRAM)
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ELCT 912: Advanced embedded Systems Winter 2011
Dynamic Random Access Memory (DRAM)
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� 1-transistor DRAM cell� During a write, put value on bitline and then set WL=1� During a read, prechage bitline to Vdd (1) before assert WL to 1�Storage decays, thus requires periodic refreshing (read-sense-write)
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ELCT 912: Advanced embedded Systems Winter 2011
Memory Description
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ELCT 912: Advanced embedded Systems Winter 2011
How to address Memory
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ELCT 912: Advanced embedded Systems Winter 2011
How to address Memory
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ELCT 912: Advanced embedded Systems Winter 2011
Use 2 Decoders
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ELCT 912: Advanced embedded Systems Winter 2011
Tristate Buffer
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ELCT 912: Advanced embedded Systems Winter 2011
Bi-directional Bus using Tri-state Buffer
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ELCT 912: Advanced embedded Systems Winter 2011
Read/Write Memory
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ELCT 912: Advanced embedded Systems Winter 2011
Read/Write Memory
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ELCT 912: Advanced embedded Systems Winter 2011
Building Memory in Hierarchy
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Building Memory in Hierarchy
Design a 2Mx4 using 1Mx4 memory chips
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ELCT 912: Advanced embedded Systems Winter 2011
Building Memory in Hierarchy
Design a 2Mx8 using 1Mx4 memory chips
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Memory Model
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ELCT 912: Advanced embedded Systems Winter 2011
Endianness [Danny Cohen 91]
� A byte ordering- How a multiple byte data word stored in memory
�Endianness (from Gulliver’s Travels)
�Big Endian
�Most significant byte of a multi-byte word is stored at the lowestmemory address
18Dr. Mohamed Abd el Ghany Department of Electronics and Electrical Engineering
memory address
�E.g. Sun Sparc, PowerPC
�Little Endian
�Least significant byte of a multi-byte word is stored at the lowestmemory address
� e.g. Intel x86
�Some embedded & DSP processors would support both for interoperability
ELCT 912: Advanced embedded Systems Winter 2011
Endianness Examples
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ELCT 912: Advanced embedded Systems Winter 2011
� “Permanent” binary information is stored
�Non-volatile memory
�Power off does not erase information stored
Read Only Memory (ROM)
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ELCT 912: Advanced embedded Systems Winter 2011
32x8 ROM
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ELCT 912: Advanced embedded Systems Winter 2011
Programming the 32x8 ROM
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ELCT 912: Advanced embedded Systems Winter 2011
Example: Lookup Table
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ELCT 912: Advanced embedded Systems Winter 2011
Classifying Three Basic PLDs
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ELCT 912: Advanced embedded Systems Winter 2011
Programmable Logic Array (PLA)
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ELCT 912: Advanced embedded Systems Winter 2011
Example using PLA
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ELCT 912: Advanced embedded Systems Winter 2011
Example using PLA
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ELCT 912: Advanced embedded Systems Winter 2011
PLA Device
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ELCT 912: Advanced embedded Systems Winter 2011
PLA Device Design Example
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ELCT 912: Advanced embedded Systems Winter 2011
CPLD and FPGA [brown & Rose 96]
� Complex Programmable Logic Device (CPLD)
�Multiple PLDs (e.g. PALs, PLAs) with Programmable interconnectionstructure
�Pioneered by Altera
�Field-Programmable Gate Array (FPGA)
33Dr. Mohamed Abd el Ghany Department of Electronics and Electrical Engineering
�Field-Programmable Gate Array (FPGA)
�High logic capacity with large distributed interconnection structure
�Logic capacity= number of 2-input NAND gates
�Offers more narrow logic resources
�CPLD offers logic resources with a wide number of inputs (AND planes)
�Offer a higher ratio of Flip-flops to logic resources than CPLD
�High Capacity PLD (HCPLD) is often used to refer to both CPLD and FPGA
ELCT 912: Advanced embedded Systems Winter 2011
CPLD Structure
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ELCT 912: Advanced embedded Systems Winter 2011
FPGA Structure
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ELCT 912: Advanced embedded Systems Winter 2011
FPGA Programmability
� Floating gate transistor
�Used in EPROM and EEPROM
�SRAM-controlled switch-Control
�Pass transistors
36Dr. Mohamed Abd el Ghany Department of Electronics and Electrical Engineering
�Pass transistors
�Multiplexers (to determine how to route inputs)
�Antifuse
�Similar to fuse
�Originally an Open-Circuit
�One-Time Programmable (OTP)
ELCT 912: Advanced embedded Systems Winter 2011
References
� Logic and Computer Design Fundamentalsby M. Morris Mano and Charles R. Kime. 4thedition, Prentice Hall. 2008.
�P. Marwedel: Embedded System Design,
37Dr. Mohamed Abd el Ghany Department of Electronics and Electrical Engineering
�P. Marwedel: Embedded System Design,Springer, 2006
� “First Steps with Embedded Systems” ByteCraft Limited
ELCT 912: Advanced embedded Systems Winter 2011