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Page 1: COE-09-6th Sem

8/6/2019 COE-09-6th Sem 1/12

Total No. ofPages 3



Roll No, ..... .

B.E. (COE)


Time: 3 Hours



Max. Marks : 70

I [a] Draw the signal flow graph and determine transfer function US1l1g

Mason's gain formula, for the block diagram shown in Fig.l. 6

F I §- I, '

[b] A thermometer has a time constant of 15.33 sec. It is qu ickly taken

from temperature O°C to water bath having temperature '100°C . Wha t

temperature will be indicated after 60 sec. ' 4

[c] Exp lain the effect of feedback on sensi tivity and over all gain of the

system. 4

2[a] Deduce the time response of a second order system subjected to unit

ramp input. 5

[b] A servo mechanism is represented by

y +4.8y =144E

where E = C - 0.54 is actuating signal. Find the value of damping

rat io, damped and undamped frequency oscillations. Draw the block

diagram of the system described by abo ve differenti al equations.

c . ( ) s(s +2)[c] A network runct ion H s = ( X2 )

s +4 .I' + 6.1' + 18

Find h(t) using pole zero plot.



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3[a] A unity feedback system has open-loop transfer function

G(.,·)H(.I·)- k(s+I) . k I h I 1 . h k . bletc 1 t e root ocus p ot WI t as vana eS(.I· - I)

parameter. Mark all points on root locus. 5

[b] A feedback system has open loop transfer function

ke"G(.I )H(s )= ( 2 ) Determine by use of Routh criterion , the

s s +5,,+9

maximum value of k for the system to be stable. 4

[e] Expla in thc effect of Integral controller on the performance of a second

order system subjected to unit step input. 5

4[a] The open loop transfer function of certain unity feedback system IS

G(.I')=; 12 (s + 3) . o ~ s t l ' \ l ~ . t Bode-plot and comment upon. " 1.' + 16s .+ 256)

stability of the system. . - . 7

[b] The closed loop magnitude vs frequency response of a second order

system is' shown in Fig.2, find·damping ratio, peak time and percentage

peak overshoot. . 7t ' /-Lj



o 3 F/§-.:l. W---7'5[a] For a unity feedback control system the open loop transfer function

given by G(s)H(s )= I ( ( + I)) , draw the Nyquist plot and determines s +4

whet her the closed loop system will be stable. 7

[b] Design a suitable phase-lag compensating network for a unity feedback

kopen loop transfer fnnction G(s)H(s)= ( X ) to meet thes 1+0 .1 s 1+0.2.1

follow ing specifications, velocity error coeffi cient = 30 sec-' and phas e

margin ;0,400• 7

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6[a] Derive a transfe r function of a system from the data given on Bode

If' diagram shown in Fig.3. 6

db dh /eire.

30 - -- - - - . -,.I

" " I

-1'-- .1. \ - - - -

F / t j -3

20[b] Sketch polar plot for G(s) = ( X ).

S 5+1 s+ 2[c] For a given open loop transfer function


G(s)H(s)= - , determine gam

s(1 + 0.5sXI

+0.05s)phase margin.

7 Write short notes on any FOUR of the follow ing:

[a] M-N circle

[b] Servomotor

[c] Tuning of PID controller

[d] Lead-lag compensation[e] Nichol chart

[fJ Nyquist stability criterion.


rnargm and



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Total No. of pages: 02

SnCTtlnfTn SEMESTERRoll No. _


Time: 3:IIrs



Max. Marks: 70

Note: Attempt any FIVE question,

All Questions carry equal marks.

Assume suitable missing data, if any

Quesla. Design an ER model for keeping track of your favorite sports team. You should

store the matches played, the scores in each match, the players in each match

and individual player statistics for each match. Summary statistics should be

modeled as derived attributes. Illustrate composite and multivalued attributes

in the ER model. 8

b. How will you convert an ER model to relational model? Explain , 6

Ques2a. Consider the following relational schema

Hotel(Hotelno, name, city)

Room(roomno., hotelno, type, price)Booking(hotc lno, guestno, date from, date_to, roomno)

Guest(guestno, guestname, address)

Answer the following queries in SQL and relational algebra:

I. List all the rooms that are currently unoccupied in hotel 'TAJ'.

2. What is the lost income from unoccupied room at hotel 'TAJ'

3. What is average number ofbookings for each hotel in the month ofAugust.

4. Update the price of all rooms in the hotels in Delhi by 5%.

5. Write DOL statement to create the relation 'Booking' . 10

b. What are various quantifiers in relational calculus? Give examples. 4

Qucs3 a. What is meant by Weak entity? How is it related to strong entity? Explain.


b. Explain primary, super key and foreign key. Discuss their significance with

the help of suitable examples. 5

c. Why do we need views? Create a view, List problems with processing update

operations expressed in terms of views. 5

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Ques4a. Describe the concept of full functional dependency with the help of

suitable examples. 4

b. Consider a relation R(A,B,C,D,E) with the following set of FDs:

A-7 BC

CD-7 E



1. Find the candidate keys for R. 2

n. Show that decompo sition of R in Rl(A,B,C) and R2(A,D,E) is a lossless

decomposition. 4

c. Is the above decomposition in BCNF. If yes, explain else get a BCNF

decomposition for R. 4

Ques5 a. What do you mean by Two phase Locking protocol. 5

b. Discuss the problems that can occur with lock based concurrency control

mechanisms and the actions that can be taken by DBMS to prevent them.

5c. Define the prob lem of Dirty read and unrepeatable read. 4

Ques6 a. Explain various kinds of failures that can arise in the system , 4

b. Differentiate between the immediate and deferred mode of log based recovery

techniques with the help of suitable examples. 6

c. How checkpoint mechanism works. 4

Ques7 a. Define serial, concurrent and serializable schedules. 4

b. Discuss RAID and its various levels. 5

c. How will database ensure the properties of atomicity and consistency while

working with transactions? 5

Ques8. Write short notes on any four of the followings

1. Deadlock handl ing

u. Data independence

111. Lossless join decomposition

iv. Aggregation

v. Triggers 14

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Total No. of Pages 3


RollNo .

B.E. (COE)



Time: 3 Hours Max. Marks: 70

Note: Answer any FI\(E questions.Assume suitablemissin data, if an .

1[a] Show how the following problem does not satisfy the requ irements o f a

mechanism to contest acce ss to a critical sectionShared int tum = 1;

int myPid =0; II for process O. Set to 1 for process 111int otherPid = l -m Pid .

while (tum! = myPid)

Do nothin

Ilcritical section

Itum = otherPid;


[b] Given process resource usage and availability as described in following

bl d h llocati ha e , raw t e resource a ocation graPI

Process Current allocation Outstanding Reauests Resources Available

R, R, R] R, R, R) R 1 R, R,

P , 2 0 0 1 1 0 .-P, 3 1 0 0 0 0 0 0 0

P, 13

0 0 0 1

P4 0 1 1 0 1 0



[c] Why are page sizes always a power of 2?

[d] What advantage does segmentation offer


On a simple paged system, can the logical address spac e be smaller

than the physical address space? Can it be larger? 4

[b] List out all the major differences between segmentation and paging.


over multiple variable


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Given references to the following pages by a program

0, 9, 0, 1, 8 1, 8, 7, 8, 7, 1, 2, 8, 2, 7, 8, 2, 3, 8, 3,

how many page faults will occur if the program has three pag e frames

ava ilable to it and uses:

(i) FIFO replacement?

(ii) LRU replacement?

(iii) Opt imal replacement? 6

[b] The second-chance algo rithm rejects pages that have their re ference bitset to I. What happens if all pages have their reference bit set to I .


[c] Explain access Matrix method related to file protection and security.

4Which allocation scheme would work best for a file syst em

implemented on a device that can only be accessed sequentially, a tape

drive, for instance. 4

[b] Classify each of the following as authentication, presentation,

detection. identification, or correction.

(i) A log in program

(ii) Scanning for recently mod ified files in a system directory

(iii) Weekly backups

(iv) Logging all logins and layouts

(v) Promptly deleting unused accounts

[c] Suggest a scheme for implementing the current directory

e fficiently.



d rob in (quantum =1)

Process Arriva l time Processing Time

A 0.000 3

B 1.001 6

_C 4.001 4

0 6.001 2

5[a] For the processes listed in followin g table, what is the average

tum around time (rounding to the nearest hundredth) using:

(i) first-come First served

(ii) Shortest Job First

(ii) Shortest Rema ining Time

(iv) Round Robin (quantum =2)

(v) Roun

[b] Is a non- premptive scheduling algo rithm a good choi ce

interactive system? Briefly explain, why?


for an

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Suppose the head of a moving-head disk with 200 tracks, numbered 0

to 199, is currently serving a request at track 143 and has just finished

a request at track 125. If the queue of requests is kept in the FIFO


86, 147,91, 177,94, 150, 102, 175, 130

What is the total head movement to satisfy these requests for the

following disk scheduli ng algorithms?(i) FCFS (ii) SSTF (iii) SCAN

(iv) LOOK (v) C-SCAN

[b] ls disk scheduling other than FCFS useful III a



Available5 2 0

7[a] Consider the following snapshot of a system

Allocation MaxPo 0 0 1 2 0 0 1 2

Pl I O 0 0 1 7 5 0

P2 1 3 5 4 2 3 5 6

PJ 0 6 3 2 0 6 5 2

p. 0 0 I 4 0 6 5 6

Answer the following questions using the banker 's algorithm:

(i) What is the conte nt of the arrayNeed?

(ii) Is the system in a safe state?

(iii) If a request from process PI arrives for (0,4 ,2,0) can the request

be immediately granted? ? 10

[b] What are the difficulties that may arise when a process is rolled back as

the result of a deadlock? 4

8 Write short notes on any TWO of the following:[a] Interprocess Communication

[b) Semaphores

[e] Process Scheduling

[d) Case study of Linux. 2x7

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Total No. of Pages: 2 Roll Number: .




NOTE: Attempt any FIVE questions. All question carry equal marks.

Assume suitable missing data, if any, and specify it clearly.


Ouestion 1 [6+8](a) Parallelism may be exploited at different processing levels. Explain the ways of exploiting the

parallelism in these levels. Which levels are best suited for SISD, SIMD, MIMD systems?

(b) Consider a dual-processor (PI and P2) system using direct-mapped write-back private caches and a

shared memory, all connected to a common bus. Each cache can have four blocks (0 .. ..3). The shared

memory is divided into eight blocks as 0, 1.. ..7. To maintain cache coherence, the system uses Snoopy

Protocol based on Write-Invalidate policy. Draw the relevant state diagram. Indicate the state of each

valid cache block and mark cache miss/hit in the block trace for each cycle for the following two

asynchronous sequences of memory-access events, where boldface numbers are for write and the

remaining are for read.Processor PI: 0, Q, 0,1, 1,4,3 , 5,Processor P2: 2, a, 0, 0, 1, , 7, 0

Question 2 [7+7]

(a) List all the data dependencies in the following code fragment. Indicate whether these are loop carried or

not. Is the loop paralleli zable? Why or why not?

for ( i = 2 ; i < 100 ; i + I)

{ ali] = b[i] + a[i] ; ;* SI *;c[i-I] = a ji] + d[i] ;;* S2 >';

a[i-I) = 2 * b[i]; ;* S3 *;b[i+l] = 2 * b[i]; j* S4 *; }

(b) Draw 8 x 8 Omega network. Show, whether the permutation (0, 6, 4, 7, 3) (I, 5) (2) can be implemented

without blocking or not?

Question 3 [7+7]

(a) A non-pipelined processor X has a clock rate of 50 MHz and an average CPI of 4. Processor Y, an

improved successor of X, is designed with a five-stage linear instruction pipeline. However, due to

pipeline overheads, the clock rate of Y is only 45 MHz. If a program containing 1000 instructions is

executed on both processors, what is the speedup of processor Y compared with that of processor X?

(b) Consider the following code:

JNEZ RI ne x t ; i f RI != 0 - > nex t (b I)SET RI, 1 ; se t RI = 1

ne x t : SUB R2 ,R I ,1 ; s ubt r ac t 1 f rom RI

JNEZ R2 s omewhere; i f R2 1= 0 - > somewhere (b 2)

(i) Suppose the value of Rl alternates between 2 and O. Ifwe use I-bit of branch history and initially

predict nottaken, then find the number ofmis-predictions over two passes?

(ii) What will be number of mis-predictions in the two passes if we use 2-bit correlating branch


Page 10: COE-09-6th Sem

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Question 4 [4+4+6]

(a) Explain in brief the branch speedup, branch elimination and branch prediction techniques for reducing

the branch hazards in pipelined processors.

(b) Show the recursive construction of a 16 x 16 Baseline Network.

(c) Consider the following reservation table fo r a static pipeline:

0 I 2 3 4 5


(i) Draw the state diagram.

(ii) Find the MAL. Is it optimal?(iii)Is it possible to reduce MAL by adding delays? If so, explain by showing one case.

Question 5 [7+7]

(a) Show in detail the construction of a Decreasing Sorting Network based on Bitonic Sort algorithm for

sorting an unsorted list of8 elements: 3,4, 1,8,5,7,6,2.

(b) Use Software pipelining to improve the ILP for the following loop and show the restructured loop along

with prologue and epiiogue.(Don 't convert C statements into assembly language instructions)

for (k = 0; k < 100 ; k = k + 1){

x[k] = x[k] + 1 ;

y[k] = y[k] + x[k] ;

z[k] = y[k] + 2 ;


Question 6 [8+6]

(a) Characterize the following interconnection networks in terms of latency, bandwidth, cost, scalability and

systems where they are commonly used: (i) 2D-Torus (ii) Hypercube (iii) Illiac Mesh (iv) Tree

(b) Explain the loop skewing transformation and discuss how to apply this to make the following codeparallelizable: for i=2 to n-I do

for j=2 to m-I do

a[ij]={a[i-lj] + a[i+lj] a[ij-l] + a[i j +l]}/4;

Question 7

. .[4+5+5]

(a) Write a loop in C language which contains a branch that will be completely mis-predicted by a one-bitbranch predictor.

(b) Write short note on any TWO of the following:

(i) Consistency models

(ii) 8 x 8 Multi-stage Cube Network

(iii)PRAM algorithm for multiplication of two n x n matrices with n3 processors

(iv)Batcher's Odd Even Merge Sort for sorting 3, 4, 1,8,5, 7,6,2.

(v) Comparison of Store-and-forward routing with Wormhole routing


Page 11: COE-09-6th Sem

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End Semeste r Examination, May 2009

B .E. Btl lSemester. EC/CoE/IC-311 ; Microprocessors

Maximum Marks : 70. Time: Three Hours . Assume any missing data .

Question num ber 1 is compulsory. Attempt any four othe r questions .

<)1. ( ' I "

(a ) D itlc rcm iatc betwee n ( i) th e ins tructions " RS TO'" au rl ".1 iV lI' 0000 '" a nd (ii ) the

acri ou o f execut in g th e '"I II .r instruct ion am i 'Isse rti llg th e " I IO j .I )" s igllal.

( ~ !\ ighl ;l!k r a l l :-:lOX) xvst ciu is reset. the lirsl inst ruc t iou tha t is executed at ad d ress0000 [hcx I is " I'llsh 1\" . \Vh:rl a rc till' c" "k "t s "r Ihe S lac k .unl Ihe S lac k Poiu t.-r:a lic r this inxtrucI iou is cxccurcd? .I l1 st il'y .\"llll r an swer.

(d) l r l lh: ln tcnup t Rcspon«: l ime or a \\'s tCIll is tlclilll'd ;IS l h l . · ~ ] l t illlC between

till' uccurrcncc ol ,01 iu tcrru p: signa l andexecution or (he COITCSpoJldillg interrup t

<uh ro ut in c . then w hat is Ihe ,,"orst ra .'\t' illlc rrt 'j)l respon se l illi e Il l!" a ll :)()X)

: - S C l l l operating \\-jlll ,I 1. 1\1 111. rrvx t.rl? i \ SS Il Il I\. that :111 inl e rru pl s a rc enabled

:lIld tluu non e or tlu: inrcrrupt s is mas ked.

(c) \Vl" i tc ;\ progralll scg lllc...' lli wirl: l '.\act ly 2 iuxtruct iun s th.uwou ld \:;111 a subrout ine

at :\lId l" \' :-;: '; /\ !3 ( 'I ) {l l l ' ' \ ) (l Il ly ilt h.: co ntents or /\C ClI l l l UI; l l p !" arc les s tl1<1 11 0 1" Clltl :lI10 . 111he .' ).

( I)! a ll the m.ich iuc Cyc les Iha l XliX) I1 SCS. Which is the O I ~ s machi ne cycle".

!\S:-illIllC that the sys le lll o pe rat e s without ;IIlY wa it s lales.

(,!:;) I .is t <I ll th e in xtruct ious n fXOX) 111;1 1ca n he lIse d to rc.u l and \\T i l l ' dat a to Ille llio r y

Inill'l 'e,! I/O I'0ns.

I.e (' .\ 't mark s)

l :l) I)\'" ig n the 11H.' 111o ry i l l l \ ' r !; ICl ' Illg ic to in terface I } EI' I{ () i\ '1 and.L' k l : ,·\e { \ ( 'Ill XOX5 IC I is 17 l cX whic h is a Ih l, l\y le J - : I ' I { ch ip;I( ':.: is l ( 27 12(;, wh i!c I( '3 is (J22)(1. which is { l 1 t SI{ ;\ rvl chip. T ile

i "J'I<O i\;! chips arc 11idP IK'd to cove r thl' lo-ver 11 <11 1' PI' l ite (J·lKhy tc ;ldd ress

spac c wh ilv thc l ~ is ma pped 10 the I1pper I",JI'. 1\ lso . IC I Illaps al l even

ad d resses .uul 1( '2 Illa p' all odd addresse s. i.c. add resses DOOO. 000 :' . 000 ·1.

()(IO(, c lc ma p 10 J( 'I a lld add resses 000 I. {)llll.' . OO IiS etc ma p io I( '2 .

(b ) For the qucxiiou ill p;trl (;I), design the mcn rorv in t,.. rl acc such that the

I':I'ROM is 'llTcssed wit]: 110 wa il s lalcs wh ile the S I(I\ M ,leCeSS includcx one

wuit sta te .

Page 12: COE-09-6th Sem

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( ~ (2 .\ 7 l l r ~ (;1) l)r:l\v :! flowchart ,llld .vri u - ;W; S a ~ l l l d co de l'or a s uh ro utiuc to gCllc ra te: l

Pu lse Width Modlll"kd <1'\\ s igll,,1Oil the SUI) pill, The illpil l para meter

10 the xuhrou unc is th vulu- o r lhe desired dill y cvc lc ' I ) ' , The valu e 01" 1) '

lies h l ' I \ \ 'LT I l 0 tn loon I .un l , .1ITcsponds ' 0 all g hit va lue between (and

i llcl udill t!- ) () to 25:', is .....o uunuuicntcd 10 :hc sub rou tine hy the c t l l i llg r o r l 1 through the Accumuln.or. T Ilt' XOX5 sysh' lll runx a l I i\,1I 11. clock sign:lI .uu l

des irl'd I ' \ \ ' 1 lrcqucn ,' is 1"Il I I/..

(b) ' \ 11 I/() dev ice gCIH.:raks 10 I po sitive Fliises that is used to inte rrup t all XOX5

IIsing RST7,5 interrup t input pin , I)r",, ' a llowcha rt and write an lntcrrup:

Sub rou tine ( ISI{ ) wh ic': t l ~ r l the va lue o fa n output port Oil each in terrup t.

The por i address is -IOlhes ), I he rescl value at the output o lI hc pori is

OO( hcx).

(" J :\ set or "n hvles is su .rcd i:: memory sl:\I'l ing::1 address 2000(hes) , The value

"I' ' 11 ' is s tored "I :"Idress I l' lTihes), I)r:;',\' " 11<1\\'eh" r1 and wr ite XOX 5

,,';semh lv xuhrourinc I" hc k d CI IKSI ~ 10 cnlcul ntc the che cksum o ft hcxc


bytes :.Jlld s tore the ' LSUIt :11 ! l lL I lHlry ;lddn.:ss I FFE{hex), 'lh« chec ksum

the l \ \Oo 's comp lement I I 1 : sum ol't hc 'II ' hytL's,

(11) I"stil11 ;ltC' the del; ly illl'l n "cd 1_ the ( K ~ ; l J r \ subrout ine 11IL' l1 tiolled ill part

( <I ) . l S ; \ Iun ction nl'tl11' ,, ',d ll' : . •r ' I1'. The ;'; ()})S system ope rates ;112 ivllL .

\.,o!o ( k.

() S. x "7 m.rrkx)

(:1) !'o:-;p !;I!1l the mod e 1 Op t" ol1 iOil or X25S w i. ' : the tim illg d iag rams lill" the

: ; I I ~ d s h k signa ls ;lS \'..,11 as l coruro! 'gll;ds lIsed hv both the inpu: roor l

I :llhk

and output port 1! ' :H,k.

<h i l.x plai» Ihe uunsm iucr :"-cl i,,, o r lhe X2 :, I IJSi\ I{T ch ip, incl uding Ihl'

n : P ~ \ 1 l contro l si t:I1:Jls. ,, \"ilb:' Il ea l block di agr;IIlL 1:.\ Jl laill the P ( l I ' P l oft!lL'mi hk and couuuand i l l ~ ~ ; o l 1 e l i l l l byres ill ;l';Y1 chn lllllus format.

(a ) I: \ piain Ihe Iun ct ion :lIh: purpose "I' ( l ( ' \ \ ' : , OC \V2 "n d 1)( ' \V-' li ll Ihe X25 'iI' !e: ch ip,

( h) \\'ri le il1i t i ; l1 i / ;l l iol l rout ine Iorth c X251) PI( ' confi gured :ls an I/( ) po rt \vi ; ll

base address I:O(he ,) . 10 sci it up lu r opcr.uion wu h the li, II"lI'ing

s:l\.Li l i r <l l iol i s: XOX 5 xvs tcm, I n r l l 1 a l : ( 1 1 ~ c non-bu ffered en vironm en t .un !

1:,,11\' : ~ l ' s l l ' d d ( :,,11 :"Idress ini crval «. he ,I hvtcs. AII IR pins except 11{2

arc ma sked. Asxum c ih.u Ihe e,,11 "dd ress Ii,,. IRO is OI'-IO(h",),

1)7, (2 , -; Illarks)

\ xln ut not ex Oil ;IllY 1\ \ , (1 tn pi t·s :

_ I " n 'll' lwd 1 0 po rt ill s lave I I I \Hk ,( i l) " 1),\·1,\ l ' l l l l l rn l k r \ , : t l l ! I I as a 1l11.:11l0l ) I . .

(h ) ~ l l l l l k o f Opl : r;llio llo

(e) ~ 7 l,c yho:ln l and I) isp l:J .' cOl l t r o l ler.

(d) X:!5·' o pe l 'a l i \l l l i l l l lHl l k : ~