Chapter 5 Problems.pdf

8/17/2019 Chapter 5 Problems.pdf

1/21

Chapter 5 Problems

Question # 1:-

Solution:-

a)

b)


2/21

c)

Question # 2:-

Solution:-


3/21

a)


4/21


5/21


6/21

Question # 3:-

Solution:-


7/21


8/21


9/21


10/21

Question # 4:-

Solution:-


11/21


12/21


13/21

d)


14/21

Question # 5:-

Solution:-


15/21


16/21


17/21


18/21


19/21


20/21

Question # 6:-

Solution:-

entity AND_OR is

port (

AND_OUT : out std_logic;

OR_OUT : out std_logic;

I0 : in std_logic;

I1 : in std_logic;

CLK : in std_logic;

CE : in std_logic;

RST : in std_logic);

end AND_OR;

architecture BEHAVIORAL_ARCHITECTURE of AND_OR is

signal and_int : std_logic;


21/21

signal or_int : std_logic;

begin

AND_OUT

Chapter 5 Problems.pdf

Documents

Chapter 5 Problems.pdf