ARM7 - INTRODUCTION

HISTORY

Developed by Arcon Computers Ltd between 1983-1985

Design of RISC I & II by the post graduate Students of University of California fell as a base for the ARM

ARM – Advanced RISC Machines Von Neumann Architecture

ARM PROGRAMMING MODEL

SPLR

PC

32BIT

CURRENT PROGRAM STATUS REGISTER

When the 31st bit of result is 1 (Negative)

When the result is zeroWhen the result of arithmetic or shifting operation gives carry out

Overflow into the sign bit

Enable/disable IRQ interrupt

Enable/Disable FIQ interrupt

Indicates Normal/Thumb

Instructions are executed

Overflow

0 1 1 1 0 0 0 0+70H

0 1 1 1 0 0 0 0+70H +

1 1 1 0 0 0 0 0-60H

Overflow into sign bit

Let us take 2, 8 bit signed integers

ARM Operating Modes and Register usage

ARM –Memory Organization

ARM7

32 BIT ADDRESS BUS

MEMORY32 BIT DATA BUS

Addresses up to 4GB (232) Memory (Program + data)

0 – Starting Address

232-1 – Ending Address

Little Endian & Big Endian

Suppose that following 32 bit number is going to be stored in a byte wide memory

0x73425A69

73

42

5A

691000

1001

1002

1003 69

5A

42

731000

1001

1002

1003

Little Endian Big Endian

3 Stage Pipeline

ARM7 Instruction-Features

Load store Architecture Fixed length 32 bit instructions 3 Address Instruction formats

Ex:

ADD R0,R1,R2

R0=R1+R2 Conditional execution of every instructions

All the operands should be loaded into Registers (Before processing)

The result in register has to be stored in memory back

Opposite to this architecture is 8085’s where one operand can be in memory

Ex: ADD M

ARM7 Instruction-Features

Load Store Multiple Registers Ability to perform shift operations and ALU

operations in one cycle 16 bit compressed representation of

instruction for Thumb architecture.

Because ARM7 core has separate 32 bit shifter

ARM Assembly Language Programming Data Processing Instructions

ADD R0,R1,R2 ;R0 :=R1 +R2

Arithmetic and Logical Operations on the Data values in registers

Arithmetic Instructions

Types of Instructions

Data Processing Instructions

It use and change the register values Data Transfer Instructions

It stores register contents to memory and memory contents to register.

Control flow Instructions

Changes the control flow of execution

Branching Instructions

Data Processing Instructions

Bitwise logical OperationsBit clear

Where every 1’s in the second operand (r2) clears the

corresponding bits of first operand (r1).

Register Movement OperationsMove Negated

Data Processing Instructions

Compare Instructions

Instructions with Immediate operands

Instructions with Shifted Register Operands

Immediate values has to be preceded by #

Left shift r1 thrice and add it with r2

Compare, Compare negated, Test, Test equal

Shift Operations

Addition of 64 bit Numbers

Two numbers are held in r0-r1 and r2-r3

Adding ‘s’ to the opcode stands for Set Condition codes

Comparison instruction sets the conditional codes without ‘s’

Multiplication

Multiply and Accumulate Instruction

Provides only 32 bit result

UMULL, SMULL, UMLAL, SMLAL

Provides 64bit results

Register Indirect Addressing

Load register r0 with the content of memory location [r1]

Stores register r0 content to memory location [r1]

How to store the address to the registers?

By using ADR pseudo instruction

ALP to copy memory block

Memory location is incremented by 4 because, 32bit word is taken from the byte wide memory

Various Addressing modes

Base plus Offset Addressing

Pre indexed Mode:

Auto Indexed ModeBase

Offset (can go up to 4kB)

Base Register gets incremented by 4

Various Addressing modes

Post Indexed Addressing

Here the data from the address location [r1] is loaded to r0. Then the base register gets updated.

Multiple Register Transfer

R2=mem32[r0]

R0=r0+4;

R3 =mem32[r0]

R0=R0+4

R4=mem32[r0] so on

Load Multiple Register Increment After

Multiple Register Transfer

Store Multiple Register Increment After (storing)

Store Multiple Register Increment Before (storing)

Stack Addressing

Ascending Stack – When pushing data into the stack, stack grows up (address increasing)

Descending Stack –When pushing the data into the stack, stack goes down (Address decreasing)

Full Stack –SP points to the last valid data item in stack

Empty stack – SP points to the empty location where the data can be pushed

Stack Addressing

Full Ascending Stack (FA) Full Descending Stack (FD) Empty Ascending Stack (EA) Empty Descending Stack (ED)

Control Flow Instructions

B – Branch

Conditional BranchesBEQ BNE

BPL BMI BGT BLT BGE BLE

Unconditional Jump

Conditional Branch - Example MOV R0, #0

LOOP

ADD R0,R1,#1

CMP R0,#10

BNE LOOP

Do the code for the high level language Statements

Conditional execution not only for Branch, for all instructions in ARM

Subroutine call

Branch after storing the next instruction address to link register

Load the link Register content to PC to return to main program

If another subroutine is called from this subroutine, use stack for storing and retrieving PC

ARM Organization

Philips LPC2138

LPC2138 Features

32 bit ARM7TDMI-S Microcontroller 32KB on chip Static RAM/ 512KB Flash ISP via on chip Boot-loader software Two 8 Channel 10 bit A/D Converters with

conversion time of 2.44uS. Single 10 bit D/A Converter Two 32 bit Timers/Counters, PWM unit, Watchdog

Timers Real Time Clock Two UARTs, Two I2C,SPI,SSP Vectored Interrupt Controller

LPC2138 Block Diagram

LPC2138 Memory Organization

Thank You