x86 segmentation, page tables, and interrupts– segment registers (cs, ss, ds, es) – segment * 16 + offset physical address • OS can switch to protected mode – Segmentation

x86 segmentation, page tables, and interrupts

3/17/08 Frans Kaashoek

MIT [email protected]

Outline

•  Enforcing modularity with virtualization – Virtualize processor and memory

•  x86 mechanism for virtualization – Segmentation – User and kernel mode – Page tables – System calls

Last lecture’s computer

•  Memory holds instructions and data •  CPU interprets instructions

for (;;) { next instruction }

instruction

instruction

instruction

data data

data

CPU Main memory

Better view

•  For modularity reasons: many programs •  OS switches processor(s) between programs

Program 1: for (;;) { next instruction }

Program1

Program 2

Program 3

Data for P2

Data for P1

Data for P3

CPU Main memory

Problem: no boundaries

•  A program can modify other programs data •  A program jumps into other program’s code •  A program may get into an infinite loop

0

232-1 Program1

Program 2

Program 3

Data for P2 Data for P1

Data for P3

Main memory

Goal: enforcing modularity

•  Give each program its private memory for code, stack, and data

•  Prevent one program from getting out of its memory

•  Allowing sharing between programs when needed

•  Force programs to share processor

Solution approach: virtualization

•  Virtualize memory: virtual addresses •  Virtualize processor: preemptive scheduling

0

232-1 Program1

Program 2

Program 3

Data for P2

Data for P1

Data for P3

Virtual address

Physical address

0

232-1

232-1

0

232-1

0

MMU

Physical address

Virtual address

Page map guides translation

•  Each program has its own page map –  Physical memory doesn’t have to be contiguous

•  When switching program, switch page map •  Page maps stored in main memory

MMU

Page-map register 0 0xBF

P1’s PT

Protecting page maps: kernel and user mode

•  Kernel mode: can change page-map register, U/K •  In user mode: cannot •  Processor starts in kernel mode •  On interrupts, processor switches to kernel mode

mov $val, %cr3

Page-map register

U/K

What is a kernel?

•  The code running in kernel mode –  Trusted program: e.g., sets page-map, U/K register –  Enforces modularity

Kernel

LibOS w. Unix API

sh

LibOS w. Unix API

ls

K

U

Entering the kernel: system calls

•  Special instructions –  Switches U/K bit

•  Enter kernel at kernel-specified addresses

Kernel

LibOS w. Unix API

sh

LibOS w. Unix API

ls int #

iret

x86 virtual addresses

•  x86 starts in real mode (no protection) –  segment registers (cs, ss, ds, es) –  segment * 16 + offset ➯physical address

•  OS can switch to protected mode –  Segmentation and paging

Translation with segments

•  LDGT loads CPU’s GDT •  PE bit in CR0 register enables protected mode •  Segments registers contain index

Segment descriptor

•  Linear address = logical address + base –  assert: logical address < limit

•  Segment restricts what memory an application can reference

JOS code

•  Why does EIP contain the address of “ljmp” instruction after “movl %eax, %cr0”?

Enforcing modularity in x86

•  CPL: current privilege level – 0: privileged (kernel mode) – 3: user mode

•  User programs can set segment selector •  Kernel can load value in CPL and GDT, but

user programs cannot

x86 two-level page table

•  Page size is 4,096 bytes –  1,048,576 pages in 232 –  Two-level structure to translate

x86 page table entry

•  W: writable? –  Page fault when W = 0 and writing

•  U: user mode references allowed? –  Page fault when U = 0 and user references address

•  P: present? –  Page fault when P = 0

what does the x86 do exactly?

When does page table take effect?

•  PG enables page-based translation •  CR3 contains address of page table

–  Where does the next instruction come from? •  When changing PDE or PTE, you must flush TLB

–  Reload CR3

User mode to kernel mode

•  Instruction: INT n, or interrupt •  n indexes into interrupt descriptor table (IDT) •  IDTR contains physical address of IDT

IDT descriptor

•  Three ways to get into kernel: –  User asks (trap) –  Page fault (trap) –  Interrupts

What happens on trap/interrupt? 1.  CPU uses vector n to index into IDT 2.  Checks that CPL ≤ DPL 3.  Saves ESP and SS in internal register 4.  Loads ESP and SS from TSS 5.  Push user SS 6.  Push user ESP 7.  Push user EFLAGS 8.  Push user CS 9.  Push user EIP 10. Clear some EFLAGS bits 11. Set CS and EIP from IDT descriptor

From kernel to user

•  IRET instruction – Reverse of INT

Labs

•  Lab 1: start kernel –  setup and use segmentation

•  Lab 2: kernel –  Set up kernel address space

•  Lab 3: user/kernel –  Set up user address space –  Set up IDT ‒  System calls and page faults

•  Lab 4: many user programs ‒  Preemptive scheduling

JOS

Recall x86 page table

•  To find P for V OS can walk PT manually

VPT: Mapping the page table

•  Z|Z maps to the page directory •  Z|V maps to V’s page table entry

Z

Summary

•  Kernel enforcing modularity –  By switching processor between programs –  By giving each program its own virtual memory

•  x86 support for enforcing modularity –  Segments –  User and kernel mode –  Page tables –  Interrupts and traps

•  JOS