Top Banner

of 60

Vlsi Design & Technolgy

Apr 05, 2018

Download

Documents

Dimple Gala
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
  • 7/31/2019 Vlsi Design & Technolgy

    1/60

    VLSI Technology Overview

    Jeff Davis

    ECE6130Reading (IEDM 2002 Paper plus

    Begin Chapter 3)

  • 7/31/2019 Vlsi Design & Technolgy

    2/60

    Outline

    Introduction/Motivation

    Physical Technology Trends

    Clock Frequency and Power Trends

    Intels 90nm Logic Process

    Future Opportunities

    Questions

  • 7/31/2019 Vlsi Design & Technolgy

    3/60

    0.001

    0.01

    0.1

    1

    10

    100

    1000

    10000

    1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015

    Year

    NumberofTransistors(Millions)

    1 million transistors @ 1989

    1 billion transistors @ 2008

    40048008

    8080

    8086

    286 386

    486 DX Pentium

    Pentium II Pentium III

    Pentium 4

    Moores Law

    Number of transistors doubles every 18 months!!

  • 7/31/2019 Vlsi Design & Technolgy

    4/60

    Cost-per-function

    Historically 25% reduction every year.

    1971to 2004 --- approximately 4 orders of magnitude decrease in

    cost in cost-per-function.

    Smaller Transistor size reduces the Cost-Per-Function!

    1.58 x increase in transistors per die ?=? 38% reduction in cost?

    Question where does this come from?

  • 7/31/2019 Vlsi Design & Technolgy

    5/60

    1

    10

    10 0

    1000

    10000

    1995 2000 2005 2010 2015

    Yea r

    #oftransistorsper

    chip(M/chip)ITRS partially uses historical

    trends to PROJECT the

    FUTURE of the

    Semiconductor Industry

    FYI: Intel recently

    announced that they will reach

    1 billion transistors by 2007

    with 65nm technology

    ITRS Future Trends/Projections

    Gigascale Integration (GSI) = 1 billion transistors per chip

    (public.itrs.net)

  • 7/31/2019 Vlsi Design & Technolgy

    6/60

    Technology Generation

    DefinitionTraditionally this has been every three years (1994 Roadmap)

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

    (Intel has new technology generation every two years)

  • 7/31/2019 Vlsi Design & Technolgy

    7/60

    Intel on Schedule?The company has attained yields suitable for volumeproduction of 90nm-based processors at Fab D1C,according to Burns. Incorporating CDO (carbon-dopedoxide, a low-k dielectric material) technology, seven copper

    interconnect layers and flip chip packaging, the processorsperformance was outstanding, he added. Fabs 11X isslated to begin volume production next quarter andFab 24 will start wafer input in 2004.

    Further, Intel has begun 65nm test production at its FabD1D and Fabs 24 and 12C will follow in 2005. When Intel

    enters 32 and 22nm processing in 2009 and 2011,respectively, the transistors will be smaller than achromosome, Burns noted.

    DigiTimes (Sept. 22, 2003)

  • 7/31/2019 Vlsi Design & Technolgy

    8/60

    Zeroth Level MOSFET Model

    Q = CV

    Q/L = I

    Moving all charge out of Channel

    Parallel Plate Charge Approximation

    Current Expression

    IDS= C(VGS-VT)/L

    IDS= m Cox (W/L)(VGS-VT)VDS

    kn = process transconductance = mCox VLSI designer does not control

    electron mobility

    =mE

    Lateral Electric Field Approx

    E = V/L

    Rough average carrier velocity

    =m(VDS/L)

    Gate Stack Capacitance

    C = CoxWL

    Cox = eox/tox

    Cox Definition

    bn= device transconductance = (W/L) kn

  • 7/31/2019 Vlsi Design & Technolgy

    9/60

    Zeroth Order nFET Model

    Drain

    Source

    Gate

    IDS

    =

    Drain

    Source

    Rn= VDS/IDS= 1/[mnCox (W/L)n(VGS-VTn)]

    Normally open switch -- assert high switch

    (i.e. VG = high then switch is on )

  • 7/31/2019 Vlsi Design & Technolgy

    10/60

    Zeroth Order pFET Model

    Drain

    Source

    Gate IDS =

    Drain

    Source

    Rp= VDS/IDS= 1/[mpCox (W/L)p(VGS-|VTp|)]

    Normally closed switch -- assert low switch

    (i.e. VG = low then switch is on )

  • 7/31/2019 Vlsi Design & Technolgy

    11/60

    IDS

    VDS

    Drain

    Source

    Gate

    Vdd

    Isaturation

    =1

    2bn(V

    GS-V

    Tn)(V

    DS)VDS=V

    GS-V

    t

    IDS VGS

    =VDD

    VT

  • 7/31/2019 Vlsi Design & Technolgy

    12/60

    Drive Current Metric

    n+ n+

    p

    Source Drain

    Gate Length

    tox

    L

    Idrive

    =mn

    2

    eoer

    tox

    W

    L(V

    dd-V

    Tn)2

    mn

    2

    eoer

    tox

    W

    L(V

    dd)2

    Vdd

    Channel Length

  • 7/31/2019 Vlsi Design & Technolgy

    13/60

    Constant-Field Scaling

    MOSFET device parameters Scaling factor (s>1)

    Doping concentration (Na, Nd) s

    Voltage (V) 1/s

    Gate Oxide Thickness (tox) 1/s

    Channel Length (L) 1/s

    Transistor Width (W)

    1/sJunction Depth (xj)

    1/s

    22 )(

    2

    )(

    2

    dd

    ox

    ro

    tdd

    ox

    ro

    driveV

    L

    W

    t

    VV

    L

    W

    t

    Ieemeem

    -=

  • 7/31/2019 Vlsi Design & Technolgy

    14/60

    Electric Field (E)

    Scaling factor (s>1)

    1

    Carrier Velocity (v = mE) 1

    Depletion Layer Width 1/s

    Gate Capacitance (C=eA/tox) 1/s

    Inversion layer charge density (Qi) 1

    Current (drift) 1/s

    Channel Resistance (R) 1

    Constant-Field Scaling

    Device BehaviorMOSFET device parameters

  • 7/31/2019 Vlsi Design & Technolgy

    15/60

    Constant-Field Scaling

    Circuit Behavior

    Circuit Delay Time(t ~ CV/I) 1/s

    Power Dissipation per circuit (~VI) 1/s2

    Power-Delay Product per circuit (P x t) 1/s3

    Circuit Density ( 1/A ) s2

    Power Density (P/A) 1

    MOSFET device parameters Scaling factor (s>1)

  • 7/31/2019 Vlsi Design & Technolgy

    16/60

    driveICV

    dt

    dVCI dsgds =

    )(2

    )(2

    2

    2dd

    tddox

    ddox

    drive

    dd

    V

    L

    VVL

    WC

    WLVC

    I

    VC

    mm

    t

    -

    ==

    Transistor Performance Metric

    =

    =

    =

    =

    =ddds

    ds

    VV

    V

    ds

    ds

    g

    t

    t

    dVI

    Cdt

    00

    1t

  • 7/31/2019 Vlsi Design & Technolgy

    17/60

    Rn= VDS/IDS= 1/[mnCox (W/L)n(VGS-VTn)]

    A Different View of CV/I?

    t = 2.3RnCGn

    = 2.3 CoxWL

    Cox

    mW

    L(V

    dd-V

    t)

    2 L2

    m(Vdd

    )

    CGn= CoxWL+

    -

  • 7/31/2019 Vlsi Design & Technolgy

    18/60

    Dont forget the wires!

    silicon wafer surface

    M1

    M2

    M3

    M4

    Interconnections between transistors are stacked on top!!

    IBM microprocessor micrograph

  • 7/31/2019 Vlsi Design & Technolgy

    19/60

    Wires Classification: Local and Global

    local wires = intramacrocell wiring

    global wires = inter

    macrocell wiring

  • 7/31/2019 Vlsi Design & Technolgy

    20/60

    ( )

    +

    -

    +=+=

    ddox

    w

    dd

    tddox

    ddwddox

    ds

    ddwg

    WVC

    LC

    V

    L

    VV

    L

    WC

    VCWLVC

    I

    VCC

    mm

    m

    t

    2)(

    2

    )(

    22

    2

    Cgdrive

    I

    CV

    Impact Extra Wire Capacitance??

    Cw

  • 7/31/2019 Vlsi Design & Technolgy

    21/60

    Rwire

    =r

    WrH

    r

    Lwire

    Cwire

    =ereoWr

    He

    Lwire

    t = Rwire

    Cwire

    = ereor

    Lwire2

    HrH

    e

    Global Wire Performance Metric

    Wr

    Hr

    He +-

  • 7/31/2019 Vlsi Design & Technolgy

    22/60

    Transistor and Interconnect

    Performance Metrics

    )(2

    2

    ddV

    L

    m

    +

    ddox

    w

    ddWVC

    LC

    V

    L

    mm2

    )(2

    2

    er

    HrH

    e

    Lwire

    2

    Smaller = Faster!Smaller = No Improvement!

    .Or slower!!

    Transistor only Transistor plus local wire Global long wire

  • 7/31/2019 Vlsi Design & Technolgy

    23/60

    020

    40

    60

    80

    100

    120

    140

    160

    180

    200

    1999 2002 2005 2008 2011 2014

    Year

    D

    rawnandEffectiv

    eChannel

    Length

    +

    ddox

    w

    ddWVC

    LC

    V

    L

    mm2

    )(2

    2

    Minimum Feature Size Decreases 30% every technology generation!

    Minimum Feature Size Projections

    DRAM 1/2 Pitch

    MPU Gate Length

  • 7/31/2019 Vlsi Design & Technolgy

    24/60

    Intel is ahead!

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

  • 7/31/2019 Vlsi Design & Technolgy

    25/60

    0

    0. 5

    1

    1. 5

    2

    2. 5

    3

    1999 2002 2005 2008 2011 2014

    Year

    EffectiveOxideThickn

    ess[nm]

    Equivalent Gate Oxide

    Thickness Projections

    +

    ddox

    wox

    ddWV

    CLt

    V

    L

    mem2

    )(2

    2

    No known solutions

    Quantum Effects!

  • 7/31/2019 Vlsi Design & Technolgy

    26/60

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

    Intel is ahead!

  • 7/31/2019 Vlsi Design & Technolgy

    27/60

    Gate Leakage on the RISE!

    Intel Technology Journal Q3 1998 Thompson, Packan and Bohr

  • 7/31/2019 Vlsi Design & Technolgy

    28/60

    0

    0. 2

    0. 4

    0. 6

    0. 8

    1

    1. 2

    1. 4

    1. 6

    1. 8

    2

    1999 2002 2005 2008 2011 2014

    Year

    Supply

    Voltage

    [Volts]

    Supply Voltage Scaling

    +

    ddox

    w

    dd WVC

    LC

    V

    L

    mm2

    )(2

    2

    WHY SCALE THIS?

  • 7/31/2019 Vlsi Design & Technolgy

    29/60

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

    Intel?

  • 7/31/2019 Vlsi Design & Technolgy

    30/60

    0

    500

    1000

    1500

    2000

    2500

    1999 2002 2005 2008 2011 2014

    Year

    Dr

    iveCurrentperunitwidth(Idrive/W)

    (microA/m

    icron)

    Drive Current Projections

    (microA/micron)ITRS Projections

    ITRS Drive Current per

    Transistor Width Stays constant!

    Idrive

    W=

    m

    2

    eoer

    tox

    1

    L(V

    dd-V

    t)2

    m

    2

    eoer

    tox

    1

    L(V

    dd)2

  • 7/31/2019 Vlsi Design & Technolgy

    31/60

  • 7/31/2019 Vlsi Design & Technolgy

    32/60

    Why?

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

  • 7/31/2019 Vlsi Design & Technolgy

    33/60

    0

    2E-12

    4E-12

    6E-12

    8E-12

    1E-11

    1.2E-11

    1999 2002 2005 2008 2011 2014

    Year

    CV/Imetric[secs]

    Transistor OnlyTransistor plus Local Interconnect

    ITRS Values

    +

    ddox

    w

    dd WVC

    LC

    V

    L

    mm2

    )(2

    2

    CV/I Metric Projections

    Assume Lwire

    = 30F!!

  • 7/31/2019 Vlsi Design & Technolgy

    34/60

    0.00

    20.00

    40.00

    60.00

    80.00

    100.00

    120.00

    140.00

    160.00

    1999 2002 2005 2008 2011 2014

    Year

    GlobalRCChargingTime/C

    V/Igatedelay

    metric

    Global Interconnect 1mm : W=F : Aluminum

    Global Interconnect Delay

    Trends for Lwire=1mm

    ereor

    F2

    Lwire

    2

    What are we going to do! Interconnects dont scale!

  • 7/31/2019 Vlsi Design & Technolgy

    35/60

    Material Changes will help!

    0.00

    20.00

    40.00

    60.00

    80.00

    100.00

    120.00

    140.00

    160.00

    1999 2002 2005 2008 2011 2014

    Year

    GlobalRC

    ChargingTime/(CV/I)gate

    delaymet

    ric

    Global Interconnect 1mm : W=F: Aluminum

    Global Interconnect 1mm: W=F : Copper

    Global Interconnect 1mm: W=F : Copper Low k

    dielectric

  • 7/31/2019 Vlsi Design & Technolgy

    36/60

    0.00

    10.00

    20.00

    30.00

    40.00

    50.00

    60.00

    70.00

    80.00

    90.00

    1999 2002 2005 2008 2011 2014

    Year

    Globa

    lRCChargingTime/CV/Igatedelay

    metric

    Global Interconnect 1mm : W=F : Copper

    Global Interconnect 1mm : W=2F : Copper

    Global Interconnect 1mm : W=3F : Copper

    Reverse-Scaling Methodology

    er

    HrH

    e

    Lwire

    2

    F 2F3F

    Reverse Scaling works --- but at a price!! DENSITY

  • 7/31/2019 Vlsi Design & Technolgy

    37/60

    Repeater Insertion

    0.00

    10.00

    20.00

    30.00

    40.00

    50.00

    60.00

    70.00

    80.00

    90.00

    1999 2002 2005 2008 2011 2014

    Year

    GlobalRCCha

    rgingTime/CV/Igatedelay

    metric

    Global Interconnect: L= 1mm : W=F : Copper

    Global Interconnects With Repeaters:

    L=1mm: W=F: Cu

    L

    L/k L/k L/k

  • 7/31/2019 Vlsi Design & Technolgy

    38/60

    Current Solution:

    Metal Wire Stacks

    0

    2

    4

    6

    8

    10

    12

    1999 2002 2005 2008 2011 2014

    Year

    NumberofMetalLev

    els

    Silicon Transistors

  • 7/31/2019 Vlsi Design & Technolgy

    39/60

    Outline Introduction/Motivation

    Physical Technology Trends

    Clock Frequency and Power Trends

    Intels 90nm Logic Process

    Future Opportunities

    Questions

  • 7/31/2019 Vlsi Design & Technolgy

    40/60

    Trends in Clock Frequency

    Intel Technology Journal Q3 1998 Thompson, Packan and Bohr

    Doubles everytechnology generation

  • 7/31/2019 Vlsi Design & Technolgy

    41/60

    What is driving Increase in Clock

    Frequency?

    Where is extra performance coming from?

    Circuit Delay Time(t ~ CV/I) 1/s

  • 7/31/2019 Vlsi Design & Technolgy

    42/60

  • 7/31/2019 Vlsi Design & Technolgy

    43/60

    Intel Technology Journal Q3 1998 Thompson, Packan, and Bohr

    ~ 1.8x increase per generation

    Trends in Power Dissipation

  • 7/31/2019 Vlsi Design & Technolgy

    44/60

    Dynamic vs. Static Power Trends

    Intel Technology Journal Q3 1998 Thompson, Packan, and Bohr

  • 7/31/2019 Vlsi Design & Technolgy

    45/60

    Why is Static Power Increasing?

    Intel Technology Journal Q3 1998 Thompson and Bohr

  • 7/31/2019 Vlsi Design & Technolgy

    46/60

    Why is Static Power Increasing?

    Intel Technology Journal Q3 1998 Thompson, Packan, and Bohr

  • 7/31/2019 Vlsi Design & Technolgy

    47/60

    Outline Introduction/Motivation

    Physical Technology Trends

    Clock Frequency and Power Trends

    Intels 90nm Logic Process

    Future Opportunities

    Question

  • 7/31/2019 Vlsi Design & Technolgy

    48/60

    Intel State of the Art

    90nm Technology with 50nm gate lengths

    1.2nm gate oxides

    Strained silicon used to increase mobility

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

  • 7/31/2019 Vlsi Design & Technolgy

    49/60

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

  • 7/31/2019 Vlsi Design & Technolgy

    50/60

    After K, Rim, et al (IBM),Mobility Enhancement in Strained Si NMOSFETs with Hf02 Gate

    Dielectrics, 2002 Symposium on VLSI Technology Digest of Technical Papers, Kyoto, Japan,

    pp. 12-13.

  • 7/31/2019 Vlsi Design & Technolgy

    51/60

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

  • 7/31/2019 Vlsi Design & Technolgy

    52/60

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

  • 7/31/2019 Vlsi Design & Technolgy

    53/60

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

  • 7/31/2019 Vlsi Design & Technolgy

    54/60

    Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

  • 7/31/2019 Vlsi Design & Technolgy

    55/60

    Outline Introduction/Motivation

    Physical Technology Trends

    Clock Frequency and Power Trends

    Intels 90nm Logic Process

    Future Opportunities

    Questions

  • 7/31/2019 Vlsi Design & Technolgy

    56/60

    INTELs TRANSISTOR OF THE

    FUTURE!!!!

    Kevin Teixeira, Online Intel Technological Background Report,

    Intels Terahertz Transistor Architecture,www.intel.com/research/silicon.

    AKA Fully-Depleted SOI Device!

    THE TERAHERTZ TRANSISTOR!!

  • 7/31/2019 Vlsi Design & Technolgy

    57/60

    Kevin Teixeira, Online Intel Technological Background Report,

    Intels Terahertz Transistor Architecture,www.intel.com/research/silicon.

  • 7/31/2019 Vlsi Design & Technolgy

    58/60

    James Hutchby, et al, Extending the Road Beyond CMOS, IEEE Circuits and Devices

    Magazine, March 2002, pp. 28-41.

    Other Choices???

  • 7/31/2019 Vlsi Design & Technolgy

    59/60

    Exotic Choices??

    James Hutchby, et al, Extending the Road Beyond CMOS, IEEE Circuits and Devices

    Magazine, March 2002, pp. 28-41.

  • 7/31/2019 Vlsi Design & Technolgy

    60/60

    Outline Introduction/Motivation

    Physical Technology Trends

    Clock Frequency and Power Trends

    Intels 90nm Logic Process

    Future Opportunities

    Questions