vestel-dvb-4_sat-3600_[ET][1]

VESTEL STBSERVICE MANUAL

SATELLITE STBMODELS

SAT 3600SAT 3700SAT 3701SAT 3702SAT 3703SAT 3800SAT 3801SAT 3802

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SATELLITE STB MODELS

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SATELLITE STB MODELS ...................................................................................................................................................... 2

REVISION HISTORY ................................................................................................................................................................. 6

GENERAL DESCRIPTION ........................................................................................................................................................ 7

STI5518 (IC100) ........................................................................................................................................................................ 7SDRAM 8MBYTE (IC300) ...................................................................................................................................................... 23FLASH MEMORY 1 MBYTE (IC301) ........................................................................................................................................ 23EEPROMS 128K (16,384 X 8) 2-WIRE SERIAL (IC302)......................................................................................................... 25

USED IC LISTS.......................................................................................................................................................................... 33

CONNECTORS .......................................................................................................................................................................... 34

POWER CONNECTOR.................................................................................................................................................................. 34FRONT PANEL CONNECTOR ....................................................................................................................................................... 345512 JTAG CONNECTORS......................................................................................................................................................... 34SCART CONNECTION........................................................................................................................................................... 35TV SCART SOCKET................................................................................................................................................................... 35VCR SCART SOCKET ................................................................................................................................................................ 36RS232 SERIAL PORT.................................................................................................................................................................. 36RCA (AUDIO AND COMPOSITE VIDEO) CONNECTOR................................................................................................................. 36

POWER REQUIREMENTS...................................................................................................................................................... 37

PCB EXPLANATIONS.............................................................................................................................................................. 37

INTRODUCTION................................................................................................................................................................... 37POWER BOARD (16PW07 E3) ............................................................................................................................................ 37MAIN BOARD (16MB07 E3 ) ............................................................................................................................................... 38FRONT PANEL BOARD (TK507-2) .................................................................................................................................... 39

SERVICE MENU INTERFACE ............................................................................................................................................... 40

RF MODULATOR SYSTEM :........................................................................................................................................................ 40RF MODULATOR TYPE : ............................................................................................................................................................ 40TUNER TYPE : ............................................................................................................................................................................ 40SCARTS : .................................................................................................................................................................................... 40REBOOT : ................................................................................................................................................................................... 40CLEAR DATABASE : ................................................................................................................................................................... 41L/R: DBCOPY – OK: UPLOAD PGM : ....................................................................................................................................... 41DOWNLOAD PGM : ................................................................................................................................................................... 42REMOTE/FRONT TEST : .............................................................................................................................................................. 427-SEGMENT DISPLAY TEST : ...................................................................................................................................................... 43SYSTEM DIAGNOSTIC :............................................................................................................................................................... 43DEVELOPMENT TEAM : .............................................................................................................................................................. 43UPLOAD DEFAULT SAT_XPDRS : ............................................................................................................................................... 43DOWNLOAD DEFAULT SAT_XPDRS : ......................................................................................................................................... 43RS232 TEST : ............................................................................................................................................................................. 44

SOFTWARE UPGRADE THROUGH RS232 ......................................................................................................................... 45

SCHEMATICS............................................................................................................. ERROR! BOOKMARK NOT DEFINED.

BILL OF MATERIALS ............................................................................................................................................................. 48

BOARD LAYOUT....................................................................................................... ERROR! BOOKMARK NOT DEFINED.

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REVISION HISTORYRev 1.0 07/25/02 Tuncay Akkurt Initial Revision

Schematics

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GENERAL DESCRIPTIONMajor functional blocks are discussed briefly in this section. A more detailed description is contained later in thedocument.

STi5518 (IC100)

1. IntroductionThe STi5518 integrates in a single chip: a transport demultiplex block; an ST20 32-bit system CPU; an

audio/video MPEG2 decoder; display and graphics features; a digital video encoder; and system peripherals. TheSti5518 integrates DirecTV and DVB descramblers in the transport demultiplex block, allowing it to be used in bothDigital Video Broadcasting (DVB) and Digital Satellite System (DSS) set-top box applications.

2. Technical SpecificationIntegrated 32-bit host CPU up to 81 MHz

2 Kbytes of Icache, 2 Kbytes of Dcache, and 4 Kbytes of SRAM configurable as Dcache.

Audio decoder

5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputsIEC60958 -IEC61937 digital outputSRS®/TruSurround®DTS® digital out and MP3 decodingAlignment beep for satellite dishes.

Video decoder

Supports MPEG-2 MP@MLFully programmable zoom-in and zoom-outNTSC to PAL conversion.

DVD and SVCD subpicture decoder

High performance on-screen display

2 to 8 bits per pixel OSD optionsAnti-flicker, anti-flutter and anti-aliasing filters.

PAL/NTSC/SECAM encoder

RGB, CVBS, Y/C and YUV outputs with 10-bit DACsMacrovision® 7.01/6.1 compatible (optional).

Shared SDRAM memory interface

1 or 2x16-Mbit, or 1x64-Mbit 125 MHZ SDRAM.

Programmable CPU memory interface for SDRAM, ROM, peripherals...

Front-end interface

DVD, VCD, SVCD and CD-DA compatible

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Serial, parallel and ATAPI interfacesHardware sector filteringIntegrated CSS decryption and track buffer.

Hardware transport-stream demultiplexor

Parallel/serial inputDES and DVB descramblers32 PID support.

Integrated peripherals

2 UARTs, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timersModem support44 bits of programmable I/OIR transmitter/receiver.

Professional toolset support

ANSI C compiler and libraries.

208 pin PQFP package.

The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes.It integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport demultiplexing anddescrambling, modules for MPEG-2 video and audio decoding with 3D-surround and MP3 support, advanceddisplay and graphics features, a digital video encoder and all of the system peripherals required in a typical low-costinteractive receiver. To cover the needs of DVD-capable set-top boxes, STi5518 integration options include a CSSdecryption block, a Dolby Digital audio decoder and Macrovision copy protection. An ATAPI interface is built-in,supporting the glueless connection of standard Hard Disk Drives. In this way, the STi5518 is ideal for set-top boxesfeaturing trick modes such as live TV recording, pausing and time-shifting. The STi5518 is backward compatiblewith the popular STi5500 set-top box decoder, allowing easy migration from the previous generation. The high levelof integration in a single PQFP-208 package makes the STi5518 ideally suited for low-cost, high-volume set-top boxapplications.

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3. Architecture overviewThe figure below shows the architecture of the Sti5518.

This chapter gives a brief overview of each of the functional blocks of the STi5518.

4. STi5518 functional modulesa. Central processorThe STi5518 Central Processing Unit is a ST20C2+ 32-bit processor core. It contains instruction processing logic,instruction and data pointers, and an operand register. It directly accesses the high-speed on-chip SRAM, whichcan store data or programs and uses the cache to reduce access time to off-chip program and data memory.The processor can access memory via the Programmable CPU Interface (often referred to as the EMI) or theShared Memory Interface (SMI), which is shared with the video, audio, sub-picture and OSD decoders.

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b. MPEG video decoderThis is a real-time video compression processor supporting the MPEG-1 and MPEG-2 standards at video rates up t720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion for display is performed by vertical andhorizontal filters. User-defined bitmaps can be super-imposed on the display picture by using the on-screen displayfunction. The display unit is part of the MPEG video decoder, it overlays the four display planes shown in the figurebelow. The display planes are normally overlaid in the order illustrated, with the background color at the back andthe sub-picture at the front (used as a cursor plane). The sub-picture plane can alternatively be positioned betweenthe OSD and MPEG video planes where it can be used as a second on-screen display plane.

c. Audio decoderThe audio decoder accepts: Dolby Digital, MPEG-1 layers I, II and III, MPEG-2 layer II 6-channel, PCM, CDDA dataformats; MPEG2 PES streams for MPEG-2, MPEG-1, Dolby Digital, MP3, and Linear PCM (LPCM). The audiodecoder supports DTS® digital out (DVD DTS and CDDA DTS). SPDIF input data (IEC-60958 or IEC-61937standards) is accepted if an external circuitry extracts the PCM clock from the stream. Skip frame, repeat blocksand soft mute frame features can be used to synchronize audio and video data. PTS audio extraction is alsosupported. The device outputs up to 6 channels of PCM data and appropriate clocks for external digital-to-analogconverters. Programmable downmix enables 1,2,3 or 4 channel outputs. Data can be output in either I²S format orSony format. The decoder can format output data according to IEC-60958 standard (for non compressed data: L/Rchannels, 16, 18, 20 and 24-bits) or IEC-61937 standard (for compressed data), for FS = 96 kHz, 48 kHz, 44.1 kHzor 32 kHz. Sampling frequencies of 96 kHz, 48 kHz, 44.1 kHz, 32 kHz and half sampling frequencies are supported.A downsampling filter (96 kHz/48 kHz) is available. The decoder supports dual mode for MPEG and Dolby Digital. Itincludes a Dolby surround compatible downmix and a ProLogic decoder. A pink noise generator enables theaccurate positioning of speakers for optimal surround sound setup. PCM beep tone is a special mode used for SetTop Box. It generates a triangular signal of variable frequency and amplitude on the left and right channels. Inglobal mute mode, the decoder decodes the incoming bitstream normally but the PCM and SPDIF outputs aresoftmuted. This mode is used to prepare a period of decoding mode, to synchronize audio and video data withouthearing the audio. Slow-forward and fast-forward trick modes are available for compressed and non-compresseddata. The control interface of the decoder is activated via memory mapped registers in the ST20 address space.

d. IR transmitter/receiverThe STi5518 provides a pulse-position modulated signal for automatic VCR programming by the set-top box. Thesignal is output to the IR blast pin and an accessory jack pin, simultaneously. The pulse frequency, number ofpulses (envelope length) and the total cycle time is controlled by registers.

e. Modem analog front-end interfaceThe Modem Analog Front-end interface is used to transfer transmit and receive DAC and ADC samples betweenthe memory and an external modem analog front-end (MAFE), using a synchronous serial protocol. DMA is used totransfer the sample data between memory buffers and the MAFE interface module, with separate transmit andreceive buffers and double buffering of the buffer pointers. FIFOs are used to take into account the access latencyto memory, in a worst case system and to allow the use of bursts for memory bandwidth efficiency improvement.The V22 bis standard is supported.

f. Memory subsystem

On-chipThe on-chip memory includes 2Kbytes of instruction cache, 2Kbytes of data cache and 4Kbytes of SRAM that canbe optionally configured as data cache. The subsystem provides 240M/bytes of internal bandwidth, supportingpipelined 2- cycle internal memory access. The instruction and data caches are direct-mapped, with a write-backsystem for the data-cache. The caches support burst accesses to the external memories for refill and write-back.Burst access increases the performance of pagemode DRAM memories.

Off-chipThere are two off-chip memory interfaces:• The external memory interface (EMI) accessed by the ST20 is used for the transfer of data and programsbetween the STi5518 and external peripherals, flash and additional SDRAM and DRAM.

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• Shared memory interface (SMI) controls the movement of data between the STi5518 and 16, 32 or 64 Mbits ofSDRAM. This external SDRAM stores the display data generated by the MPEG decoder and CPU and the C2+code data.The EMI uses minimal external support logic to support memory subsystems, and accesses a 32 Mbytes of physicaladdress space (greater if SDRAM or DRAM is used) in four general purpose memory banks of 8 or 16 bits wide, 21or 22 address lines, and byte select. For applications requiring extra memory, the EMI supports this extra memorywith zero external support logic, even for 16-bit SDRAM devices. The EMI can be configured for a wide variety oftiming and decode functions by the configuration registers. The timing of each of the four memory banks can be setseparately, with different device types being placed in each bank with no need for external hardware.

g. Serial communication

Asynchronous serial controllersThe Asynchronous Serial Controller (ASC), also referred to as the UART interface, provides serial communicationbetween the STi5518 and other microcontrollers, microprocessors or external peripherals. The STi5518 has fourASCs, two of which are generally used by the SmartCard controllers.

Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. Parity, framing, andoverrun error detection increase data transfer reliability. Transmission and reception of data can be double-buffered,or 16-deep FIFOs can be used. A mechanism to distinguish the address from the data bytes is included formultiprocessor communication. Testing is supported by a loop-back option. A 16-bit baud-rate generator providesthe ASC with a separate serial clock signal.

Two ASCs support full-duplex and 2 half-duplex asynchronous communication, where both the transmitter and thereceiver use the same data frame format and the same baud rate. Each ASC can be set to operate in SmartCardmode for use when interfacing to a SmartCard.

Synchronous serial controllerTwo Synchronous Serial Controllers (SSC) provide high-speed interfaces to a wide variety of serial memories,remote control receivers and other microcontrollers. The SSCs support all of the features of the Serial PeripheralInterface bus (SPI) and the I2C bus. The SSCs can be programmed to interface to other serial bus standards. TheSSCs share pins with the parallel input/output (PIO) ports, and support half-duplex synchronous communication.

h. Front-end interfaceThe STi5518 can be connected to a front-end through the following interfaces:• I2S interface;• multi-format serial interface;• multi-format parallel interface;• ATAPI interface (for Hard Disk Drives and DVD-ROMs)

i. On-chip PLLThe on-chip PLL accepts 27 MHz input and generates all the internal high-frequency clocks needed for the CPU,MPEG and audio subsystems.

j. Diagnostic controller (DCU)The ST20 Diagnostic Controller Unit (DCU) is used to boot the CPU and to control and monitor the chip systems viathe standard IEEE 1194.1 Test Access Port. The DCU includes on-chip hardware with ICE (In Circuit Emulation)and LSA (Logic State Analyzer) features to facilitate verification and debugging of software running on the on-chipCPU in real time. It is an independent hardware module with a private link from the host to support real-timediagnostics.

k. Interrupt subsystemThe interrupt system allows an on-chip module or external interrupt pin to interrupt an active process so that an

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interrupt handling process can be run. An interrupt can be signalled by one of the following: a signal on an externalinterrupt pin, a signal from an internal peripheral or subsystem, software asserting an interrupt in the pendingregister. Interrupts are implemented by an on-chip interrupt controller and an on-chip interrupt-level controller. Theinterrupt controller supports eight prioritized interrupts as inputs and manages the pending interrupts. This allowsthe nesting of pre-emptive interrupts for real-time system design. Each interrupt can be programmed to be at alower or higher priority than the high priority process queue.

l. PAL/NTSC/SECAM encoderThe integrated digital encoder converts a multiplexed 4:2:2 or 4:4:4 YCbCr stream into a standard analog basebandPAL/NTSC or SECAM signal and into RGB, YUV, Yc and CVBS components. The encoder can perform closed-caption, CGMS encoding, and allows MacrovisionTM 7.01/6.1 copy protection. The DENC is able to encode Teletextaccording to the “CCIR/ITU-R Broadcast Teletext System B” specification, also known as “World System Teletext”.In DVB applications, Teletext data is embedded within DVB streams as MPEG data packets. It is the responsibilityof the software to handle incoming data packets and in particular to store Teletext packets in a buffer, which thenpasses them to the DENC on request.

m. SmartCard interfacesTwo SmartCard interfaces support SmartCards compliant with ISO7816-3. Each interface is has a UART (ASC), adedicated programmable clock generator, and eight bits of parallel IO port.

n. PWM and counter moduleThe PWM and counter module provides three PWM encoder outputs, three PWM decoder (capture) inputs and fourprogrammable timers. Each capture input can be programmed to detect rising edge, falling edge, both edges orneither edge (disabled). These facilities are clocked by two independent clocks, one for PWM outputs and one forcapture inputs/timers. The PWM counter is 8-bit, with 8-bit registers to set the output-high time. Thecapture/compare counter and the compare and capture registers are 32-bit. The module generates a singleinterrupt signal.

o. Parallel I/O module44 bits of parallel I/O are configured in 6 ports, and each bit is programmable as output or input. The output can beconfigured as a totem-pole or open-drain driver. The input compare logic can generate an interrupt on any changeof any input bit. Many parallel IO have alternate functions and can be connected to an internal peripheral signalsuch as a UART or SSC.

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5. Pin list sorted by function

Alternate functions printed in Italic show a suggested use of the PIO; alternate functions not printed in Italic aremultiplexed with a specific hardware.

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1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration.2. The NRSS_IN and NRSS_OUT pins are swapped around on the STi5518 compared to the STi5508.3. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path.4. Inverted. ATTENTION! the PIO input is also inverted.5. The PIO must be configured in open drain.6. BOOT_FROM_ROM is active during reset.7. Tie low whenever JTAG is not used.

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6. Pins sorted by pin number

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1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration.2. The NRSS_IN and NRSS_OUT pins are swapped around on the STi5518 compared to the STi5508.3. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path.4. Inverted. ATTENTION! the PIO input is also inverted.5. The PIO must be configured in open drain.6. Tie low whenever JTAG is not used7. BOOT_FROM_ROM is active during reset.

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SDRAM 8MByte (IC300)

FEATURES• PC66-, PC100- and PC133-compliant• Fully synchronous; all signals registered on positive edge of system clock• Internal pipelined operation; column address can bechanged every clock cycle• Internal banks for hiding row access/ precharge• Programmable burst lengths: 1, 2, 4, 8 or full page• Auto Precharge, includes CONCURRENT AUTOPRECHARGE, and Auto Refresh Modes• Self Refresh Modes: standard and low power• 64ms, 4,096-cycle refresh• LVTTL-compatible inputs and outputs• Single +3.3V ±0.3V power supply

GENERAL DESCRIPTIONThe 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is

internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positiveedge of the clock signal, CLK). Each of the x4’s 16,777,216 -bit banks is organized as 4,096 rows by 1,024 columns by 4bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of the x16’s16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to theSDRAM are burst oriented; accesses start at a selected location and continue for a programmed number oflocations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is thenfollowed by a READ or WRITEcommand. The address bits registered coincident with the ACTIVE command are used to select the bank and row to beaccessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ orWRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page,with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge thatis initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the columnaddress to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank whileaccessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-accessoperation. The 64Mb SDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode isprovided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM’s offersubstantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data ratewith automatic column-address generation, the ability to interleave between internal banks in order to hide precharge timeand the capability to randomly change column addresses on each clock cycle during a burst access.

Flash Memory 1 MByte (IC301)Low Voltage Single Supply Flash Memory

2.7V to 3.6V SUPPLY VOLTAGEforPROGRAM, ERASE and READ OPERATIONSFASTACCESS TIME: 90nsFASTPROGRAMMING TIME– 10µs by Byte / 20µs by Word typicalPROGRAM/ERASE CONTROLLER (P/E.C.)– Program Byte-by-Byte or Word-by-Word– Status Register bits and Ready/Busy OutputMEMORY BLOCKS– Boot Block (Top or Bottom location)– Parameter and Main blocks

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BLOCK, MULTI-BLOCK and CHIP ERASEMULTI BLOCK PROTECTION/TEMPORARYUNPROTECTION MODESERASE SUSPEND and RESUME MODES– Read and Program another Block duringErase SuspendLOW POWER CONSUMPTION– Stand-byand AutomaticStand-by100,000 PROGRAM/ERASE CYCLES perBLOCK20 YEARSDATARETENTION– Defectivity below 1ppm/yearELECTRONIC SIGNATURE– Manufacturer Code: 0020h– Device Code, M29W800T: 00D7h– Device Code, M29W800B: 005Bh

DESCRIPTIONThe M29W800 is a non-volatile memory that may be erased electrically at the block or chip level and programmedin-system ona Byte-by-Byteor Wordby-Word basis using only a single 2.7V to 3.6V VCC supply. For Program andErase operations the necessary high voltages are generated internally. The device can also be programmed instandard programmers. The array matrix organisation allows each block to be erased and reprogrammed withoutaffecting other blocks. Blocks can be protected against programing and erase on programming equipment, andtemporarily unprotected to make changes in the application. Each block can be programmed and erased over100,000 cycles. Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protectionstatus, Programming, Blockand Chip Erase, Erase Suspend and Resume are written to the device in cycles ofcommands to a Command Interface using standard microprocessor write timings. The device is offered inTSOP48(12 x 20mm) and SO44 packages. Both normal and reverse pinouts are available for the TSOP48package.

OrganisationTheM29W800 is organised as 1 Mx8 or 512K x16 bits selectable by the BYTE signal. When BYTEis Low the Byte-wide x8 organisation is selected and the address lines are DQ15A–1 and A0-A18. The Data Input/Output signalDQ15A–1 acts as address line A–1 which selects the lower or upper Byte of the memory word for output on DQ0-DQ7,DQ8-DQ14 remain at High impedance. When BYTEis High the memory uses the address inputs A0-A18 andthe Data Input/Outputs DQ0-DQ15. Memory control is provided by Chip Enable E, Output Enable G and WriteEnableW inputs. AReset/Block Temporary Unprotection RPtri-level input provides a hardware reset when pulledLow,and when held High (atVID) temporarily unprotects blocks previously protected allowing them to be programedand erased. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). StatusRegister data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicatethe state of the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms.

Memory BlocksThe devices feature asymmetrically blocked architecture providing system memory integration. Both M29W800TandM29W800Bdeviceshavean array of 19 blocks, one Boot Block of 16 KBytes or 8KWords, two Parameter Blocks of 8KBytes or 4KWords, one Main Block of 32 KBytes or 16KWordsand fifteen Main Blocks of 64 KBytes or 32KWords.The M29W800Thas the Boot Block at the top of the memory address space and the M29W800B locates the BootBlock starting at the bottom. The memory maps are showed in Figure3. Each block can be erased separately, anycombination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operationsare managed automatically by the P/E.C. The block erase operation can be suspended in order to read from orprogram to any block not being ersased, and then resumed. Block protection provides additional data security. Eachblock can be separately protected or unprotected against Program or Erase on programming equipment. Allpreviously protected blocks can be temporarily unprotected in the application.

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Bus OperationsThe following operations can be performed using the appropriate bus cycles: Read(Array, Electronic Signature,Block Protection Status), Write command, Output Disable, Standby, Reset, Block Protection, Unprotection,Protection Verify, Unprotection Verify and Block Temporary Unprotection.

Command InterfaceInstructions, made up of commands written in cycles, can be given to the Program/Erase Controller through aCommand Interface (C.I.). For added data protection, program or erase execution starts after4 or 6 cycles. The first,second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for allProgram/Erase Controller instructions. The ’Command’ itself and its confirmation, when applicable, are given on thethird, fourth or sixth cycles. Any incorrect command or any improper command sequence will reset the device toRead Array mode.

InstructionsSeven instructions are defined to perform Read Array, Auto Select (to read the Electronic Signature or BlockProtection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C.automatically handles all timing and verification of the Program and Erase operations. The Status Register DataPolling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitorthe progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Codedsequence to the Command Interface which is common to all instructions The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status forRead operations. In order to give additional data protection, the instructions for Program and Block or Chip Eraserequire further command inputs. For a Program instruction, the fourth command cycle inputs the address and datato be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Codedsequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, inorder to read data from another block or to program data in another block, and then resumed. When power is firstapplied or if VCC falls below VLKO, the command interface is reset to Read Array.

EEPROMs 128K (16,384 x 8) 2-wire Serial (IC302)

Features• Low-voltage and Standard-voltage Operation– 5.0 (VCC = 4.5V to 5.5V)– 2.7 (VCC = 2.7V to 5.5V)– 1.8 (VCC = 1.8V to 3.6V)• Internally Organized 16,384 x 8 and 32,768 x 8• 2-wire Serial Interface• Schmitt Trigger, Filtered Inputs for Noise Suppression• Bidirectional Data Transfer Protocol• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility• Write Protect Pin for Hardware and Software Data Protection• 64-byte Page Write Mode (Partial Page Writes Allowed)• Self-timed Write Cycle (5 ms Typical)• High Reliability– Endurance: 100,000 Write Cycles– Data Retention: 40 Years– ESD Protection: > 4000V• Automotive Grade and Extended Temperature Devices Available• 8-pin JEDEC PDIP, 8-lead JEDEC and EIAJ SOIC, 14-lead TSSOP, and8-pad Leadless Array Packages

DescriptionThe AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read onlymemory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device’s cascadable feature allows up tofour devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial

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applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin JEDEC PDIP, 8-lead EIAJ, 8-lead JEDEC SOIC, 14-lead TSSOP, and 8-pad LAP packages. In addition, theentire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negativeedge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and maybe wire-O Red with any number of other open-drain or open collector devices.DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left notconnected for hardware compatibility with AT24C32/64. When the pins are hardwired, as many as four 128K/256Kdevices may be addressed on a single bus system (device addressing is discussed in detail under the DeviceAddressing section). When the pins are not hardwired, the default A1 and A0 are zero.WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP istied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down toGND. Switching WP to VCC prior to a write operation creates a software write protect function.

Memory OrganizationAT24C128/256, 128K/256K SERIAL EEPROM: The128K/256K is internally organized as 256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data word address.

Absolute Maximum RatingsOperating Temperature.................................. -55°C to +125°CStorage Temperature ..................................... -65°C to +150°CVoltage on Any Pinwith Respect to Ground .....................................-1.0V to +7.0VMaximum Operating Voltage .......................................... 6.25VDC Output Current........................................................ 5.0 mA

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Tuner Alps (TU400)

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USED IC LISTS MAINBOARD (16MB07 E3)

MAX 232 (IC101) RS232 Driver/Receiver

Sti5518(IC100) Set Top Box Backend Decoder With Integrated Host Processor

TSH 22 (IC103) Dual Bipolar Operational Amplifier

M74HCU04 (IC102) Hex Inverter

MT48LC4M16A2 (IC300) 1 Mbyte x 16 x 4 banks SDRAM

M29W800T (IC301) Single Supply Flash Memory

M24C128 (IC302) 128Kbit Serial EEPROM

LM833 (IC501) Low Noise Dual Operational Amplifier

CS4335 (IC500) 8-Pin, 24 Bit, 96 KHz Stereo D/A Converter

DS1811 (IC400) Reset IC

NDS8947 (Q402) Dual P – Channel Enhancement Mode Field Effect Transistor

POWER BOARD (16PW07 E3)

TOP233Y (IC1) SMPS primary IC

SFH617A (IC2) Optocoupler

TL431(IC3) Programmable Precision Reference

LM358N (IC4) Low Power Dual Operantional Amplifier

LM7812 (IC5) 12V Voltage Regulator

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CONNECTORS

Power Connector

Power Connector – PL400Pin Description1 LNB_SUPPLY_IN2 +30V3 +12 V4 GND5 GND6 +5 V7 +3V38 +3V39 H/V10 LNB_POWER_ENABLE11 DISEQC

Front Panel Connector

Front Panel Connector – PL401Pin Description1 STANDBY2 SW3_STDBY3 GND4 SW1_UP5 SW1_DOWN6 GND7 IR_IN8 5VFP

5512 JTAG Connectors

JTAG Connector – PL100Pin Description Pin Description1 ------ 11 TCK2 GND 12 GND3 TRIGOUT 13 TDI4 GND 14 GND5 TRIGIN 15 TDO6 GND 16 GND7 ------ 17 JTAGRESET8 GND 18 GND9 TMS 19 TRST10 GND 20 GND

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SCART CONNECTION

20 18 16 14 12 10 8 6 4 2

21 19 17 15 13 11 9 7 5 3 1

TV Scart Socket

TV Scart Socket – PL200Pin Description Pin Description1 Audio Right Output 12 No Connection

2 No Connection 13 GND

3 Audio Left Output 14 GND

4 GND 15 RED Output

5 GND 16 Fast Blanking Output


7 BLUE Output 18 GND

8 Function Switching Output 19 CVBS Output

9 GND 20 No Connection


11 GREEN Output

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VCR Scart Socket

VCR Scart Socket – PL200Pin Description Pin Description1 Audio Right Output 12 No Connection

2 Audio Right Input 13 GND

3 Audio Left Output 14 GND



6 Audio Left Input 17 GND


8 Function Switching Input 19 CVBS Output

9 GND 20 CVBS Input


11 No Connection

RS232 Serial Port

RS232 Header – JK_DSUB_9Pin Description Pin Description1 - 2 -3 TXD 4 CTS5 RXD 6 RTS7 - 8 -9 GND

RCA (Audio and Composite Video) Connector

A/V Connector – JK1Pin Description1 CVBS VIDEO2 LEFT AUDIO3 RIGHT AUDIO

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POWER REQUIREMENTSPower measurements are for a board configured according to the included Bill of Materials while playing a

typical DVB channel.

16MB07 E3 BoardPower Consumption

Voltage Current mA PowerWatts

LNB_SUPPLY_IN (13V, 18V) ----- -----+30V 1mA+12V 30mA+5V 130mAST

AN

D_B

Y

+3V3 ----- ----Voltage Current mA Power

WattsLNB_SUPPLY_IN (13V, 18V) 500mA (max)

+30V 1mA+12V 100mA+5V 200mA

POW

ER_O

N

+3V3 960mA

PCB EXPLANATIONS

INTRODUCTION

DVB-S (digital satellite receiver) is designed with ST chipset. The technical information ofthe receiver will be explained as three parts in the following pages: Power Board, Main Boardand Front Panel Board.

POWER BOARD (16PW07 E3)

The TOPSwitch concept is used for power supply. TOP 233Y (IC1) is designed to workuntil 50 Watts in family of TOPSwitch_FX with 5 pins. The receiver works between 85 and 265VAC mains voltage by using TOP 233Y in SMPS (Switch Mode Power Supply). The secondaryvoltage regulation is adjusted by changing the duty cycle of drain signal according to thefeedback voltage, which is got from the secondary side of transformer. The feedback voltagesare 3.3V and 5V. This is connected to the comparator pin of TOP 233Y (IC1-pin1) via IC12(Optocoupler). The comparator pin also protects the box against short circuits and overload. TheVcc voltage of IC1 is between 2V –3V at pin2. The TOP 233Y works at a fixed frequency. Thisfrequency is fixed by RC oscillator at pin1. The pin3 and pin 4 are ground and the pin5 is drainof MOSFET, which is inside the TOP 233Y.

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The switching of LNB supply voltage is done here. 18V and 22V outputs of transformerswitched by Q1, Q2 and H/V output of STV299 (TU400). By this way overheating andunnecessary power consumption of Q5 (BD235) that regulates the LNB supply is prevented.22kHz tone which is needed for DiSEqC signals, is generated at pin15 (Alps-TU400) or pin12(Sharp-TU400) of STV0299 in tuner 22KHz is added to LNB supply here via LM358N (IC4).

16PW07-3 Power BoardRange of Voltage

Voltage Range of VoltageLNB_SUPPLY_IN (13V, 18V) -----

+30V 31V – 34V+12V 11.8V – 12.20V+5V 4.7 V – 5.3V

STA

ND

_BY

+3V3 3.6 V – 3.9VVoltage Range of Voltage

LNB_SUPPLY_IN (13V VER) 13 V – 14 VLNB_SUPPLY_IN (18V HOR) 17V – 19V

+30V 31 V – 34 V+12V 11.8 V – 12.2 V+5V 4.8 V – 5.2 V+3V3 3.3 V – 3.6VPO

WER

_ON

+2V5 2.4 V – 2.7V

MAIN BOARD (16MB07 E3 )

The main board contains two parts: Front-end and Back-end. The digital signal isdemodulated in Front-end and then decoded in Back-end. Analog signals are processed indifferent part.

The tuner (TU400 Alps or Sharp) is capable of getting both digital broadcasts. After themodulated signals (I, Q outputs) receive from tuner, they go to STV0299 for demodulationprocess in tuner. (TU400) In this IC, QPSK (Quadrated Phase Shift Keying) demodulation andForward Error Correction (FEC) are done which is necessary to demodulate DVB-Stransmission. TS (transport stream): The multiplexed digital stream which includes video, audioand data information related to more than one channel (can be only one channel for SCPCsignals) and DVB tables. TS signals which are generated after demodulation, reach to Sti5518(IC100) via 8 bits data bus. However, Byte Clock (TSIn_BCLK), Packet Clock (TSIn _STROUT)signals are also sent to ST5518 (IC100) for demultiplexing process of TS. STV0299 is controlledby I2C. In addition, 22kHz tone which is needed for DiSEqC signals, is generated at pin12 (Alps)or pin10 (Sharp) of STV0299 in tuner.

LNB supply voltage (13/18V) is regulated via power board. Switching of supply voltagebetween LOOP_IN and LNB_SUPPLY is done by Q402 transistors. The voltage on R403 isproportional with the current of LNB supply. Overload on LNB supply increases the voltage onR403, which results switching of Q400, Q401. By this way input LNB_OVERLOAD signal port of

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Sti 5518 (IC100) has the knowledge of LNB overload and then LNB supply is cut off forprotection of box via Sti 5518 port (P25).

At the backend part, there is a 32-bit CPU ST20 (in Sti 5518 embedded) that controls allprocesses. Demultiplexer of the CPU provides the transmission of the desired channel’sinformation from TS (Transport Stream) to MPEG Decoder section. The program that runs onSti5518 is in Flash memories (IC301). 8Mbits SDRAM (IC300) is used for data memory of thisprogram.

ST20 uses 32- bit data and 22- bit address buses for access to flash, DRAM and MPEGdecoder. It uses RAS, CAS etc. (read, write, enable) signals to activate related IC whileaccessing them.

The clock which is needed by Sti 5518 (IC100), is generated at power on mode by27MHz crystal (X100) and IC102 (74HCU04). The output of PWM outputs of Sti 5518 (IC100), isfiltered to have a DC level via R129 and C118. At the output of ICS3, the 27MHz clock can beadjusted according to capacity of pins of 27MHz crystal to ground. This capacity is related withDC value on D100 and D101 (BB133) at pins of crystal. This operation maintainssynchronization between audio-video that are coming from MPEG transport stream and PCRclock.

Sti 5518 (IC100) can communicate any micro controller via RS232 by using IC101(MAX232- RS232 level converter). The RS232 output of receiver is used for debug any problemusing Windows Hyper Terminal program.

MPEG decoder in Sti 5518 (IC100), is responsible for decoding of MPEG video and audiosignals. The video, which is compressed using MPEG2 and audio, which is compressed usingMPEG1 Layer 1-2, are processed here. After decoding, CCIR 601 formatted 8-bit video andPCM formatted audio, are generated by mpeg decoder.

If digital broadcast has a teletext information, Sti 5518 (IC100) inserts teletext info intoVBI (vertical blanking interval) which can be watched on TV. Digital audio that is PCM formattedon Sti 5518’ s output, is processed by CS4335 (IC500) and amplified by LM833 (IC501) andthen switched through IC200 (M74HC4052).

In digital mode, RGB signals are only delivered to TV scart. CVBS output is distributedthrough IC201 (M74HC4052) to TV, AUX/VCR and VCR scarts. When VCR becomes active,audio and video signals are driven to TV and VCR scarts, which is activated by pin8 of VCRscart.

The program information is stored in 128Kbits EEPROM (24C128 – IC302) via I2C.

FRONT PANEL BOARD (TK507-2)

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To show program number, 4 digit 7 segment display (P2) is used on front panel board.They are driven by 97C52 (IC502) which is controlled by MC. The functional keys are Standby,Prog+, Prog-. IR module (IR01) is used for remote control.

FRONT PANEL PCBsFunctional Keys

Key Name Description 16FP05-2Key Name

Standby Standby SW101

Prog + Program Up SW102

Prog - Program Down SW103

SERVICE MENU INTERFACE

There is a service menu for service person which is accessed by entering “MAIN MENU”then pressing “9”, “2”, “9”, “5”, “2”, “6” keys on the remote control. You will see service menuon the screen. This menu consists of fifteen active lines.

RF Modulator System :

You can control RF modulator system at this line. RF modulator system option can beselected as Pal G or Pal I or Pal K type in software side by pressing left or right cursor key onthe remote control.

RF Modulator Type :

You can control RF modulator type at this line. RF modulator option can be selected asSharp or Samsung or LG type in software side by pressing left or right cursor key on the remotecontrol.

Tuner Type :

You can control Tuner type in software version at this line

Scarts :

You can control number of scarts in software version at this line

Reboot :

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You press OK button on the remote commander. Apparatus is restart.

Clear Database :

You press OK button on the remote commander. These settings reinitialize wholeEEPROM and store all programs erase.

L/R: DBCopy – OK: Upload PGM :

The object of this manual is to give necessary information and details to the user toUPLOAD the program table to the receiver through RS232.

The list of the necessary equipment is as follows:• Receiver and TV• PC with “Hyper Terminal” function,• RS232 serial communication cable (male to female modem cable).

Steps to be followed by the user are given below:1. Connect the serial communication cable between the RS232 outport of the receiver and the

serial communication port (COM1 or COM2) of the PC.2. Make sure that the PC is on and the receiver is in Power on mode.3. Run “Hyper Terminal” program of the PC from Start / Programs / Accessories /

Communications / Hyper Terminal menu.4. For a new connection, run Hypertrm.exe file.5. Give a name and choose an icon for the connection. (You do not need to make a new

connection every time. You can use this name for the future connections.)6. Choose communication port in the new coming window (COM1 or COM2) whichever you

have used in Step 1.7. Port settings should be as follows:

Bits per second : 38400Data Bits : 8Parity : NoneStop bits : 1Flow control : None

8. Now Hyper Terminal connection is established.9. Go to “L/R: DBCopy – OK: Upload PGM” line on the service menu and press “LEFT” or

“RIGHT” keys of remote control (for copying database to the receiver). Please wait until theprint statements on the Hyper Terminal screen end.

10. From “Transfer” menu, choose “Receive File”.11. Choose 1K Xmodem as protocol type.12. “L/R: DBCopy – OK: Upload PGM” line on the service menu and press “OK” key of remote

control. Then Receive on of Hyper Terminal window and enter a file name like(Program_table.pit) and press “OK” button. then You will see the progress on the PCscreen. Besides, on TV screen the receiver will count the downloaded packets.

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13. Wait for the transfer to be completed. Then, disconnect and exit from Hyper Terminalwindow.

Download PGM :

The object of this manual is to give necessary information and details to the user toupgrade the program table of the receiver through RS232.

The list of the necessary equipment is as follows:• Receiver and TV• PC with “Hyper Terminal” function,• RS232 serial communication cable (male to female modem cable).

Steps to be followed by the user are given below:1. Connect the serial communication cable between the RS232 outport of the receiver and the

serial communication port (COM1 or COM2) of the PC.2. Make sure that the PC is on and the receiver is in Power on mode.3. Go to “ Clear Database ” line and press “OK” key and then wait for twenty seconds (old

program table is deleted).4. Run “Hyper Terminal” program of the PC from Start / Programs / Accessories /





9. Now Hyper Terminal connection is established. From “Transfer” menu, choose “Send File”.10. Enter file name to be sent (program table).11. Choose 1K Xmodem as protocol type.12. Press Send button of Hyper Terminal window and then Go to “Download PGM” line on the

service menu and press “OK” key of remote control. You will see the progress on the PCscreen. Besides, on TV screen the receiver will count the downloaded packets.


Reset receiver by replugging in the mains cord of the set to the mains supply. Receiver will tuneto new program table.

Remote/Front Test :

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You press “OK” button remote commander to enter Remote/Front panel test then you cansee name of the button on the front panel or remote commander you pressed. By pressing Menubutton on the remote commander two times, you can exit.

7-Segment Display Test :

You press the OK key on the remote commander to start 7-segment display test. Youcan see the test pattern on the display.

System Diagnostic :

You press the OK key on the remote commander and show your IC information inapparatus main hardware

Development Team :

You press the OK key on the remote commander and Show your development team list

Upload Default Sat_Xpdrs :

This line can explain information under line

Download Default Sat_Xpdrs :

The object of this manual is to give necessary information and details to the user totransmission the program table and preset table to the receiver through RS232.

The list of the necessary equipment is as follows:• Receiver (master that sends the program table), TV• Receiver (slave that receives the program table), TV• RS232 serial communication cable (male to male modem cable).

Steps to be followed by the user are given below:1. Connect the serial communication cable between the RS232 outport of the receiver to other

receiver.2. Make sure that both receivers are in Power on mode.3. Open the “main menu” and press “929526” keys sequentially for both of the receivers, you

will see service menu on the TV screens.4. Go to “L/R: DBCopy – OK: Upload PGM” line on the service menu for master receiver and

press “LEFT” or “RIGHT” keys of remote control (for copying database to the receiver).5. Go to “Download PGM” line on the service menu for slave receiver6. “L/R: DBCopy – OK: Upload PGM” line on the service menu and press “OK” key of remote

control for master device. “Download PGM” line on the service menu and press “OK” key ofremote control for slave device. Besides, on TV screen the receiver will count thedownloaded packets.

7. Wait for the transfer to be completed the program table for both receivers.8. Power off both receivers then power on them.

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9. Open the “main menu” and press “929526” keys sequentially for both of the receivers, youwill see service menu on the TV screens.

10. Go to “Upload default Sat_Xpdrs” line on the service menu for master receiver.11. Go to “Download default Sat_Xpdrs” line on the service menu for slave receiver12. “Upload default Sat_Xpdrs” line on the service menu and press “OK” key of remote control

for master device. “Download default Sat_Xpdrs” line on the service menu and press “OK”key of remote control for slave device. Besides, on TV screen the receiver will count thedownloaded packets.

13. Wait for the transfer to be completed the preset table for both receivers.

Rs232 Test :

You connect the jumper to Rx output and Tx output. You press the “OK” key on theremote commander then you can see “tESt” at the front display. You release the “OK” key on theremote commander then you can see “Err” at the front display.

You can return to main menu by pressing “Menu” keys on the remote control

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SOFTWARE UPGRADE THROUGH RS232 FOR HAVİNG 7-SEGMENTDISPLAY MODELS

The object of this manual is to give necessary information and details to the user toupgrade the software of the receiver through RS232.

The list of the necessary equipment is as follows:Receiver and TVPC with “Hyper Terminal” function,RS232 serial communication cable (male to female modem cable).

Steps to be followed by the user are given below:1. Connect the serial communication cable between the RS232 out port of the receiver and the

serial communication port (COM1 or COM2) of the PC.2. Make sure that the PC is on and the receiver is in the Standby mode.3. Run “Hyper Terminal” program of the PC from Start / Programs / Accessories /





8. Now Hyper Terminal connection is established. From “Transfer” menu, choose “Send File”.9. Enter file name to be sent.10. Choose Xmodem1K as protocol type.11. Get the receiver out of standby mode using front panel keys just after pressing Send button

at the hyper terminal window. You will see the progress on the PC screen. Besides, frontpanel display of the receiver will count the downloaded packets.


Receiver will automatically start to operate

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SOFTWARE UPGRADE THROUGH RS232 FOR HAVING LED MODELS

The object of this manual is to give necessary information and details to the user toupgrade the software of the receiver through RS232.

The list of the necessary equipment is as follows:Receiver and TVPC with “Hyper Terminal” function,RS232 serial communication cable (male to female modem cable).

Steps to be followed by the user are given below:1. Connect the serial communication cable between the RS232 out port of the receiver and the

serial communication port (COM1 or COM2) of the PC.2. Make sure that the PC is on.3. Run “Hyper Terminal” program of the PC from Start / Programs / Accessories /





8. Now Hyper Terminal connection is established. From “Transfer” menu, choose “Send File”.9. Enter file name to be sent.10. Choose Xmodem1K as protocol type.11. Plug in the mains cord of the set to the mains supply just after pressing Send button at the

hyper terminal window. You will see the progress on the PC screen. Besides, front paneldisplay of the receiver will count the downloaded packets.


Receiver will automatically start on standby mode. After software initialisation(it takes 5 second)finished you can turn on your digital set-top box by pressing one of the standby button, up/downor numeric buttons on remote control or up/down/standby button on the front panel.

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BILL OF MATERIALS

Ves.Code Description

20092206 MAINBOARD (MAN) SHARP20092207 MAINBOARD (RAD) SHARP20092208 MAINBOARD (SMD) SHARP30000294 CAP SMD 100NF 50V K (0805) C427 C412 C413 C414 C244 C438 C26530000814 RES SMD 1/10W 820R J R225 R233 R240 R24630001734 JUMPER SMD (0805) S107 S108 S415 S416 S417 S418 S41930001968 FERRITE BEAD (0805) BLM21B201S L106 L301 L302 L303 L304 L407 L400 L409 L410 L414 L208 L417 L418 L419 L420 L4 21 L422 L42330007366 IC TSH22 (SO8) tape&reel IC10330007378 IC LM 833(SO8) tape&reel IC50130010689 DIODE VAR BB133 SMD D100 D10130010780 IC 74HCU04 (SO14) tape&reel IC10230010796 IC 24C128 SMD tape&reel IC30230010817 IC MAX232 (SOIC16) IC10130010822 IC M74HC4052 (SO16) tape&reel IC200 IC20130012509 RES SMD 1/16W 100K J (0603) R502 R50330012510 RES SMD 1/16W 100R J (0603) R108 R140 R147 R148 R254 R255 R411 R280 R28130012551 TR BC847B SMD Q102 Q103 Q104 Q200 Q201 Q202 Q203 Q204 Q205 Q400 Q403 Q500 Q501 Q502 Q503 Q504 Q505 Q506 Q209 Q215 Q507 Q21730012552 TR BC857B SMD Q100 Q101 Q105 Q206 Q207 Q208 Q212 Q40130012559 CAP SMD 10PF 50V D COG (0603) C204 C208 C212 C21630012560 CAP SMD 100PF 50V J (0603) C236 C22030012564 CAP SMD 18PF 50V J (0603) C113 C11630012567 CAP SMD 220PF 50V J (0603) C232 C234 C235 C243 C24630012568 CAP SMD 270PF 50V J (0603) C502 C50430012570 CAP SMD 330PF 50V J (0603) C11930012573 CAP SMD 47PF 50V J (0603) C205 C206 C209 C210 C213 C214 C217 C21830012581 CAP SMD 1NF 50V K R (0603) C221 C222 C228 C230 C238 C239 C241 C400 C401 C432 C433 C434 C435 C436 C24030012582 CAP SMD 10NF 50V K R (0603) C100 C102 C104 C107 C114 C115 C40930012583 CAP SMD 1.5NF 50V K (0603) C26030012608 CAP SMD 27PF 50V J CH (0603) C515 C51630012616 CAP SMD 2.7NF 50V K B (0603) C511 C51230012641 RES SMD 1/16W 10K J (0603) R113 R114 R118 R119 R120 R121 R142 R300 R400 R401 R283 R512 R513 R514 R527 R29230012650 RES SMD 1/16W 15K J (0603) R28230012657 RES SMD 1/16W 1K J (0603) R134 R208 R211 R212 R213 R250 R251 R252 R253 R266 R267 R180 R518 R259 R214 R133 R13530012658 RES SMD 1/16W 1M J (0603) R12330012659 RES SMD 1/16W 2.2K J (0603) R110 R111 R402 R516 R53930012667 RES SMD 1/16W 220K J (0603) R504 R51030012668 RES SMD 1/16W 220R J (0603) R248 R519 R520 R521 R522 R523 R524 R525 R54030012669 RES SMD 1/16W 22K J (0603) R128 R137 R138 R139 R218 R219 R220 R256 R257 R276 R277 R278 R279 R136 R287 R216 R273 R272 R271 R286 R290 R29130012673 RES SMD 1/16W 270R J (0603) R24930012677 RES SMD 1/16W 3.3K J (0603) R506 R509 R20930012684 RES SMD 1/16W 330R J (0603) R224 R231 R238 R24530012685 RES SMD 1/16W 33K J (0603) R404 R501 R50730012692 RES SMD 1/16W 4.7K J (0603) R100 R109 R117 R505 R508 R526 R528 R529 R530 R531 R532 R533 R221 R228 R235 R242 R536 R537 R538 R541

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30012694 RES SMD 1/16W 470K J (0603) R124 R12530012695 RES SMD 1/16W 470R J (0603) R227 R232 R24130012696 RES SMD 1/16W 47K J (0603) R511 R500 R12630012698 RES SMD 1/16W 5.6K J (0603) R51530012702 RES SMD 1/16W 560R J (0603) R200 R201 R202 R203 R204 R205 R206 R20730012707 RES SMD 1/16W 680R J (0603) R223 R229 R237 R243 R258 R222 R230 R236 R24430012709 RES SMD 1/16W 7.5K J (0603) R217 R269 R27030012712 RES SMD 1/16W 8.2K J (0603) R127 R12930012713 RES SMD 1/16W 75R J (0603) R143 R226 R234 R239 R24730012800 IC DAC CS4335 tape&reel IC50030012982 RES SMD 1/16W 10R J 0603 R288 R28930012985 JUMPER SMD 0603 S201 S203 S205 S300 S302 S304 S400 S401 S403 S404 S407 S411 S412 R11630012986 RES SMD 1/16W 68R J 0603 R26030014022 RES SMD 1/16W 47R J (0603) R103 R104 R105 R106 R130 R131 R144 R145 R51730014088 IC SDRAM 4MX16 100MHZ tape&reel IC30030014128 RES SMD 1/16W 33R J (0603) R112 R122 R132 R149 R151 R413 R414 R415 R184 R419 R420 R421 R422 R423 R424 R425 R41630014342 IC TS87C52X2-MCB tape&reel IC50230014344 TR NDS8947 IC40230014442 RES SMD 1/16W 20K F(0603) R101 R10230014714 IC DS1811(RESET IC) IC40030014952 IC FLASH 8MB (TOP BOOT) tape&reel IC30130016427 IC STI5518 IC10030016654 CAP SMD 100NF 16V K R (0603) C108 C109 C110 C111 C112 C117 C120 C122 C123 C124 C125 C127 C128 C129 C130 C131 C133 C134 C135 C136 C138 C139 C201 C203 C223 C252 C253 C254 C255 C300 C302 C303 C305 C306 C307 C308 C309 C310 C311 C402 C403 C404 C405 C406 C407 C408 C410 C411 C418 C420 C421 C422 C423 C428 C506 C507 C509 C510 C225 C415C513 C430 C142 C269 C437 C23330017143 COIL SMD 22UH (2520) L100 L101 L102 L103 L200 L201 L202 L203 L204 L207 L300 L405 L500 L501 L20630017653 RES SMD NET 1/16W 47RX4 J (0603) R153 R154 R155 R156 R157 R158 R159 R160 R161 R162 R163 R164 R165 R166 R167 R168 R169 R17030018776 PCB 16MB07E350010922 LABEL FRONT ''YESIL NOKTA'' (ÇAP 1 CM )30000345 CAP EL 10UF 50V M C101 C103 C105 C106 C256 C257 C258 C301 C503 C50530000352 CAP EL 100UF 16V M C118 C121 C126 C132 C304 C50830000353 CAP EL 100UF 25V M C200 C245 C247 C248 C249 C250 C251 C207 C211 C215 C21930000355 CAP EL 100UF 50V M C259 C261 C26230000362 CAP EL 1UF 50V M C517 C51830000375 CAP EL 220UF 16V M C202 C263 C26430000384 CAP EL 2.2UF 50V M C500 C50130000395 CAP EL 47UF 6.3V M (4*7MM) C416 C417 C42930000400 CAP EL 47UF 50V M C424 C425 C426 C419 C51430000407 CAP EL 470UF 16V M C31230001452 TR BC327 Q21630011011 COIL FIXED 22UH J RAD L401 L402 L403 L404 L415 L20530000769 RES CF 1/2W 680R J R40630001422 TR BD238 Q40230001753 XTAL 8MHZ X50030001851 CONN MALE 7P 2.5MM PL40130006710 CONN MALE 11P TOP WHITE PL40030007040 JACK D-SUB 9P JACK_D30007367 XTAL 27MHZ R=20 OHM X10030010700 DIODE BYV28-200 3.5A/200V 90A D40030010902 HEADER 10X2(2,54MM) PL100

SERVICE MANUAL

Rev 1.0 21.10.02 16:23 Page 50

30010921 DOUBLE-DECK SCART SOCKET PL20030014089 MODULATOR RF TAMC_G001D TU20030014123 TUNER NIM BS2F7VZ0180 TU40030014191 CONN MALE 12P TOP WHITE PL50030014195 JACK RCA 3P-DVB- JK130016742 RES MF 1/2W 0.82R J R40335000006 SINGLE BATT.CONTACT (-) RC200050010759 LABEL SERIAL NO (UNIVERSAL)20092367 POWERBOARD CHS.DVB-4 (MAN)20092368 POWERBOARD CHS.DVB-4 (RAD)20092369 POWERBOARD CHS.DVB-4 (AXI)20092370 POWERBOARD CHS.DVB-4 (SEQ)30000452 RES CF 1/4W 10R J R630000471 RES CF 1/4W 10K J R14 R23 R29 R30 R34 R3530000477 RES CF 1/4W 100K J R4330000583 RES CF 1/4W 220R J R1030000590 RES CF 1/4W 2.2K J R2630000599 RES CF 1/4W 220K J R4230000712 RES CF 1/4W 470R J R530000718 RES CF 1/4W 4.7K J R13 R28 R3130000736 RES CF 1/4W 51R J R11 R4430000767 RES CF 1/4W 68R J R2030000769 RES CF 1/2W 680R J R1230000790 RES CF 1/4W 6.8R J R4030000820 RES CF 1/4W 82K J R2730000888 RES MF 1/4W 15K F R930000985 RES MF 1/4W 47K F R22 R2430001028 RES MF 1/4W 82K G R25 R3230001284 DIODE 1N4148 0.15A/100V 0.5A D530001303 DIODE BYD33M 1A/1000V 20A D930001318 DIODE BA159 1A/800V 20A D630001329 DIODE 1N4007 1A/1000V 30A D1 D2 D3 D4 D1430001377 DIODE ZENER 33V UZT 33B D1330002583 SHORT CIRCUIT # 0.6MM GR 0,875 J2 J4 J1 J3 J5 J6 D1530007200 RES MF 1/4W 10K F R7 R8 R2170000593 SEQUENCER TAPE 5.8mmx2700m M 0,81030018871 PCB 16PW07E330000225 CAP CER 220PF 50V J SL C3730000244 CAP CER 330PF 50V J SL C2530000269 CAP CER 68PF 50V J CH C2730000283 CAP CER 1NF 50V K B C26 C2930000287 CAP CER 10NF 50V K B C2830000295 CAP CER 100NF 50V Z F C12 C24 C32 C5 C3030000352 CAP EL 100UF 16V M C10 C11 C3330000371 CAP EL 22UF 50V M C1330000400 CAP EL 47UF 50V M C3430000431 CAP CER 100PF 1KV M C35 C36 C3830001454 TR BC548B Q2 Q6 Q7 Q8 Q9 Q1050010759 LABEL SERIAL NO (UNIVERSAL)30000094 CAP MKT 220NF 275V M AC C1 C230000359 CAP EL 1000UF 16V M C8 C930000361 CAP EL 1000UF 35V M C1930000377 CAP EL 220UF 35V M C15 C1630000402 CAP EL 47UF 100V M C1730000409 CAP EL 470UF 25V M C2030000423 CAP EL 47UF 400V M C3

SERVICE MANUAL

Rev 1.0 21.10.02 16:23 Page 51

30000440 CAP CER 2.2NF 4KV M C2130000525 RES CF 1/2W 1.5K J R4130000603 RES CF 1/2W 2.2M J (400V) R130001422 TR BD238 Q130001446 TR BD235 Q530001501 IC MC7812CT IC530001506 IC TL431 IC330001731 FUSE 2.5A 250V 5*20MM F130001792 CONN.MALE 2P MOLEX PL130002103 LINE FILTER 2*32MH (AK19) L630006710 CONN MALE 11P TOP WHITE PL230010700 DIODE BYV28-200 3.5A/200V 90A D8 D10 D1130010708 DIODE ZENER 200V D1630011450 COIL CHOKE 22UH RADIAL L1 L2 L3 L530012864 IC TOP233Y IC130013160 COIL ZBF116T-01A L7 L830014414 TRF SMPS DVB TR130015087 IC TCET1102G IC230015124 IC LM358N (ANALOG SAT) IC430017602 DIODE SCHOTTKY 3A D735000136 TK79-A (GRAY)35000158 NUT C ZN BOTTOM M335000165 RONDELA C ZNSY 3*6*04 (M3)35000181 C ZN YSMB M3*835002781 TR SOGUTUCU (10X19X35 MM)50010759 LABEL SERIAL NO (UNIVERSAL)20103681 TOUCH B.ASSY DVB-4 RED DS.30000345 CAP EL 10UF 50V M CT0130000459 RES CF 1/4W 100R J RT0330001670 PREAMPLIFIER TFMS5360 IR0130002178 SWITCH TACT SKHHLU X1 X2 X330002583 SHORT CIRCUIT # 0.6MM GR 0,250 J1 J230011017 DISPL.SEGMENT A-574E (H-96)B/W P230011068 PCB TK507-230018914 CONN ASSY 7P 15CM W/FERRITE P130018915 CONN ASSY 12P 13CM W/FERRITE KON0420105468 R/C DVB2 SERVISAT (S) (SILVER)20062060 UKV B.ASSY. (MAN)20062061 UKV B.ASSY. (SMD)30000464 RES SMD 1/10W 100R J R10130000475 RES SMD 1/10W 10K J 0805 R10430000499 RES SMD 1/10W 1.2K J (0805) R10230000546 RES SMD 1/10W 1.5R J (0805) R10630000727 RES SMD 1/10W 47K J (0805) R10530000778 RES SMD 1/10W 6.8K J 0805 R10030002731 RES SMD 1/10W 68R J R10330002735 IC SAA3010T IC130015100 PCB 16UV04-130000395 CAP EL 47UF 6.3V M (4*7MM) C10030001452 TR BC327 Q10230001454 TR BC548B Q10130002733 LED INFRARED IR333 D10030011443 XTAL REZ 429KHZ (0.9MM) X10035000006 SINGLE BATT.CONTACT (-) RC200035000007 SINGLE BATT.CONTACT (+) RC200035000003 DOUBLE BATTERY CONTACT UKV-900

SERVICE MANUAL

Rev 1.0 21.10.02 16:23 Page 52

35000210 S C ZNSY YSMB 2.9*6.540006044 LENS RCDVB (I)40008432 RUBBER PAD TRP38 (RCDVB) R0140009550 BOTTOM COVER RCDVB (I) (SILVER)40009561 BATTERY COVER RCDVB (I) (SILVER)40011111 TOP CVR.RCDVB2 UK750 SERVISAT (S) (SLV)50010561 NYLON (8CM *25CM ) KG 0,00230011787 POWER CORD ASSY.(2.4MT W/FTZ)-SATELLITE-30016831 CONN ASSY 11P 10CM W/FERRITE35000228 C ZNSY YSMB 2.9*9.535002504 RONDELA DKP 14*9.5*0.635002530 C ZNSY YSMB 2.9*635002531 C ZNSY YSMB 2.9*835002560 3/8 UNEF-2A35005664 TOP CVR.DVB-4(M.SLV)(LARGE)FF166/7837 ST40005461 FOOT RUBBER RF-002 10*2.740005474 CABLE HOLDER 5RF-440010912 DVB 4 LARGE BOTTOM COVER40011113 FRONTA.DVB-4 SERVISAT DSR 2003 3800(SLV)50010560 NYLON (38CM *42CM ) KG 0,01650010687 BIG CARTON BOX (OUT)(5'L#)50010759 LABEL SERIAL NO (UNIVERSAL)50010922 LABEL FRONT ''YESIL NOKTA'' (1 CM )50010940 12MM TAPE50013519 LABEL BARCODE (60x60) TRIPLE50014939 LABEL BARCODE (80x30) OUTBOX50018038 SNOW BOX RECEIVER LEFT50018040 SNOW BOX RECEIVER RIGHT50029712 PASTEBOARD DVB-4 STD50029717 PROG.LIST DVB-4 SERVISAT/FRA50029718 PROG.LIST.DVB-4 SERVISAT/ARABIC50029719 PASTEBOARD ET#.DVB-4 SERVISAT DSR200350029720 USER_MAN.DVB-4 SERVISAT DSR 2003/FRA50029721 USER_MAN.DVB-4 SERVISAT DSR 2003/ARABIC50029722 TAG.DVB-4 SERVISAT DSR 2003/ENG

SERVICE MANUAL

Rev 1.0 21.10.02 16:23 Page 53

vestel-dvb-4_sat-3600_[ET][1]

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