Top Banner
USART 1 USART
47

USART-Universal Synchronous A Synchronous Receiver Transmitter

Apr 08, 2015

Download

Documents

Brety Angel
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Page 1: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

1

USART

Page 2: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

2

Dependencies PMC has to be programmed 1st for USART to work PIO Controller has to be programmed for the pins to behave as intended The USART configuration can be done before enabling the USART clock Depending on application needs, the USART clock can be stopped when not

needed after restart the USART resumes its operations where it left off

Page 3: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

3

USART Features Independent Programmable Baud Rate Generator 5- to 9-bit Full-duplex Synchronous Asynchronous Serial Communications Hardware Handshaking RTS-CTS Modem Signal Management DTR-DSR-DCD-RI RS485 with Driver Control Signal ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards IrDA Modulation and Demodulation Communication at up to 115.2 Kbps MSB or LSB support 5 Parity mode Time Guard generation Break generation Framing Error Test Modes

- Remote Loopback, Local Loopback, Automatic Echo

Page 4: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

4

USART: Block Diagram Common USART Signals:

- SCK Serial Clock- RXD Receive Data- RTS Request To send- TXD Transmit Data- CTS Clear To Send

Modem Signals:- DTR Data Terminal Ready- DSR Data Set Ready- DCD Data Carrier Detect- RI Ring Indicator

Page 5: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

5

USARTs on AT91SAM7S64 2 USARTs embedded:

- USART0, USART1 Full Modem Line Support ONLY on USART1

- Each USART have its own Baud Rate generator- Modem Signals available only on USART1

Page 6: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

6

Baud Rate Generator The baud rate generator provides the bit period clock named Baud Rate

clock Based on a 16-bit divider, programmable thanks to CD field of the

US_BRGR (Baud rate Generator Register) The clock source is programmable through the USCLKS field in the US_MR

(Mode Register): - AT91SAM7S64 Master Clock MCK- A division of MCK (CD field) - External Clock provides on SCK

Baud Rate Error : - In most of the cases needs to be < 5%- In IrDA mode needs to be < 1.87%

Page 7: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

7

USART Modes vs Baud Rate Calculation

Synchronous:

Asynchronous:

ISO7816:- ISO7816 Bit rate

- ISO7816 bit rate is the duration of a bit in number of ISO7816 clock cycles- ISO7816 Clock is provided to the USART SCK pin to feed the SMART card clock- Fi_Di_Ratio is defined in accordance to ISO7816 standard and the Smart Card

application user. Note: On reset Fi_Di_Ratio is set to 372 value

Page 8: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

8

Baud Rate Generator

Page 9: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

9

Asynchronous Receiver Mode Valid Start Detection :

- A LOW level on RXD is interpreted as a valid START bit if it is detected for more than 8 cycles of the sampling clock, which is 16 times the baud rate when OVER =0

- OVER=1 , 4 cycles of the sampling clock

Page 10: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

10

Asynchronous Receiver Mode The RXD line is sampled by the Receiver US_MR

- SYNC field =0- OVER 1-bit field

• =0 RXD line over samples 16 times the Baud Rate Clock

• =1 RXD line over samples 8 times the Baud Rate Clock

ONLY 1 STOP bit is read As soon as the STOP bit is sampled, the receiver is looking for a new valid

START bit

Page 11: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

11

Synchronous Receiver Mode The RXD line is sampled at each rising edge of Baud Rate Clock Baud Rate Clock Max = MCK Synchronous mode allows HIGH speed transfer US_MR (SYNC 1-bit field =1) Valid START bit is a LOW level detected on RXD

Page 12: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

12

Transmitter Mode

Start bit, data bits, parity bit and stop bits are- Shifted on falling edge of the Baud Rate clock- Sampled at each rising edge of Baud Rate Clock

Page 13: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

13

IrDA Mode Half Duplex point to point wireless communication USART embeds infrared modulator and demodulator compliant with IrDa

specification version 1.1 Data transfer from 2.4Kb/s up to 115.2Kb/s IrDA mode activated by setting USART_MODE field to value 0x8 in the US_MR Use the same logic as the ISO7816, the IrDA activation is mandatory by setting

a non zero value to the Fi_Di field (US_FIDI register) IrDA Filter Register (US_IF) configures the demodulator filter

Page 14: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

14

IrDA Modulation Modulator is based on IrDA Transmitter Based on Return to Zero Inverter (RZI) modulation “0” is represented a a light pulse with a duration of 3/16 of a bit time

Page 15: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

15

IrDA Demodulation Demodulator is based on IrDA Receiver Non zero value of US_IF field allows a 8-bit counter to validate that the RX line

is kept to value zero during a time of US_IF x 1/MCK - RX line is NOT asserted during this time the counter restart with US_IF value and

count down for reach 0.- RX line is asserted and after the data bits (pulse) on RX are validated. 

Page 16: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

16

IrDA Mode Specific Registers US_IF: Infra-Red

- Sets the filter of the IrDA demodulator- IrDA demodulator available on the receiver part- IRDA_FILTER 8-bit field- determine the duration necessary to valid the RX line

US_FIDI: - FI_DI_RATIO 11-bit field- 1 – 2047 value range- MUST be set to a non-zero value

Page 17: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

17

ISO7816 Mode USART interface for Smart Cards and Security Access Module ISO7816 T=0 and T=1 protocols supported Half Duplex Mode TXD line is bi-directional Fixed Data Format ( Automatic set up of the corresponding fields)

- 8 data bits- Even parity- 1 or 2 stop bit

Page 18: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

18

ISO7816 Mode

ISO7816 T=0 without parity error

As there is no parity error the RXD line is set to one during the time guard and allow the next

character to be sent

US_MR settings

MAX_ITERATION CLKONBSTOP USART_MODE

ISO7816 mandatory fields

USCLKS0x4 T=0, 0x6 T=10x0 or 0x10x0 or 0x20x1 min , max 0x7field value: 0x1

ONLY for T=0

INACK OVERMSBFoptional fields

Page 19: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

19

ISO7816 Mode ISO7816 T=0 with parity error and NACK generation

RXD line is set to zero during the time guard NACK is activated and add one bit after the time guard Repetition of the character is done according to the MAX_ITERATION field

value in the US_MR The Receiver does not put the erroneous value on the US_RHR register PARE field is activated in the US_CSR If Inhibit NACK is set on the US_MR, the Error is not driven on the I/O line and

the INACK is set on the US_CSR

NACK

Page 20: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

20

ISO7816 Mode Specific Registers US_NER: Number of Errors

- NB_ERRORS 8-bit field gives the total number of errors that occurred during an ISO7816 transfer

- 8- bit counter- automatically clears when read

US_FIDI: - FI_DI_RATIO 11-bit field- 1 – 2047 value range :completes the Baud Rate set up- The clock provided on SCK is divided by FI_DI_RATIO

FI_DI Ratio Example MCK=SCK=18.432 Mhz CD=5- SmartCard needed Clock= 3.686Mhz = MCK/CD- ISO7816_ClockBit Rate= ISO7816_Clock/Fi_Di_Ratio= 38400- ISO7816_Clock => 18.432/5=3.686Mhz for an equivalent baudrate of 38400 we

have 38400=MCK/CD/Fi_Di => Fi_Di = 3.686M/38400=96

The bit rate is the duration of a bit in number of ISO7816_Clock

Page 21: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

21

RS485 Mode USART_MODE 2-bit field of US_MR set to 0x01 value RS485 mode enables line driver control USART as the Same behavior than in Asynchronous or synchronous

Mode RTS pin is driven HIGH when the Transmitter is operating

- TXEMPTY flag controls RTS line behavior

Page 22: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

22

RS485 Mode RTS pin is driven at inverse level than the TXEMPTY bit RTS in HIGH level means that a transmission is in progress Below an example with Timeguard set

Page 23: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

23

Modem Mode USART_MODE in the Mode Register (US_MR) is set to the value 0x3. In Modem Mode :

- USART acts as in asynchronous mode - All the asynchronous parameters are available- provides the current state of the control lines from the modem to the CPU

TXD RTS: Request To Send DTR: Data Terminal Ready RXD CTS: Clear To Send DSR: Data Set Ready DCD: Data Carrier Detect RI: Ring Indicator

Page 24: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

24

Modem Mode USART acts as a Data Terminal Equipment USART drives DTR and RTS signals USART detects a level change on

- DSR means DSRIC bit of the Status Register is set and can trigger an interrupt- DCD means DCDIC bit of the Status Register is set and can trigger an interrupt- CTS means CTSIC bit of the Status Register is set and can trigger an interrupt- RI means RIIC bit of the Status Register is set and can trigger an interrupt

CTS to HIGH level disable the Transmitter, once the character transmission is completed

Page 25: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

25

USART Test Modes 3 USART Test Modes Allow on-board diagnostics

Normal Mode - RXD pin on the receiver input - TXD pin on the the transmitter output

Page 26: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

26

USART Test Modes Automatic Echo Mode: Bit by bit retransmission

- A bit is received on the RXD pin is sent to the TXD pin- Programming the transmitter as no impact on TXD - Receiver is active

Page 27: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

27

USART Test Modes Local Loop Back

- Direct Connection between the transmitter output and the receiver input- TXD and RXD pins are not used:

• RXD pin has no effect on the receiver

• TXD pin is continuously driven high

Page 28: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

28

USART Test Modes Remote Loop Back Mode: bit-by-bit retransmission.

- Direct connection of the RXD pin to the TXD pin- Transmitter and the Receiver are disabled and have no effect

Page 29: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

29

Multidrop Mode PAR 3-bit field of US_MR set to 11x value DATA and ADDRESS characters follow the rule:

- Parity bit set to ONE means ADDRESS character- Parity bit set to ZERO means DATA character

Receiver- PARE bit of the Status Register is SET while receiving an address character- No parity error can be detected- PARE bit reset when active RSTSTA bit of the Control register

Transmitter- SENDA bit need to be SET in the Control Register while sending an address

character (US_THR)- SENDA to level zero, a data character will be write in the US_THR

Page 30: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

30

USART Options USART Options:

- Parity- Break- Timeguard- Time-Out

USART options can be used when using the USART in SYNCHRONOUS and ASYNCHRONOUS modes

Timeguard and Time-out delays are limited by the Baud rate

Page 31: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

31

Framing Error Can be detected only on Receiver side

- The STOP bit is detected to level ZERO- FRAME bit is set on the Status Register (US_CSR)

• On the middle of the stop bit

FRAME is cleared by writing the RSTSTA bit of the Control Register (US_CR)

Page 32: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

32

Parity Options 5 parity modes:Odd, Even, Mark, Space, None Even parity example:

- If the number of set bits is even, it sets the parity bit to 0; if the number of set bits is odd, it sets the parity bit to 1. In this way, every data has an even number of set bits. On the receiving side, the device checks each byte to make sure that it has an even number of set bits. If it finds an odd number of set bits, the receiver knows there was an error during transmission

Below Parity True table associated with an example

Page 33: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

33

Parity Options Configurable through the PAR (3-bit) field of the US_MR Parity Error detection:

- sets the PARE (Parity Error) bit in US_CSR PARE bit cleared by writing US_CR with the RSTSTA bit at 1

Page 34: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

34

Timeguard Options Allows transmission with SLOW remote devices The Transmitter insert an ‘idle state’ between 2 characters

- ‘idle state’ is a HIGH level on the TXD line- Duration of the ‘idle state’ is programmable through the Timeguard register

(US_TTGR):• TG x Bit Period

• TG is 8-bit field, programmable up to 255 value

• TG =0 means no Timeguard programmed

Page 35: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

35

Timeguard Options Change TXRDY and TXEMPTY normal behavior TXRDY rises ONLY at the start bit of the next character TXRDY remains to ZERO during Timeguard if the character is written in

US_THR TXEMPTY rises at the end of the character transmission and after the

Timeguard

Page 36: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

36

Break Options Transmit a BREAK condition on the TXD line Break TXD line is driven to Low level:

- Duration, at least one complete character transmission- Break equivalent frame is a zero character with parity and stop bit at 0- Only one break a time

The Transmission is Stopped until the Break is completed and cleared- Completed: duration constraints- Cleared: STPBRK bit set in the US_CR, allow the TXD line to transmit

After the Break, TXD line remains HIGH- During a minimum of 12 bit times or Timeguard value if set to a upper value that 12- Ensure that the Remote receiver detect the end of the Break to prevent the lose of t

he next sent character

Page 37: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

37

Break Options Transmit a BREAK condition on the TXD line USART configuration: 8-bit data, parity enable, 1 stop bit, no Timeguard

- Start Break active at the END of the current Character transfer- Stop Break is active ONLY after the Minimal Break duration - Minimal Break Transmission duration = Character transmission duration- End of the Break duration = 12 bit time

Page 38: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

38

Time-Out Options Allow the Receiver to handle variable length frames Receive a Time-Out condition on the RXD line RXD line is driven to HIGH level:

- Time-out delay period is set on the TO 16-bit field of the Receiver Time-Out (US_RTOR)

- Time-Out Delay = T0 x Bit Time- A 16-bit counter start decrement from the TO value to 0

Each character received re-start the Time-Out Counter End of the Time-Out, the TIMEOUT bit is set in Status register (US_CSR) On the Control Register:

- RETTO-bit, Reload and Start Time-Out allows a periodic interrupt while no character received

- STTO-bit, Start Time-out. One character must be received before active the Time_Out, and an interrupt is performed when Time-Out occurs

Page 39: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

39

Hardware Handshaking Option Flow control by connected

- RequesToSend RTS - ClearToSend CTS

Same behavior than in Asynchronous or synchronous Mode PDC channels are mandatory

Page 40: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

40

Hardware Handshaking Option

Transmitter- CTS line driven HIGH disable the

Transmitter- CTS is driven HIGH after completed

the character transmission

Receiver- RTS line is driven HIGH means receiver disable and the PDC Receive Buffer is Full- Receiver Enables RTS line is driven LOW

Page 41: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

41

USART & Peripheral DMA Controller Kind of DMA dedicated to a peripheral operation Minimum CPU overhead/per transfer : 2 cycles Increase the microcontroller performance Decrease the power consumption Several channels: Receiver,Transmitter Integrated PDC user interface on USART memory space:

- 32-bit Transmitter and Receiver Pointer Registers• Buffer Address

- 16-bit Transmitter and Receiver Counter Registers• Buffer Size

- 32-bit Transmitter and Receiver NEXT Pointer Registers• Buffer Address

- 16-bit Transmitter and Receiver NEXT Counter Registers• Buffer Size

Page 42: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

42

USART PDC Register Locations Control registers start at peripheral address offset by 0x100

- 0x100 : US_RPR : USART Receive Pointer Register, Read/Write- 0x104 : US_RCR : USART Receive Counter Register, Read/Write- 0x108 : US_TPR : USART Transmit Pointer Register, Read/Write- 0x10C : US_TCR : USART Transmit Counter Register, Read/Write- 0x110 : US_RNPR : USART Receive Next Pointer Register, Read/Write- 0x114 : US_RNCR : USART Receive Next Counter Register, Read/Write- 0x118 : US_TNPR : USART Transmit Next Pointer Register, Read/Write- 0x11C : US_TNCR : USART Transmit Next Counter Register, Read/Write- 0x120 : US_PTCR : USART PDC Transfer Control Register, Write-only- 0x124 : US_PTSR : USART PDC Transfer Status Register, Read-only

USART0 control registers for SAM7S start at address 0 xFFFC 0000 USART0 PDC control registers start at address 0 xFFFC0100 USART1 control registers for SAM7S start at address 0 xFFFC 4000 USART1 PDC control registers start at address 0 xFFFC 4100

Page 43: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

43

USART Interrupts USART Interrupt Enable Register US_IER (Write Only)

0 = No effect

1 = Enable USART Interrupt Disable Register US_IDR (Write Only)

0 = No effect

1 = Disable USART Interrupt Mask Register US_IMR (Read Only)

0 = Not enabled

1 = Enabled

TXEMPMTY9

ITERATION10

NACK RXBUFF13 12RIIC

16

DSRIC17

DCDIC18

CTSSIC19

US_IER, US_IDR, US_IMR

TXRDY RXRDY1 0

RXBRK2

ENDRX3

OVRE ENDTX5 4

RXBUFF6

FRAME6

PARE7

TIMEOUT9

Page 44: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

44

USART Interrupts RXRDY: RXRDY TXRDY: TXRDY RXBRK: Receiver Break ENDRX: End of Receive Transfer ENDTX: End of Transmit TXBUFE: Buffer Empty RXBUFF: Buffer Full OVRE: Overrun Error FRAME: Framing Error PARE: Parity Error TIMEOUT: Time-out TXEMPTY: TXEMPTY ITERATION: Iteration NACK: Non Acknowledge RIIC: Ring Indicator Input Change DSRIC: Data Set Ready Input Change DCDIC: Data Carrier Detect Input Change CTSIC: Clear to Send Input Change

Modem Mode Related

PDC Related

Page 45: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

45

USART & AT91 Software Libraries USART Standalone software examples are provided USART Standard Modes example

- Send / receive Characters- With the PDC features activated or not- Interrupt managements

AT91SAM7S64.h file describes all the peripherals and their dedicated registers lib_AT91SAM7S64.h file contains ‘inline more common USART functions:

- PIO configuration- USART Clock activation through the Power Management Controller - Baud Rate function

Page 46: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

46

USART & AT91 CD-ROM Tools USART Utility Javascript tools: Setting of USART Baud Rate according to the:

- Mode required- Master Clock source- Baud Rate required- Gives the value to set in the USART mode register, and specific register according

to USART Mode

Page 47: USART-Universal Synchronous A Synchronous Receiver Transmitter

USART

47

USART Summary The USART support all following facilities: Several modes supported:

- Asynchronous, Synchronous, Modem, ISO7816, IrDA, RS485, 3 test modes 5 to 9 byte length data length MSB or LSB support 1, 1.5 or 2 Stop bits 5 parity mode Over sampling control Time Guard generation Break generation Framing Error Hardware Handshaking Time-Out