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DMA CONTROLLER 8257 Features: It is a 4-channel DMA. So 4 I/O devices can be interfaced to DMA It is designed by Intel Each channel have 16-bit address and 14 bit counter It provides chip priority resolver that resolves priority of channels in fixed or rotating mode.
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Page 1: Unit 3 PART2 Dmacontroller8257

DMA CONTROLLER 8257Features:It is a 4-channel DMA. So 4 I/O devices can be interfaced to DMA It is designed by Intel Each channel have 16-bit address and 14 bit

counter It provides chip priority resolver that resolves

priority of channels in fixed or rotating mode. It provide on chip channel inhibit logic.

Page 2: Unit 3 PART2 Dmacontroller8257

• It generates a TC signal to indicate the peripheral that the programmed number of data bytes have been transferred.• It generates MARK signal to indicate

the peripheral that 128 bytes have been transferred.• It requires single phase clock.The maximum frequency is 3Mhz and

minimum frequency is 250 Hz.

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• It execute 3 DMA cycles 1.DMA read 2.DMA write 3.DMA

verify.• It provide AEN signal that can be used

to isolate CPU and other devices from the system bus.• It is operate in two modes. 1.Master Mode 2.Slave Mode

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Need for DMA• In the applications where the microprocessor/CPU is to transfer bulk

data, it may be a waste of time to transfer the data from source to destination using program controlled data transfer or Interrupt driven data transfer.

• The alternate way of transferring the bulk data is the Direct Memory Access (DMA) technique in which the data is transferred under the control of a DMA controller, after it is properly initialized by the microprocessor/CPU.

• A DMA controller is designed to complete the bulk data transfer task much faster than the CPU.

• A DMA controller may also be used to transfer data from the system memory to a video RAM of a CRT display.

• Data transfer between CPU & FDC may be controlled using DMA controller.

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8257 BLOCK DIAGRAM

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Description

• It containing Five main Blocks.1. Data bus buffer2. Read/Control logic3. DMA channels. (CH0 – CH3)4. Control logic block5. Priority resolver

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DATA BUS BUFFER:• It contain tristate ,8 bit bi-directional buffer.• Slave mode ,it transfer data between

microprocessor and internal data bus.• Master mode ,the outputs A8-A15 bits of

memory address on data lines (Unidirectional).READ/WRITE CONTROL LOGIC:• It control all internal Read/Write operation.• Slave mode ,it accepts address bits and control

signal from microprocessor.• Master mode ,it generate address bits and

control signal.

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8257 register selection

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FIRST/LAST FLIP FLOP:• 8257 have 8bit data line and 16 bit address line.• A0-A3 lines are used to distinguish between

registers ,but they are not distinguish lower and higher address.

• It is reset by external RESET signal.• It is also reset by whenever mode set register is

loaded.• So program initialization with a dummy (00 H).• FF=1=Higher byte of address• FF=0=Lower byte of address.

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Control logic block:• It contains ,1. Control logic2. Mode set register and 3. Status Register.CONTROL LOGIC:• Master mode ,It control the sequence of DMA

operation during all DMA cycles.• It generates address and control signals.• It increments 16 bit address and decrement 14 bit

counter registers.• It activate a HRQ signal on DMA channel Request.• Slave ,mode it is disabled.

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MODE SET REGISTERS:• It is a write only registers.• It is used to set the operating modes.• This registers is programmed after initialization of

DMA channel.

D7 D6 D5 D4 D3 D2 D1 D0

AL TCS

EW RP EN3

EN2

EN1

EN0

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The use of mode set register is,                       1. Enable/disable a channel.                       2. Fixed/rotating priority                       3. Stop DMA on terminal count.                       4.Extended/normal write time.                       5. Auto reloading of channel-2.• The bits D0, D1, D2, and D3 of mode set register are used to enable/disable channel -0, 1, 2 and 3 respectively. A one in these Position will enable a particular channel and a zero will disable it.• If the bit D4(ERP) is set to one, then the channels will have rotating priority and if it zero then the channels wilt have fixed priority.1.In rotating priority after servicing a channel its priority is made as lowest.2. In fixed priority the channel-0 has highest priority and channel-3 has lowest priority. If the bit D5(EEW) is set to one, then the timing of low write signals (MEMW and IOW) will be extended.  

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• If the bit D6 (TC) is set to one then the DMA operation is stopped at the terminal count.

•  The bit D7(EAL) is used to select the auto load feature for DMA channel 2.When bit D7 is set to one, then the content of channel-3 count and address registers are loaded in channel-2 count and address registers respectively whenever the channel-2 reaches terminal count. When this mode is activated the number of channels available for DMA reduces from four to three.

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STATUS REGISTERS:• It is read only registers.• It is tell the status of DMA channels• TC status bits are set when TC signal is activated for

that channel.• Update flag is not affected during read operation.• The UP bit is set during update cycle . It is cleared

after completion of update cycle.

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 UP TC3 TC2 TC1 TCO

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• UP=Update flag• UP=1=8257 executing update cycle (content of

CH3 is reload in CH2 corresponding reg.)• UP=0=8257 executing DMA cycle( by resetting

the auto load bit of MSR)

• TC3=1=TC activated CH-3

• TC3=0=TC activated CH-3

• TC2=1=TC activated CH-2

• TC2=0=TC activated CH-2

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• TC1=1=TC activated CH-1

• TC1=0=TC activated CH-1

• TC0=1=TC activated CH-0

• TC0=0=TC activated CH-0

• The address of status register is A3A2A1A0=1000.

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Pin Diagram of DMA controller

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Description of pin diagram

• D0-D7:• it is a bidirectional ,tri

state ,Buffered ,Multiplexed data (D0-D7)and (A8-A15).

• In the slave mode it is a bidirectional (Data is moving).

• In the Master mode it is a unidirectional (Address is moving).

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• IOR:• It is active low ,tristate ,buffered ,Bidirectional

lines.• In the slave mode it function as a input line. IOR

signal is generated by microprocessor to read the contents 8257 registers.

• In the master mode it function as a output line. IOR signal is used to read data from a peripheral during a memory write cycle.

Page 21: Unit 3 PART2 Dmacontroller8257

• IOW:• It is active low , tristate ,buffered ,Bidirectional

control lines.• In the slave mode it function as a input line.

IOW signal is generated by microprocessor to write the contents 8257 registers.

• In the master mode it function as a output line. IOW signal is write the data to a peripheral during DMA memory read cycle.

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CLK:• It is the input line ,connected with TTL clock generator.• This signal is ignored in slave mode.RESET:• Used to clear mode set registers and status registers and

tristates all the control lines.A0-A3:These are the tristate, buffer, bidirectional address lines.In slave mode ,these lines are used as address inputs lines

and internally decoded to access the internal registers.In master mode, these lines are used as address outputs

lines,A0-A3 bits of memory address on the lines.

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CS:• It is active low, Chip select input line.• In the slave mode, it is used to select the chip.• In the master mode, it is ignored.A4-A7:These are the tristate, buffer, output address lines.In slave mode ,these lines are used as address

outputs lines.In master mode, these lines are used as address

outputs lines,A0-A3 bits of memory address on the lines.

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READY:• It is a asynchronous input line.• In master mode,• When ready is high it is received the signal.• When ready is low, it adds wait state between S1

and S3• In slave mode ,this signal is ignored.HRQ:• It is used to receiving the hold request signal

from the output device.

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HLDA:• It is acknowledgment signal from microprocessor. MEMR:• It is active low ,tristate ,Buffered control output line.• In slave mode, it is tristated.• In master mode ,it activated during DMA read cycle. MEMW:• It is active low ,tristate ,Buffered control input line.• In slave mode, it is tristated.• In master mode ,it activated during DMA write cycle.

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AEN (Address enable):• It is a control output line.• In master mode ,it is high• In slave mode ,it is low• Used it isolate the system address ,data ,and

control lines.ADSTB: (Address Strobe)• It is a control output line.• Used to split data and address line.• It is working in master mode only.• In slave mode it is ignore.

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TC (Terminal Count):• It is a status of output line.• It is activated in master mode only.• It is high ,it selected the peripheral.• It is low ,it free and looking for a new peripheral.MARK:• It is a modulo 128 MARK output line.• It is activated in master mode only.• It goes high ,after transferring every 128 bytes of

data block.

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DRQ0-DRQ3(DMA Request):• These are the asynchronous peripheral request input

signal.• The request signals is generated by external

peripheral device.• The DRQ0 has the highest priority , where DRQ3 has

lowest priority, if fixed priority mode selected.DACK0-DACK3:• These are the active low DMA acknowledge output

lines.• Low level indicate that ,peripheral is selected for

giving the information (DMA cycle).• In master mode it is used for chip select.

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Modes of Operation

• Rotating priority Mode:• The priority of the channels has a circular

sequence.• Fixed Priority Rotating Mode:• The priority is fixed.• TC Stop Mode• Auto Load mode• Extended Write mode

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DMA Cycles

• DMA read:• DMA write • DMA Verify

Page 31: Unit 3 PART2 Dmacontroller8257