TSI Semiconductors, 7501 Foothills Blvd., Roseville, CA 95747 www.tsisemi.com foundry.sales@tsisemi.com TSI Semiconductors' 0.25 mm process is a feature rich platform with best in class CMOS, LDMOS, and BiPolar devices. The BCD technology enables logic, Mixed-Signal, and High Voltage designs for a wide range of high-growth applications such as LED Lighting, Energy Management, Consumer White Goods, and Networking. Eight-inch wafers are manufactured using this process in an automotive qualified facility located in Roseville, CA. TSBCD025 High Voltage 0.25 mm BCDMOS The process was developed such that significant die area reduction, and therefore lower die-cost, could be achieved. The process can offer >20% more die per wafer versus comparable foundry technologies. Feature rich BCD process 2.5V / 5.0V foundry compatible CMOS Scalable extended drain / lateral drain MOS from 15V to 80V Up to 6 levels of Al with a 3.3 mm ultra thick metal option Aggressive back-end design rules, similar to 0.18 mm, resulting in smaller die size Deep trench isolation (DTI) with excellent lateral isolation also for smaller die size DTI allows designers to float HV devices for use as both high and low side drivers across a substrate voltage range from -100 to +100V Key Features Applications Automotive Micro-controllers, eVehicles, hybrid vehicles, charging stations Energy Management Photovoltaics, wind and solar meters, battery management, gate drivers LED Lighting Signage, street / traffic lighting, architectural, pixilated sources, drivers Networking Power over Ethernet, power line communications, smart grid, base stations Industrial Automation Smart building, home and industrial controls, smart sensors Consumer Digital power mgmt units, active-matrix organic LED displays, class D audio, IOT
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TSI Semiconductors, 7501 Foothills Blvd., Roseville, CA 95747www.tsisemi.com foundry.sales@tsisemi.com
TSI Semiconductors' 0.25 mm process is a feature rich platform with best in class CMOS, LDMOS, and BiPolar devices. The BCD technology enables logic, Mixed-Signal, and High Voltage designs for a wide range of high-growth applications such as LED Lighting, Energy Management, Consumer White Goods, and Networking. Eight-inch wafers are manufactured using this process in an automotive qualified facility located in Roseville, CA.
TSBCD025 High Voltage 0.25 mm BCDMOS
The process was developed such that significant die area reduction, and therefore lower die-cost, could be achieved. The process can offer >20% more die per wafer versus comparable foundry technologies.
� Feature rich BCD process � 2.5V / 5.0V foundry compatible CMOS � Scalable extended drain / lateral drain MOS from
15V to 80V � Up to 6 levels of Al with a 3.3 mm ultra thick metal
option
� Aggressive back-end design rules, similar to 0.18 mm, resulting in smaller die size
� Deep trench isolation (DTI) with excellent lateral isolation also for smaller die size
� DTI allows designers to float HV devices for use as both high and low side drivers across a substrate voltage range from -100 to +100V
Key Features
Applications
Automotive Micro-controllers, eVehicles, hybrid vehicles, charging stationsEnergy Management Photovoltaics, wind and solar meters, battery management, gate driversLED Lighting Signage, street / traffic lighting, architectural, pixilated sources, driversNetworking Power over Ethernet, power line communications, smart grid, base stationsIndustrial Automation Smart building, home and industrial controls, smart sensorsConsumer Digital power mgmt units, active-matrix organic LED displays, class D audio, IOT
TSI Semiconductors, 7501 Foothills Blvd., Roseville, CA 95747www.tsisemi.com foundry.sales@tsisemi.com
Standard Cell and IO Libraries
Library Feature Voltage Range
Application
Standard Cell Library9 Track, high density, multiple drive strength & highly optimized for synthesis, optional DTI for low noise and high/low side designs.
2.25V to 2.75VSignal path, power management, low power and low noise
I/O Cell Library 2.5V/5V
Support for Circuit Under Pad (CUP) from 4LM to 6LM, inline and staggered bondpads, output frequency up to 100 Mhz, multiple (up to 8x) drive strength options, >2kV HBM
2.5V/5V Pad limited & core limited designs
I/O Cell Library 20V/40V/60V Analog I/O
Support for CUP from 4LM to 6LM, inline and staggered bondpads, output frequency up to 100Mhz, >2KV HBM
20V/40V/60V Pad limited & core limited designs
ISSI OTP Memory 1 x 32 bits 1.6 to 2.0V Trim bitsISSI OTP Memory 8k x 8 bits 4.5 to 5.5V Parameters / DataTSI Single-Port SRAM 10.51 sq. microns 2.5V +/- 10% Bit cell onlyTSI Dual-Port SRAM 16.56 sq. microns 2.5V +/- 10% Bit cell only
TSI's Design AdvantagesDeep Trench Isolation reduces die size, leakage current and allows for higher operating temperatures
20-30%
Area Reduction
DTI
TSI's 025BCD Back-End of Line (BEOL) is similar to 0.18 mm design rules and coupled with DTI, results in the potential for a 20%-30% die size area reduction.
TSI Foundry
N type Buried Layer
p-EPI
Well
DTI
Isol
atio
n
DTI
Isol
atio
n
N-Isolation N-Isolation
TSI Semiconductors, 7501 Foothills Blvd., Roseville, CA 95747www.tsisemi.com foundry.sales@tsisemi.com
TSBCD025 Core MOS Transistors
Device W/L [mm]
VT [V]
IDSAT [mA/mm]
I IOFF l [pA/mm]
I BVDSS I [V]
Max VDS [V]
Max VGS [V]
2.5V NMOS10/0.24 0.53 ±0.1 600 ±90 <250 6 ±1.5 2.75 2.75
2.5V NMOS - Isolated
2.5V PMOS10/0.24 -0.53 ±0.1 -270 ±50 <150 6 ±1.5 2.75 2.75
2.5V PMOS - Isolated
2.5V Native VT NMOS10/0.5 -0.18 ±0.12 660 ±90 NA NA 2.75 2.75
2.5V Native VT NMOS - Isolated
5V NMOS10/0.5 0.8 ±0.15 560 ±80 <250 10 ±2 5.5 5.5
5V NMOS - Isolated
5V PMOS10/0.5 -0.82 ±0.12 -240 ±40 <250 10 ±2 5.5 5.5
5V PMOS - Isolated
5V Native VT NMOS10/1.2 -0.02 ±0.15 520 ±190 NA NA 5.5 5.5
5V Native VT NMOS - Isolated
Design Rule Std 0.25mm BEOL Std 0.18mm BEOL 025BCD ~ [0.18mm] BEOLContact Width/SpaceM1 Width/SpaceVia 1-5 CD/SpaceM2-5 Width/SpaceM6 (1mm) Width/SpaceVTM CD/SpaceM6 (3mm) Width/Space
0.3/0.30.32/0.320.36/0.35
0.4/0.40.44/0.460.36/0.35
2.6/2
0.22/0.250.23/0.230.26/0.260.28/0.280.44/0.460.36/0.35
2.6/2
0.22/0.240.22/0.240.28/0.280.24/0.280.4/0.45
0.36/0.362.6/1.9
Device Electrical Parameters
BEOL Design Rules Comparison
TSBCD025 High Voltage LDMOS Transistors
Device VT[V]
IDSAT [mA/mm]
RON* Area[ohm.mm2]
I BVDSS I [V]
Max VDS [V]
Max VGS [V]
20V NDMOS 0.68 378 0.0377 >30 20 5
40V NDMOS 0.68 348 0.0562 >50 40 5
60V NDMOS 0.68 322 0.0665 >72 60 5
80V NDMOS 0.68 310 0.0828 >90 80 5
20V PDMOS -0.500 -1630 0.1812 >30 20 5
40V PDMOS -0.540 -1400 0.3212 >50 40 5
60V PDMOS -0.600 -1100 0.4518 >72 60 5
TSI Semiconductors, 7501 Foothills Blvd., Roseville, CA 95747www.tsisemi.com foundry.sales@tsisemi.com
HV Device Benchmarked to Industry
Metal Layer Options
Very competitive RDSon - TSBCD025 is useful for fast switching applications like power management.
BVDSS [V]
100010010
RV_0.25umBCD_LDNMOS
Competitor 1
Competitor 2
Competitor 3
Competitor 4
RDSO
n [m
ohm
s-m
m2 ]
10000.00
1000.00
100.00
10.00
1.00
0.10
LDNMOS RDSOn vs. BVDSS
TSI Semiconductors, 7501 Foothills Blvd., Roseville, CA 95747www.tsisemi.com foundry.sales@tsisemi.com
Cadence DFII (v5.1x). OA (6.1.6)Mentor Graphics Calibre (v2014.2_23.18)Cadence - Spectre, Spectre-VerilogSynopsis - HSPICE
Layout/SchematicDRC/LVS/ERC/PEXSPICE & Verilog SimulationSPICE Simulation
BCD25 PDK
BCD 0.25 µm Design CollateralPDK, Standard Cell Lib, I/O Lib, Memory
Synthesis (IC Compiler)
Simulation (Verilog)
Place & Route(IC Compiler, Encounter)
Post Layout Simulations(Timing, Power, Integrity,
Primetime, VPS)
Digital HV/Analog/Mixed-Signal
Schematic Capture(Virtuoso)
Simulation (Spectre,Hspice, Spectre-Verilog)
Custom Layout (VXL)Analog P&R (Virtuoso GXL)
Simulations w/ Parasitics(Spectre/Hspice back
annotation)
Veri�cation & Sign-o�
Design Flow and Tools
PDK AvailabilityLogic and HV: V1.0 - NowMixed Signal: V1.0 - March 2015
About TSI Semiconductors
TSI Semiconductors offers world class analog and mixed signal foundry processes and services for RF, power management, high voltage, and high temperature automotive applications.
TSI Semiconductors' experienced engineering teams also excel at installing customer-specific processes to meet our customers' requirements in analog and mixed signal applications. The complete array of services provided by TSI Semiconductors can take any set of specifications and create a totally transparent turnkey solution, from chipset development to fully qualified and packaged products.
TSI Semiconductors7501 Foothills Blvd.Roseville, CA 95747(916)786-3900
Visit us online at tsisemi.com or drop us a line at foundry.sales@tsisemi.com
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