The M2 ASIC

SAAB SPACE

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The M2 ASICA mixed analogue/digital ASIC for acquisition and control in data handling systems

Olle MartinssonAMICSA, October 2-3, 2006

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M2 summary

A mixed analogue/digital ASIC, including 32 kgates and a 12 bit ADC, developed by Austrian Aerospace and Saab Space under an ESA contractMain application as generic core circuit for data handling I/O boardControlled via OBDH bus or UART interfaceDigital I/O functions include all common data handling system interfaces, such as:

High level command pulse generationSerial command and acquisitionEtc.

3.3V supplyLow power, typical consumption 12mW

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M2 block diagramConfiguration

Dac/TimerBcp

MUXADC/COMP

RxAP

RxBN

TxAN

TxAInh

R tAddr(4:0 )

TxAEn

Vre fL

RstAN

Rref(3:0 )An(67 :0)

G rp8Out(3 :0)

G rp8In

IO G R P 1

IO G R P 2

IO G R P 8

G rp1Out(3 :0)

G rp1In

G rp2Out(3 :0)

G rp2InRxBP

RxAN

TxAP

RtPar

Vre fH

Buff

O B D HC TR L

Config (1:0 )

DsPort In

ACQCTRL

CONFIGANDCMDCTRL

HlcPo rt O ut

M L

M ux C trl

UART Tx

(D S16 , Uart Rx,Pu lse C ounter)

C lkSync

HlcStrNUART /O BDHBridge

AnalogVddAnVssAn

TxBInhTxBEnTxBNTxBP

RstBN & Reset

BUSSEL

BusAEnBusBEn

O BDHRT

Clock detect ClkActive

Address strap

Controlinterface

Configuration

Reset

Analog I/O interfaces

Digital I/O user interface

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M2 implementation

Commercial, epi-layered CMOS technology, AMIS 0.35µ with analog options (double poly capacitors, high resistive poly resistors)

Radiation tolerant by “Rad hard by design”

Digital cell library developed within the project

Digital part designed using VHDL, logic synthesis and place & route

Chip size 25mm2

Prototypes via Europractice MPW in 160 pin CQFP package

Tested showing full functionality and full performance at first run

Implemented on a prototype I/O board for system level test, showing similar or better performance compared to existing designs

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Rad hard by design

The methodology to reach radiation hardness has basically been the same for analogue and digital parts. This includes:

Selection of submicron CMOS assures small threshold voltage drifts

NMOS edge leakage avoided by enclosed shaped transistors

Leakage between NMOS devices avoided by guard rings

Latchup avoided by guard rings and good substrate connections

SEU hardness achieved by means of resistive feedback in flip-flops─ Limits maximum possible clock rate, but

+ Makes the design hard also to transients in combinatorial logic

Only low level measures, mainly on layout level, to achieve radiation hardness radiation aspects have only marginal impact on system, VHDL and schematic level design

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Cell library design based on “shadow” libraryS chem a tic

ed ito r

A na logs im u la to r

L ayou t e d ito r

TD B

D R C(D es ign R u le

C hecke r)E xtrac to r Models

LV S(Layout V e rsus

S ch em atic )

S p ice

Techsetup

S chem aticsA n . des ign

S p ice

S chem a ticed ito r

Tes t b enchS p ice

Shadowcell lib

M anua lcom pariso n

C e lldescrip tion

docum en t

M2 cell lib

Cell library, just like analog parts and top level design, developed using a low cost PC based tool from Tanner, including:

Schematic editorSpice simulatorLayout editorDesign rule checkExtractionLayout vs. schematicPlace & route

M2 cells selected as a subset of and compared with cells of a commercially available “shadow” library of a similar process

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Digital cell library

Library consists of:3 flip-flops14 combinatorial core cells4 digital I/O cells4 power I/O cells

Size of NAN2 gate 8.4 x 21 μm2, indicating 5.7 kgates/mm2 Size of NAN2 in AMIS library for the same technology, MTC45000: 4.5 x 12 μm2, indicating an area penalty factor 3.3 for the radiation hardnessGate density of the M2 after place & route = 31.7kgates / 15.7mm2 = 2.0 kgates/mm2 (only 3 metal layers used for place & route, limitation by Tanner tools)

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Cell layout examples

Output pad cell with tristate

MUX2

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Digital design flow using the “shadow” library

Digital part designed using a standard flow including VHDL and digital simulationLogic synthesis performed using the similar “shadow” library, but limited to use only these cells that have been implemented in the M2 libraryGate level simulation can be performed using the shadow libraryBackannotation (timing feedback from layout) not possible, good timing margins neededLayout routing verified using netlist from digital design, extraction of layout and LVS

Layou t ed ito r(d ig ita l and ana log m erge )

TD B

VH D L too l(text ed ito r)

D ig ita l s im u la to r

VH D L testbenches

Log icsyn th es ize r

P lace &R ou te

TD B

VH D L too l(text e d ito r)

V H D L R TLdesig n

V H D Lnetlis t

An a logdes ign TD B

LV S(Layo ut V e rsus S chem atic )

D R C(D es ign R u le

Che cke r)

Shadowcell lib

N etlis tconvers ion

E xtrac to r

S p iceTo found ry

Sp ice

Top leve lSp ice

Place&rou te andch ip level design

D igita l designE D IF

G D SII

Text ed ito r(d ig ita l and a na log m e rg e)

Ana log de s ignSp ice ne tlis t

M2 cell lib

TDB = Tanner layoutdatabase form at

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Analogue part description

ADC third order MASH ΣΔ type, 12.28 bits (4960 codes)External 1.25V referenceTime discrete, switched capacitor based, operating at 500kHz (typical)One conversion within minimum 100µs, including time for multiplexer settlingBuffered signal and reference inputs66 channel input multiplexerDigital outputs for control of external multiplexerSwitchable thermistor conditioning (for resistance measurements), giving:

Compact design (one conditioning resistor common for many channels)High precision (minimum number of error sources)Low power, only one channel powered at a time

Direct thermistor interface, no additional front-end neededIncludes comparator for binary acquisition of analog inputs (digital bilevel and digital relay)

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Digital noise

Digital noise, which is a potential problem, especially substrate coupled, was handled by:

Differential design

Topology (sigma-delta)

Separated digital and analogue supply lines

Input filter (especially considering unbalanced, non-differential inputs)

Early clock to analogue functions

Careful design of signal interfaces between digital to analogue domains, e.g. filters are added where feasible

Careful package grounding, considering that grounds anyway are connected via excessive substrate connections

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M2 layout

4921.5µ x 5028.5µ ≈ 24.75 mm2

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Test result summaryPower consumption typically 12mW, approximately 50/50 analogue/digitalFunctional test OKAnalog performance:

ADC linearity measured to DNL < 0.17LSB and INL < 0.17LSB (1 sample)Gain error: -0.8LSB average, 0.6LSB standard deviation (18 samples)Offset error: -0.16LSB average, 0.14LSB standard deviation (18 samples)

Environment tested:Supply voltage 2.8 to 3.6VTemperature -30 to +85CTotal dose radiation up to 300krad and annealingHeavy ion test up to 106MeV/mgcm2 effective LETLife test, 1000 hours in +125CESD test up to 4kV HBM

Virtually radiation immune, both concerning total dose and heavy ionsNo ESD damage up to 4kV HBMGood stability considering:

Input common mode variationsSupply voltage variationsTemperature variationsAgeing

17 of 18 tested samples showed full function and performance (yield = 94%)

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Measured ADC linearity performanceDNL

-1-0,8-0,6-0,4-0,2

0

0,20,40,60,8

1

-3000 -2000 -1000 0 1000 2000 3000

code

INL

-1-0,8-0,6-0,4-0,2

00,20,40,60,8

1

-3000 -2000 -1000 0 1000 2000 3000

code

DNL = Differential non-linearity

INL = Integrated non-linearity

Vertical scale in LSB

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Measured ADC performance vs. temperature

GE

-2

-1,5

-1

-0,5

0-40 -20 0 20 40 60 80 100

degrC

LSB

M2#01

M2#15

M2#16

M2#17

M2#18

OE

-0,4

-0,3

-0,2

-0,1

0-40 -20 0 20 40 60 80 100

degrC

LSB

M2#01

M2#15

M2#16

M2#17

M2#18GE = Gain Error

OE = Offset Error

1 LSB = 0.5 mV

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Measured ADC performance vs. supply voltage

GE

-1,04-1,02

-1-0,98-0,96-0,94-0,92

-0,92,8 2,9 3 3,1 3,2 3,3 3,4 3,5 3,6

Vsply

LSB M2#01

OE

-0,4

-0,3

-0,2

-0,1

02,8 2,9 3 3,1 3,2 3,3 3,4 3,5 3,6

Vsply

LSB M2#01

GE = Gain Error

OE = Offset Error

1 LSB = 0.5 mV

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Measured ADC performance vs. life in 125C

1 LSB = 0.5 mV

Gain Error

-3-2-10123

0 200 400 600 800 1000 1200hours

M2#REFM2#15M2#16M2#17M2#18Spec minSpec max

Offset Error

-1.5-1

-0.50

0.51

1.5

0 200 400 600 800 1000 1200hours

M2#REFM2#15M2#16M2#17M2#18Spec minSpec max

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Measured ADC performance vs. total dose

Gain Error

-3-2-10123

0 100 200 300 400krad

M2#REFM2#05M2#12M2#13M2#14Spec minSpec maxAnealing 168h

Offset Error

-1.5-1

-0.50

0.51

1.5

0 100 200 300 400krad

M2#REFM2#05M2#12M2#13M2#14Spec minSpec maxAnealing 168h

1 LSB = 0.5 mV

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Measured supply current vs. total doseIDDA (TID test)

1.60E-03

1.65E-03

1.70E-03

1.75E-03

1.80E-03

0 100 200 300 400 500

kRad

Ampe

re

#01(ref)

#05

#12

#13

#14

anealing 168h

IDDI (TID test)

1.90E-03

1.95E-03

2.00E-03

2.05E-03

2.10E-03

0 100 200 300 400 500

kRad

Ampe

re

#01(ref)

#05

#12

#13

#14

anealing 168h

IDDA = Analogue core supply

IDDI = Digital core supply

Note, step in IDDI was due to a change in test setup (affected also the reference M2)

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M2 SEE test summary

TestRun Condition

Vsply

Temp SN# Effective

LET Fluence Equivalent Fluence(1)

SEL SEU Acq. errors

Other events

[ # ] [V] [ ºC ] [MeV/mg·cm2] [ p/cm2 ] [ p/cm2 ] [ # ] [ # ] [ # ] [ # ] 201 Static 2,8 RT 06 30 1,00E+06 2,00E+03 0 0 0 0 202 Static 2,8 RT 07 30 3,02E+06 6,03E+03 0 0 0 0 205 Static 2,8 RT 07 60 5,00E+06 9,99E+03 0 0 0 0 206 Static 3,6 85 07 42,4 5,02E+06 1,00E+04 0 0 0 0 207 Static 3,6 85 07 75 5,28E+06 1,05E+04 0 0 0 0 208 Static 3,6 85 07 106 1,02E+07 2,04E+04 0 0 0 0 209 Static 3,6 85 06 106 1,01E+07 2,02E+04 0 0 0 0 211 Static 2,8 RT 06 106 1,02E+07 2,04E+04 0 0 0 0 213 Static 2,8 RT 07 106 1,01E+07 2,02E+04 0 0 0 1 215 Static 2,8 RT 07 106 1,00E+08 2,00E+05 0 0 0 1 216 Dynamic 2,8 RT 07 106 1,47E+07 2,76E+06 0 0 2 0 217 Static 2,8 RT 07 53 1,01E+08 2,02E+05 0 0 0 0

Note 1: Equivalent fluence is applicable to Acquisition errors only.

Conclusion: The M2 is considered immune to heavy ions regarding SEL and register SEU

Note: Maximum recorded acquisition error at LET=106 was 0.34% of full scale

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via1 array 3D cell

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