Software Notes SHW

nanoSOM™ NS02 Hardware description

ID No. THW1029 - REV. 1.4 ©2021 EXOR Embedded S.r.l. - Subject to change without notice exorint.com 2

Nanosom nS02

History Rev Date Description By 1.0 12-03-2019 Preliminary S.Fazlagic 1.1 19-09-2019 Added changes respecting BOOT pins S.Fazlagic 1.2 30-09-2019 Passed to new template S.Fazlagic 1.3 25-05-2020 Changed operating frequency of CPU (type) S.Fazlagic 1.4 25-06-2021 Solved the wrong pin out (I2C1) Table at page 11 (pins 9 and 10) S.Fazlagic

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Reference Filename Description

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The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Technical data subject to change. Copyright © 2021 EXOR International S.p.A. - All Rights Reserved.


TABLE OF CONTENTS

1. Introduction ...................................................................................................................... 5

2. nanoSOM™ technology .................................................................................................... 6

3. Dimensions ...................................................................................................................... 8

4. Pin out .............................................................................................................................. 8 4.1. Left connector external ......................................................................................... 11 4.2. Top connector external ......................................................................................... 11 4.3. Right connector external ....................................................................................... 12 4.4. Bottom connector external ................................................................................... 14 4.5. Left connector internal .......................................................................................... 15 4.6. Top connector internal .......................................................................................... 15 4.7. Right connector internal ........................................................................................ 16 4.7. Bottom connector internal .................................................................................... 17 4.8. Bottom side invisible rounded pads ..................................................................... 17

5. Description ..................................................................................................................... 18 5.1. STM32MP157FAC3 and main circuits ................................................................ 19

5.1.1. Dual Core ARM A7 ..................................................................................... 19 5.1.2. Embedded memory controller (DDR3L) .................................................... 19 5.1.3. eMMC .......................................................................................................... 19 5.1.4. USB support ................................................................................................ 19 5.1.5. CAN1 and CAN2 .......................................................................................... 20 5.1.6. UART4, UART5 and UART7......................................................................... 20 5.1.7. SPI2, SPI3, SPI4 and SPI5 ........................................................................... 21 5.1.8. Audio OUT- I2S ............................................................................................ 22 5.1.9. I2C ................................................................................................................. 22 5.1.10. SD ports ..................................................................................................... 22 5.1.11. Display interface (parallel RGB) ............................................................... 23 5.1.12. Ethernet ..................................................................................................... 24 5.1.13. GPIO and Analog inputs .......................................................................... 25 5.1.14. Buzzer ....................................................................................................... 27 5.1.15. DCMI (Digital Camera interface) ............................................................. 27 5.1.16. Mipi DSI Video out ................................................................................... 28 5.1.17. Two system LEDS .................................................................................... 28

5.2. AUX Circuits ........................................................................................................... 29 5.2.1. RTC .............................................................................................................. 30 5.2.2. SEEPROM ................................................................................................... 30 5.2.3. RES_OUT* ................................................................................................... 30

5.3. Power supplies ...................................................................................................... 30 5.4. Internal and External Pads (“Connectors”) .......................................................... 31 5.5. Board View ............................................................................................................. 33

6. Building carrier board pattern for hosting nanoSOM™ NS02 ..................................... 35 6.1 One Important addition for internal pads ............................................................. 39 6.2 Some specific signals ............................................................................................ 41 6.3 Using FRAM with nanoSOMTM NS02 ..................................................................... 43 6.4 Using TPM module with nanoSOMTM NS02 ......................................................... 43


6.5 NS01 and NS02 compatibility ................................................................................ 44 6.5.1. Common NS01 and NS02 resources ........................................................ 45 6.5.2. Only NS02 resources .................................................................................. 50 6.5.3. Boot modes for NS02/NS01 and differences ........................................... 51


1. Introduction

This document is hardware presentation of nanoSOM™ NS02.

The document can help user quickly understanding module interface specifications, electrical and mechanical details.

nanoSOM™ NS02 is member of EXOR’s nanoSOM™ family, very small, but powerful PCB board, without connectors. Practically, user can consider nanoSOM™ (NS02) as “a component”, which can be soldered directly in users, custom carrier board. nanoSOM™ NS02 is based at STM32MP157FAC3 dual A7 core processor plus M4 core (package 12 mm x 12 mm) and full features, described in this document, suppose using this processor.


2. nanoSOM™ technology

nanoSOM™ is one ultra-compact SOM, that introduces new connection, technical similar to chip scale package of IC, that allows soldering to the main carrier board the same way as other IC SMD components. nanoSOM™ adapts connection technique Flat no-leads packages with external 131 contacts 0,7mm QFN (quad-flat no-leads). It is a surface-mount technology that connect ICs to the surfaces of PCB without through-holes and without expensive connectors. nanoSOM™ NS02, adds also 69 + 10 contacts (pads) more (named internal contacts, located at bottom side). Pads at package at top and bottom side provide electrical connections to external PCB (named carrier board). The nanoSOM™ has very compact size (see drawing below) and is not invasive in the design of the carrier board. The nanoSOM™ has specially thickness of only 2.8 mm max, almost like the normal IC package, allowing user to create industrial products with very compact and incredible thin profile.

Block diagram of nanoSOM™ NS02 is presented below.

nanoSOM NS02Carrier for nanoSOM Carrier for nanoSOM

Top side of nanoSOM

Bottom side of

nanoSOM

Hole in carrier board

Solder Pads Solder Pads

2.8 mm total NS02 module

thickness



3. Dimensions

Drawing above shows dimension of nanoSOM™ NS02. Dimensions are in mm.

4. Pin out

Bottom side pads have prefiks I (internall)

NS02 TOP view

23.50mm

23.5

0mm

25.4

0mm

25.40mm

NS02 BOTTOM view(view through module)

Top

Bottom

Left

Rig

ht

Origin

T4 T34

B34B1

L3

L34 R34

R1

IL1

IL7

IT1 IT20IR1

IR20IB20IB1

IL19IL20

These 10 pads are not used

(not connected)


Picture above shows TOP side view (side of components) and BOTTOM side. Although also BOTTOM side contains components, there are much more components at TOP side.

Top edge

Bottom edge

Rig

ht e

dge

Left

edge

NS0

2 Bo

ttom

vie

w (v

iew

thro

ugh

boar

d)

Origin

IT1 IT20

IR1

IR20

IB20IB1

IL20IL19

IL1

IL7

These 10 are NC

T4 Top edge

Bottom edge

Rig

ht e

dge

Left

edge

T34

R1

R34

B34B1

L3

L34

NS0

2 To

p vi

ew


BOTTOM side contains mainly some capacitor filters and some minor components, which due to various reasons, must be located at bottom side. Note that carrier board for supporting nanoSOM™ NS02 must have HOLE in central board area. See below:

.

nanoSOM™ NS02 is built around:

• Four external (edge)”connectors” (total 131 pins) at TOP side. • Four internal (edge) “connectors” (total 69 pins) at BOTTOM side • Ten rounded pins at BOTTOM side are reserved and not connected. These pins are placed

only to provide mechanical compatibility with NS01 board and shouldn’t be connected. Really, these “connectors” are not true connectors, but simple soldering PADS, with pitch 0.7mm for external and 1mm for internal pads. Due to intentionally asymmetric shape (TOP LEFT angle is inclined), some pins are “lost” to have 4x34 =136 pins, so total number of external pins is 131 pins (31 + 32 + 34 + 34). Internal pads are: 9 (Left) + 20 (Top) + 20 (Right) + 20 (Bottom) pads. Next chapters shows all pins, located at external and internal “connectors”. Note that nearly all pins of STM32MP157FAC3 have more functions. In order to build nanoSOM™ NS02, is selected one default pin mapping, which in the best way covers most of Exor’s needs. Also very important request was to get nanoSOM™ NS02 compatible with nanoSOM™ NS01. Compatibility NS01 and nS02 is subject of one special chapter. User can select some other using-pin out (for example to have more UARTS, less SPI, to have Quad SPI connection and other combinations). Of course, this change must be followed by support in firmware and BSP. User can change this default pin out, using PINMUX tool by ST and one must be familiar with this, in case of changing. Some signals (have name GPIO in column) are true GPIO, without some special using. All signals can be used also as simple GPIO. All signals are direct LVCMOS/LVTTL (+3V3) compatible (of course expect special like USB pairs for example or DSI signals).

nanoSOM NS02Carrier for nanoSOM Carrier for nanoSOM

Top side of nanoSOM

Bottom side of

nanoSOM

Hole in carrier board

Solder Pads Solder Pads

2.8 mm total NS02 module

thickness


4.1. Left connector external

Pin Signal Name Type STM32MP157FAC3 (resource)

Pin Port Comment

3 +3V3S Supply

Supply +3V3, 5% 4 +3V3S Supply 5 +3V3S Supply 6 +3V3S Supply 7 +3V3S Supply 8 GND 9 SDA I2C1_SDA Y4 PF15 I2C system 10 SCL I2C1_SCL AC4 PF14 11 BL_PWM TIM2-CH1 V3 PA5

Video OUT AUX signals

12 EN_BL GPIO (OUT) A14 PF2 13 EN_VDD GPIO(OUT) D9 PF4 14 GND 15 LCD_DATA0 LCD_B0 D19 PE4

Video OUT data signals

16 LCD_DATA1 LCD_B1 K4 PG12 17 LCD_DATA2 LCD_B2 U2 PA3 18 LCD_DATA3 LCD_B3 Y7 PG11 19 GND 20 LCD_DATA4 LCD_B4 E4 PI4


21 LCD_DATA5 LCD_B5 F3 PI5 22 LCD_DATA6 LCD_B6 F4 PI6 23 LCD_DATA7 LCD_B7 K3 PD8 24 GND 25 LCD_DATA8 LCD_G0 AA7 PB1


26 LCD_DATA9 LCD_G1 C10 PE6 27 LCD_DATA10 LCD_G2 D1 PH13 28 LCD_DATA11 LCD_G3 AB11 PG10 29 GND 30 LCD_DATA12 LCD_G4 B3 PH4


31 LCD_DATA13 LCD_G5 C1 PI0 32 LCD_DATA14 LCD_G6 P4 PI11 33 LCD_DATA15 LCD_G7 AB9 PG8 34 GND

4.2. Top connector external

Pin Name Type STM32MP157FAC3 (resource)

Pin Port Comment


4 GND 5 GND 6 GND 7 GND 8 Not used Not used (NC)

RMII port 1 9 RMII1_CRS_DV RMII1_C_DV AB8 PA7 10 RMII1_RX0 RMII1_RX0 AC7 PC4 11 RMII1_RX1 RMII1_RX1 AB7 PC5 12 GND 13 RMII1_TXEN RMII1_TXEN AB1 PB11

RMII port 1 14 RMII1_CLK RMII1_CLK AA4 PA1 15 RMII1_TX0 RMII1_TX0 AA2 PG13 16 RMII1_TX1 RMII1_TX1 AA1 PG14 17 GND 18 LED_LINK LED_LINK (*)

Lan 2 Port 19 VDD33A VDD33A (*) 20 RX2_P RX2_P (*) 21 RX2_N RX2_N (*) 22 GND 23 LED_SPEED LED_SPEED (*)

Lan 2 Port 24 Not used Not used 25 TX2_P TX2_P (*) 26 TX2_N TX2_N (*) 27 ETH_MDIO ETH_MDIO AC3 PA2 RMII control

MDC/MDATA 28 ETH_MDC ETH_MDC AA6 PC1 29 SPI5_CS0* SPI5_CS0* AA13 PF6

SPI5 channel 30 SPI5_MOSI SPI5_MOSI Y10 PF11 31 SPI5_MISO SPI5_MISO AC11 PF8 32 SPI5_CLK SPI5_CLK Y11 PH6 33 GND 34 SPI4_CS0* SPI4_CS0* AA19 PD13 SPI4 channel

(*) LAN 2 port is controlled by, on board, LAN9512 bridge. This port “replaces” RMII2 port of nanoSOM™ NS01. It is direct LAN interface (no need for RMII PHY), with addition of only external LAN transformer and connecting appropriate LEDs. In order to have nanoSOM™ NS01 and NS02 compatibility, user must to provide it in carrier board, using some zero ohm resistors (explain in one separate chapter).

4.3. Right connector external


Pin Port Comment

1 SPI4_MOSI SPI4_MOSI C6 PE14 SPI4 channel 2 SPI4_MISO SPI4_MISO C11 PE5


3 SPI4_CLK SPI4_CLK B4 PE12 4 GPIO2/PWM2 GPIO2/TIM4-CH1 Y18 PD12

GPIO/PWM 5 GPIO1/PWM1 GPIO1/TIM4-CH3 L3 PD14 6 GPIO3 GPIO3 AC10 PD11 7 GND 8 BOOT_MODE2 (**) BOOT2 M2

Some special signals

(see below)

9 BOOT_MODE0 (**) BOOT0 N1 10 BOOT_MODE1 (**) BOOT1 N4 11 POW_GOOD (*) 12 RES_OUT* (*) 13 RES_IN* (*) 14 VBB (*) 15 GND 16 SPI2_CS1* SPI2_CS1* AC13 PE8

SPI2 channel 17 SPI2_CS0* SPI2_CS0* Y13 PG9 18 SPI2_MOSI SPI2_MOSI E1 PI3 19 SPI2_MISO SPI2_MISO E2 PI2 20 SPI2_CLK SPI2_CLK Y3 PB10 21 GND 22 SPI3_CS0* SPI3_CS0* AA14 PF9

SPI3 channel 23 SPI3_MOSI SPI3_MOSI Y16 PB2 24 SPI3_MISO SPI3_MISO B5 PD10 25 SPI3_CLK SPI3_CLK D6 PE0 26 GND 27 CAN2_TX CAN2_TX Y14 PB6 CAN2 28 CAN2_RX CAN2_RX Y8 PB5 29 CAN1_TX CAN1_TX AB19 PA12 CAN1 30 CAN1_RX CAN1_RX B8 PD0 31 GND 32 UART7_RTS UART7_RTS AA9 PE9

UART7 33 UART7_CTS UART7_CTS Y15 PE10 34 UART7_RX UART7_RX AA11 PE7

(*) These are special signals. Please check using of these signals at the end of this chapter. (**) These signals are system control for boot. BOOT_MODE0, BOOT_MODE1 BOOT_MODE2 are three pins of CPU, responsible for BOOT procedure. At startup, the boot source used by the internal BootROM is selected by the BOOT pin and OTP bytes. Theoretically is possible have eight combinations, but some of them are not possible with NS02 due to lack of appropriate hardware (for example NAND flash on FMC or serial NOR flash from QUADSPI)

Boot2 Boot1 Boot0 Initial boot mode comments

0 0 0 UART and USB Wait incoming connection on: UART4/5/7 USB high-speed device

0 1 0 eMMC eMMC on SDMMC2


1 0 0 Reserved (no boot) Used to get debug access without boot from Flash memory

1 0 1 SD card SD card on SDMMC1 (1) 1 1 1 SD card SD card on SDMMC1 (2)

1) Boot source could be changed by OTP settings (e.g. initial boot on SD card, then eMMC with OTP settings)

2) Could be disabled by OTP settings. POW_GOOD is control out from nanoSOM™ NS02. Signal is generated high when all local supplies inside nanoSOM™ NS02 are OK. User should use this signal to enable supply for I/O peripherals at carrier board. See in the rest of documents more description for this signal. RESET_OUT* is system reset (active LOW), coming from circuits inside nanoSOM™ NS02. This signal is really “OR” function of local, on board Power up Reset (POR*) and “software” RESET controlled by CPU as one GPIO (out) pin. This signal is named SOFT_RST* (port PZ5, pin H2 of CPU). (See in the rest of document in chapter “Some specific signals”). RES_IN* is (optionally) external RESET input signal (including reset KEY). (See in the rest of document in chapter “Some specific signals”). Vbb is battery supply (2-5.5V), coming from carrier board. This signal is used only to supply RTC chip inside nanoSOM™ NS02. CPU doesn’t use Vbb so battery Vbb consumption is extremely low and also super CAP can be used for some days.

4.4. Bottom connector external


Pin Port Comment

1 LCD_DATA23 LCD_R7 D3 PE15 Video OUT data

signals 2 LCD_DATA22 LCD_R6 B2 PH12 3 LCD_DATA21 LCD_R5 AB5 PC0 4 LCD_DATA20 LCD_R4 AA18 PA11 5 GND 6 LCD_DATA16 LCD_R0 AB4 PH2


7 LCD_DATA17 LCD_R1 J2 PD15 8 LCD_DATA18 LCD_R2 D5 PH8 9 LCD_DATA19 LCD_R3 C5 PH9 10 GND 11 LCD_CLK LCD_CLK AC14 PG7

Video OUT control

signals

12 LCD_DE LCD_DE Y12 PF10 13 LCD_HSYNC LCD_HSYNC T1 PI10 14 LCD_VSYNC LCD_VSYNC H4 PI19 15 LCD_RST GPIO (OUT) T2 PA14


16 GND 17 SD1_CLK SD1_CLK D13 PC12

Main SD card

18 SD1_CMD SD1_CMD D12 PD2 19 SD1_D0 SD1_D0 D18 PC8 20 SD1_D1 SD1_D1 D17 PC9 21 SD1_D2 SD1_D2 D15 PC10 22 SD1_D3 SD1_D3 D16 PC11 23 GND 24 SD1_WP* SD1_WP* U1 PF3 SD card AUX 25 SD1_CD* SD1_CD* V2 PG2 26 BUZZER TIM5-CH1 AB3 PA0 Buzzer/PWM 27 UART4_TX UART4_TX N2 PA13

UART4 28 UART4_RX UART4_RX C3 PH14 29 UART4_CTS UART4_CTS AB6 PB0 30 UART4_RTS UART4_RTS C19 PA15 31 GND 32 UART5_TX UART5_TX AA10 PB13 UART5 33 UART5_RX UART5_RX AC5 PB12 34 UART7_TX UART7_TX AB12 PF7 UART7

4.5. Left connector internal

Pin Name Type STM32MP157FAC3 (resource) Pin Port Comment

1 TRST NJTRST B19 JTAG 2 DSI_D1_P DSI_D1_P B17 DSI MIPI_DSI_D1 pair 3 DSI_D1_N DSI_D1_N A17 DSI 4 DSI_D0_P DSI_D0_P C15 DSI MIPI_DSI_D0 pair 5 DSI_D0_N DSI_D0_N B15 DSI 6 DSI_CK_P DSI_CK_P B16 DSI MIPI_DSI_CLK pair 7 DSI_CK_N DSI_CK_N A16 DSI

19 DCMI_VSYNC DCMI_VSYNC D11 PB7 Camera (DCMI) 20 DCMI_HSYNC DCMI_HSYNC K1 PD9

4.6. Top connector internal

Pin Name Type STM32MP157FAC3 (resource) Pin Port Comment

1 TDO JTAG_TDO A19 JTAG

JTAG signals 2 TDI JTAG_TDI A20 JTAG 3 TMS JTAG_TMS C20 JTAG 4 TCK JTAG_TCK B20 JTAG 5 GND


6 USB0_OTG_ VBUS USB_VBUS AC19

USB OTG Port 0 7 USB0_OTG_ID USB0_OTG_ID Y17 PA10 8 USB0_OTG_N USB_DM2 AB16 9 USB0_OTG_P USB_DP2 AC16 10 GND 11 USB1_P (*)

USB Host Port1 (Via USB HUB)

LAN9512

12 USB1_N (*) 13 USB1_EN (*) 14 USB1_OC* (*) 15 GND 16 USB2_P (*)

USB Host Port2 (Via USB HUB)

LAN9512

17 USB2_N (*) 18 USB2_EN (*) 19 USB2_OC* (*) 20 GND

Signals (*) are connected to on board LAN9512 HUB. Signals USBx_EN and USBx_OC* are really physically one signal, connected inside nanoSOM™ NS02. It is done due to support compatibility’ with nanoSOM™ NS01. LAN9512 has unique common signal and user at carrier should use USB load switch with high EN and open drain (active low OC*).

4.7. Right connector internal

Pin Name Type STM32MP157FAC3 (resource Pin Port Comment

1 GPIO4 GPIO4 Y6 PG5

Gpio 2 GPIO5 GPIO5 AB2 PG4 3 GPIO6 GPIO6 AC2 PG0 4 GPIO7 GPIO7 AA3 PH3 5 GND 6 SD3_CLK SD3_CLK B7 PG15

SD3 (second user’s SD/SDIO port)

7 SD3_CMD SD3_CMD A5 PF1 8 SD3_D0 SD3_D0 B9 PD1 9 SD3_D1 SD3_D1 B6 PD4 10 SD3_D2 SD3_D2 A7 PD5 11 SD3_D3 SD3_D3 D10 PD7 12 GND 13 I2S1_CK I2S1_CK G3 PZ0

I2S port (can be used also

as SPI1)

14 I2S1_SDO I2S1_SDO J4 PZ2 15 I2S1_SDI I2S1_SDI G1 PZ1 16 I2S1_WS I2S1_WS G4 PZ3 17 I2S1_MCLK I2S1_MCLK H1 PZ6 18 GND 19 AIN_IN0 ANA0 U3 Analog inputs


20 AIN_IN1 ANA1 U4 Attention: I2S channel can be also used as SPI1 port (of course with appropriate firmware support) I2S1_CK SPI1_SCK I2S1_SDO SPI1_MOSI I2S1_SDI SPI1_MISO I2S1_WS SPI1_CS0* I2S1_MCLK SPI1_CS1*

4.7. Bottom connector internal

Pin Name Type STM32MP157FAC3 (resource Pin Port Comment

1 DCMI_PIXCLK DCMI_PIXCLK Y2 PC2 DCMI 2 GND 3 DCMI_D11 DCMI_D11 B1 PH15

DCMI 8/10/12 bits Camera port

4 DCMI_D10 DCMI_D10 D2 PD6 5 DCMI_D9 DCMI_D9 W4 PH7 6 DCMI_D8 DCMI_D8 E3 PI1 7 DCMI_D7 DCMI_D7 F2 PI7 8 DCMI_D6 DCMI_D6 A3 PE13 9 GND 10 DCMI_D5 DCMI_D5 D14 PD3

DCMI 8/10/12 bits Camera port

11 DCMI_D4 DCMI_D4 A4 PE11 12 DCMI_D3 DCMI_D3 C8 PE1 13 DCMI_D2 DCMI_D2 C4 PH11 14 DCMI_D1 DCMI_D1 C2 PH10 15 DCMI_D0 DCMI_D0 A8 PA9 16 GND 17 AIN_IN5 AIN_IN5 Y9 PF12

Analog inputs 18 AIN_IN4 AIN_IN4 AC8 PA6 19 AIN_IN3 AIN_IN3 W2 PC3 20 AIN_IN2 AIN_IN2 W4 PA4

4.8. Bottom side invisible rounded pads

At bottom side we have also ten rounded pins.


These pins are used in nanoSOM™ NS01 as tamper pins. These tamper pins are located in “forbidden area” in order to hide these tamper pins (if customer prefers it). For nanoSOM™ NS02 these pins are meaningless (not connected towards CPU STM32MP157FAC3). If customer will use only nanoSOM™ NS02 these pads can be completely avoided in carrier shape for NS02.

5. Description

nanoSOM™ NS02 is built around SOC (System on chip) STM32MP157FAC3 dual core A7 plus M4 core, FBGA 361 pins (case 12 mm x 12 mm). Below is presented BLOCK diagram of nanoSOM™ NS02.

Main circuits are:

1) STM32MP157FAC3 with direct support the most peripherals 2) AUX CIRCUITS (peripherals on board, for additional support) 3) Power supplies 4) External and internal PADs (“connectors”)

STM32MP157FAC3 is heart of nanoSOM™ NS02 and with dual core A7 plus M4 core. Processor provides (contains cores):


• Interface towards DDR3L • Interface towards eMMC • USB interface towards USB bridge LAN9512 and one USB channel • One RMII port • A lot of peripherals (UARTs, SD, CAN, I2C, Audio I2S, Video Out RGB, camera In, SPI… • Simple GPIO /PWM pins

5.1. STM32MP157FAC3 and main circuits

5.1.1. Dual Core ARM A7

nanoSOM™ NS02 is based at STM32MP157FAC3, dual core ARM A7 plus M4 core, located in SOC, which operates at speed up to 800 MHz.

5.1.2. Embedded memory controller (DDR3L)

STM32MP157FAC3 includes embedded memory controller with support for various memory types. In nanoSOM™ NS02 is used DDR3L (1V35) in 16 bits mode. The footprint for DDRAM3L supports 2 Gb, 4 Gb and 8 Gb packages.

5.1.3. eMMC

STM32MP157FAC3 supports eMMC (embedded MMC). It is used SD2 port in 8 bits mode for eMMC. In nanoSOM™ NS02 embedded eMMC is used as main OS memory. Attention: eMMC signals are local signals, inside board (not visible at “connectors”). Table below shows assigning SD2 port signals to eMMC memory.

Signal name Signal Name (CPU) Pin Port EMMC_D0 SD2_D0 C13 PB14 EMMC_D1 SD2_D1 B12 PB15 EMMC_D2 SD2_D2 A11 PB3 EMMC_D3 SD2_D3 B13 PB4 EMMC_D4 SD2_D4 A13 PA8 EMMC_D5 SD2_D5 B10 PB9 EMMC_D6 SD2_D6 B14 PC6 EMMC_D7 SD2_D7 B11 PC7

EMMC_CLK SD2_CLK C9 PE3 EMMC_CMD SD2_CMD A10 PG6

5.1.4. USB support

USB section of STM32MP157FAC3 contains two USB controllers with incorporated PHY. In order to maximally use existing USB features, nanoSOM™ NS02 uses the next structure:


Practically, USB0 OTG Port is used directly as OTG port from CPU (USB2) and user doesn’t need to add anything to carrier board. USB1 Port od CPU is used with external USB bridge (located at nanoSOM™ NS02) dual ports HUB plus LAN port. To have full Host USB support, user must to add only external load switch and power supply (5V) at carrier. This way, nanoSOM™ NS02 is equipped with:

• One OTG port • Two HOST ports (from LAN 9512)

5.1.5. CAN1 and CAN2

nanoSOM™ NS02 contains two CAN channels. External PHY must be added at carrier board.

Signal name Signal Name (CPU) Pin Port CAN1_TX CAN1_TX AB19 PA12 CAN1_RX CAN1_RX B8 PD0 CAN2_TX CAN2_TX Y14 PB6 CAN2_RX CAN2_RX Y8 PB5

5.1.6. UART4, UART5 and UART7

STM32MP157FAC3 contains up to 7 Uarts (some of them only RX, TX pair)


In nanoSOM™ NS02, due to PIN MUXING and to get compatibility’ with NS01, only some UARTS are default provided:

• UART 5 (RX,TX) • UART 4 (RX,TX,CTS,RTS) • UART 7 (RX,TX,CTS,RTS)

Signal name Signal Name (CPU) Pin Port UART5_RX UART5_RX AC5 PB12 UART5_TX UART5_TX AA10 PB13 UART4_RX UART4_RX C3 PH14 UART4_TX UART4_TX N2 PA13

UART4_RTS UART4_RTS C19 PA15 UART4_CTS UART4_CTS AB6 PB0 UART7_RX UART7_RX AA11 PE7 UART7_TX UART7_TX AB12 PF7

UART7_RTS UART7_RTS AA9 PE9 UART7_CTS UART7_CTS Y15 PE10

5.1.7. SPI2, SPI3, SPI4 and SPI5

STM32MP157FAC3 contains total 6 SPI controllers. Unfortunately, no all SPI can be used due to the same reason (PIN MUXING). In addition, NS02 needs to provide the high level of hardware compatibility with NS01. In nanoSOM™ NS02 we have available:

• SPI2 (Two CS*) • SPI3 (One CS*) • SPI4 (One CS*) • SPI5 (One CS*)

Signal name Signal Name (CPU) Pin Port SPI2_CS0* SPI2_CS0* Y13 PG9 SPI2_CS1* SPI2_CS1* AC13 PE8 SPI2_MOSI SPI2_MOSI E1 PI3 SPI2_MISO SPI2_MISO E2 PI2 SPI2_CLK SPI2_CLK Y3 PB10

Signal name Signal Name (CPU) Pin Port SPI3_CS0* SPI3_CS0* AA14 PF9 SPI3_MOSI SPI3_MOSI Y16 PB2 SPI3_MISO SPI3_MISO B5 PD10 SPI3_CLK SPI3_CLK D6 PE0

Signal name Signal Name (CPU) Pin Port SPI4_CS0* SPI4_CS0* AA19 PD13 SPI4_MOSI SPI4_MOSI C6 PE14 SPI4_MISO SPI4_MISO C11 PE5


SPI4_CLK SPI4_CLK B4 PE12

Signal name Signal Name (CPU) Pin Port SPI5_CS0* SPI5_CS0* AA13 PF6 SPI5_MOSI SPI5_MOSI Y10 PF11 SPI5_MISO SPI5_MISO AC11 PF8 SPI5_CLK SPI5_CLK Y11 PH6

5.1.8. Audio OUT- I2S

STM32MP157FAC3 contains three I2S channels, but nanoSOM™ NS02 contains one Audio OUT I2S channel. Note that this port can also be used as SPI1 port.

Signal name Signal Name (CPU) Pin Port AUDA_TX_BCLK I2S1_CK G3 PZ0 AUDA_RX_DATA I2S1_SDI G1 PZ1 AUDA_TX_DATA I2S1_SDO J4 PZ2 AUDA_TX_SYNC I2S1_WS G4 PZ3

AUDA_MCLK I2S1_MCLK H1 PZ6

5.1.9. I2C

STM32MP157FAC3 supports more I2C controllers, but in nanoSOM™ NS02 is used I2C port as system nanoSOM™ NS02 I2C controller. .

Signal name Signal Name (CPU) Pin Port SCL I2C1_SCL AC4 PF14 SDA I2C1_SDA Y4 PF15

Attention: It is used also I2C2 port, but it is connected inside NS02 between CPU and PMIC (it is not routed at external pads).

Signal name Signal Name (CPU) Pin Port SCL_AUX I2C2_SCL G2 PZ4 SDA_AUX I2C2_SDA A2 PH5

5.1.10. SD ports

nanoSOM™ NS02 contains two SD controllers for external SD/SDIO access. Port SD1 is provided for supporting external SD card which can be used also as boot device.


This port is compatible with SD port in NS01. The second one (SD3) is additionally and typical using can be (for example) interface with WiFi cards. Port SD1:

Signal name Signal Name (CPU) Pin Port SD1_CLK SD1_CLK D13 PC12 SD1_CMD SD1_CMD D12 PD2 SD1_D0 SD1_D0 D18 PC8 SD1_D1 SD1_D1 D17 PC9 SD1_D2 SD1_D2 D15 PC10 SD1_D3 SD1_D3 D16 PC11

SD1_CD* SD1_CD* V2 PG2 SD1_WP* SD1_WP* U1 PF3

Port SD3:

Signal name Signal Name (CPU) Pin Port SD3_CLK SD3_CLK B7 PG15 SD3_CMD SD3_CMD A5 PF1 SD2_D0 SD2_D0 B9 PD1 SD3_D1 SD3_D1 B6 PD4 SD3_D2 SD3_D2 A7 PD5 SD3_D3 SD3_D3 D10 PD7

5.1.11. Display interface (parallel RGB)

The LCD-TFT display controller of nanoSOM™ NS02 provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to WXGA (1366×768) @60 fps resolution with the following features: • 2 display layers with dedicated FIFO • Color look-up table (CLUT) up to 256 colors (256×24-bit) per layer • Up to 8 input color formats selectable per layer • Flexible blending between two layers using alpha value (per pixel or constant) • Flexible programmable parameters for each layer • Color keying (transparency color) • Up to 4 programmable interrupt events • AXI master interface Table below shows video out (LCD) bits mapping

Signal name Signal name (CPU) Pin Port LCD_DATA0 LCD_B0 D19 PE4 LCD_DATA1 LCD_B1 K4 PG12 LCD_DATA2 LCD_B2 U2 PA3 LCD_DATA3 LCD_B3 Y7 PG11 LCD_DATA4 LCD_B4 E4 PI4 LCD_DATA5 LCD_B5 F3 PI5


LCD_DATA6 LCD_B6 F4 PI6 LCD_DATA7 LCD_B7 K3 PD8 LCD_DATA8 LCD_G0 AA7 PB1 LCD_DATA9 LCD_G1 C10 PE6

LCD_DATA10 LCD_G2 D1 PH13 LCD_DATA11 LCD_G3 AB11 PG10 LCD_DATA12 LCD_G4 B3 PH4 LCD_DATA13 LCD_G5 C1 PI0 LCD_DATA14 LCD_G6 P4 PI11 LCD_DATA15 LCD_G7 AB9 PG8 LCD_DATA16 LCD_R0 AB4 PH2 LCD_DATA17 LCD_R1 J2 PD15 LCD_DATA18 LCD_R2 D5 PH8 LCD_DATA19 LCD_R3 C5 PH9 LCD_DATA20 LCD_R4 AA18 PA11 LCD_DATA21 LCD_R5 AB5 PC0 LCD_DATA22 LCD_R6 B2 PH12 LCD_DATA23 LCD_R7 D3 PE15

In addition to standard Data signals, video controller is followed with some additional control signals:

Signal name Signal Name (CPU) Pin Port LCD_DE LCD_DE Y12 PF10

LCD_HSYNC LCD_HSYNC T1 PI10 LCD_VSYNC LCD_VSYNC H4 PI9

LCD_CLK LCD_CLK AC14 PG7 LCD_RST ((****) LCD_RST T2 PA14

EN_VDD (*) GPIO (OUT) D9 PF4 EN_BL (**) GPIO (OUT) A14 PF2

BL_PWM (***) TIM2/CH1 V3 PA5 (*) Signal used as enable display supply. (**) Signal used as backlight enable signal. (***) Signal used as PWM adjustment signal for backlight (dimming). (****) Signal LCD_CLK is not officially part of LCD interface. This signal is simple GPIO and it is placed in order to get full compatibility with LCD interface in NS01. It’s using is not mandatory

5.1.12. Ethernet

It is already described that STM32MP157FAC3 contains only one RMII channel. In order to support two Ethernet ports, nanoSOM™ NS02 introduces LAN9512 USB/LAN bridge to “replace” second RMII port. This way, we get nearly ideal replacing of NS01 in terms of using Ethernet. This second LAN port (from LAN9512) is real LAN port (not RMII) and user should only to add Ethernet transformer at carrier board to get full featured LAN port (of course also some LEDS which are already provided by LAN9512). In case that user wants to have carrier which will host both boards (NS01 and NS02) some precautions must be observed (using some zero ohm assembly options).


See for details in separate chapter.

Signal name Signal Name (CPU) Pin Port RMII1_CRS_DV RMII1_CRS_DV AB8 PA7

RMII1_RX0 RMII1_RX0 AC7 PC4 RMII1_RX1 RMII1_RX1 AB7 PC5

RMII1_TXEN RMII1_TXEN AB1 PB11 RMII1_CLK RMII1_CLK AA4 PA1 RMII1_TX0 RMII1_TX0 AA2 PG13 RMII1_TX1 RMII1_TX1 AA1 PG14

ETH_MDIO ETH_MDIO AC3 PA2 ETH_MDC ETH_MDC AA6 PC1

Table above shows signals included in RMII interface. Concerning LAN9512, it is followed by one 4Kbit, 3 Wire serial EEPROM inside NS02. Drawing below shows part of LAN 9512 inside nanoSOM™ NS02 responsible for second LAN port. All signals at right side (including VDD33A) are routed at external pins for direct connection with transformers and LEDS

5.1.13. GPIO and Analog inputs

Various GPIO are provided, using GPIO pins from STM32MP157FAC3. Under GPIO we consider various generic input/output signals. These signals are available to user as GPIO and are not dedicated to some special interfaces, presented above. Note that also these “special” interfaces mentioned above could, in one custom design, be used also as GPIO. For example, if user has not need for Video input, he could all these pins of Parallel video input use for GPIO or to get more UARTS or for some other needs. Of course, this change needs appropriate firmware support. One second example:

Signals routed toexternal pins


Actual NS02 doesn’t support QUAD SPI although STM32MP157FAC3 supports two channels. This support is eliminated from simple reasons:

• Available pins (pads) at external “connectors” are already occupied. • PIN MUX inside CPU couldn’t find path for some signals when possible CPU pads are already

occupied by other peripherals. This way, user always can additionally modify NS02 to get some features, not available in actual (default) NS02. One more to underline, this change needs well understanding of PIN MUX and firmware change.

Signal name Signal Name (CPU) Pin Port GPIO1/PWM1 TIM4-CH3 L3 PD14 GPIO2/PWM2 TIM4-CH1 Y18 PD12

GPIO3 AC10 PD11 GPIO4 Y6 PG5 GPIO5 AB2 PG4 GPIO6 AC2 PG0 GPIO7 AA3 PH3

Signal name Signal Name (CPU) Pin Port AN_IN0 ANA0 U3 ANA0 AN_IN1 ANA1 U4 ANA1 AN_IN2 AN_IN2 V4 PA4 AN_IN3 AN_IN3 W2 PC3 AN_IN4 AN_IN4 AC8 PA6 AN_IN5 AN_IN5 Y9 PF12

Analog inputs are single ended with Vref = +1V8. Vref+ pin is supplied locally (using CPU reference) and it is set to 1V8 (default).User can use other local references (see data sheet of CPU) or even external (+3V3) with filtered system supply (see drawing below) via zero ohm R49.

Default R49 is not mounted(used local Vref).


Attention: This document doesn’t encourage any solder/desolder at extremely small NS02, but only indicates one hypothetical modification to get some feature more. Picture below shows position of R49 at bottom side.

5.1.14. Buzzer

nanoSOM™ NS02, like NS01, supports Buzzer control. It is PWM output, controlled by one of CPU local PWM timers. It is used TIM5/CH1, connected to port PA0 (pin AB3)

5.1.15. DCMI (Digital Camera interface)

nanoSOM™ NS02 embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 12-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to 60 Mbyte/s using a 34 MHz pixel clock. It features: • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8, 10, 12 • Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode

• Capability to automatically crop the image


Signal Name Signal Name (CPU) Pin Port DCMI_PIXCLK DCMI_PIXCLK Y2 PC2 DCMI_HSYNC DCMI_HSYNC K1 PD9 DCMI_VSYNC DVMI_VSYNC D11 PB7

DCMI_D11 DCMI_D11 B1 PH15 DCMI_D10 DCMI_D10 D2 PD6 DCMI_D9 DCMI_D9 W4 PH7 DCMI_D8 DCMI_D8 E3 PI1 DCMI_D7 DCMI_D7 F2 PI7 DCMI_D6 DCMI_D6 A3 PE13 DCMI_D5 DCMI_D5 D14 PD3 DCMI_D4 DCMI_D4 A4 PE11 DCMI_D3 DCMI_D3 C8 PE1 DCMI_D2 DCMI_D2 C4 PH11 DCMI_D1 DCMI_D1 C2 PH10 DCMI_D0 DCMI_D0 A8 PA9

Really DCMI module in STM32MP157FAC3 receives also 14 bit data, but in nanoSOM™ NS02 it is not provided.

5.1.16. Mipi DSI Video out

In addition to LCD 24 bits parallel interface, nanoSOM™ NS02 provides also MIPI DSI (Display Serial Interface) two lanes. This interface is optional and can’t be used with LCD contemporary. In case of using MIPI DSI, a lot of pins from LCD interface, remain free for other using.

Signal name Signal Name (CPU) Pin Port DSI_D0_P DSI_D0_P C15 DSI_D0_N DSI_D0_N DSI_D0_N B15 DSI_D0_P DSI_D1_P DSI_D1_P B17 DSI_D1_N DSI_D1_N DSI_D1_N A17 DSI_D1_P DSI_CK_P DSI_CK_P B16 DSI_CK_N DSI_CK_N DSI_CK_N A16 DSI_CK_P

5.1.17. Two system LEDS

nanoSOM™ NS02 contains two system LEDS. These LEDS are general purpose and these are:

1) LED Error


It is RED led. Purpose of this LED is that at power up is active (ON) and after successful boot, if everything is OK, system should set to OFF. And also if something in operating mode is out of normal behavior, it should be informed via this LED. This LED is connected to port PZ7 (pin J3), see drawing below.

2) LED DL (Diagnostic LED)

This led is GREEN and it used as general purpose LED for signaling some messages (diagnostic) if needs. This LED is connected to port PF13 (pin Y3), see drawing below.

5.2. AUX Circuits

nanoSOM™ NS02 contains some additional circuits.

LED Error

LED DLBoard origin

From PZ7 (pin J3)

From PF13 (pin Y5)


5.2.1. RTC

For nanoSOM™ NS02 for RTC purpose is used M41T83 RTC chip, although STM32MP157FAC3 has own RTC. Solution with M41T83 RTC is much better in power OFF (battery) mode. Chip is supplied (standby mode) with Vbb (Vbattery). Vbb can be in range 2-5.5 V. Consumption in standby mode is about 400 nA.

5.2.2. SEEPROM

nanoSOM™ NS02 contains one standard I2C SEEPROM (X24C04) with address 0x50.

5.2.3. RES_OUT*

nanoSOM™ NS02 provides RES_OUT* as general RESET_OUT (active zero) for peripherals on board and these at carrier. This signal is really “copy” of local, on board RESET (Power on reset*). In addition, also we have possibility’ that via CPU (SOFT_RST*) perform RES_OUT* in any moment. GPIO for SOFT_RST* is located at PZ5 (pin H2) of CPU. RES_OUT* control includes also possibility that one external RES_IN* signal via supervisor U13 performs hardware reset (see drawing below).

5.3. Power supplies

Power supply for nanoSOM™ NS02 is based at STPMIC1C. STPMIC1C is special PMIC, built for STM32MP157FAC3.

Local on board RESET (POR*)


STPMIC1C is provided for typically 5V input or battery (min 3.8V), so some additional circuits are added to support also 3V3 (+- 5%) Attention: User must provide well regulated +3V3 without drops or overvoltages. because this voltage directly goes (via load switches) to some circuits inside NS02. In addition, STPMIC1C has Vin_OK = 3.1V (minimal voltage to start), so it is recommended to supply nanoSOM™ NS02 with some ten millivolts more respecting +3V3.

5.4. Internal and External Pads (“Connectors”)

This and next page show “connectors” for:

• Internal connectors (pads) • External connectors (pads)

These drawings port the same info as tables, presented before, and goal of these drawings is only to give user one compact view and position of all signals. Internal connectors (pads)


External connectors (pads)


5.5. Board View

The next two pictures below show TOP and BOTTOM (REAR) side of nanoSOM™ NS02.


Picture above shows TOP side of nanoSOM™ NS02.

Picture below shows BOTTOM side of nanoSOM™ NS02.

Attention: It is board through view (from TOP side view, where TOP side is transparent).


Take attention to external (at board edges) and internal I/O pads.

6. Building carrier board pattern for hosting nanoSOM™ NS02

This chapter shows building nanoSOM™ NS02 pattern (footprint, shape) at carrier board, where nanoSOM™ NS02 will be soldered.


Building shape is fairly simple because pin positions (IO PADS) are mainly full symmetric respecting board edges and virtual board center. Note that pattern (shape) for NS01 is only subset of NS02 shape. Practically. NS01 can be mounted in carrier pattern of NS02. Note also that 10 tamper pads (see below) has not any connection towards resources inside NS02 and these are built only to have pattern compatibility’ with NS01. Shortly, user’s procedure is:

• Create shape outline for virtual nanoSOM™ NS02 (25.4mm x 25.4 mm) and board hole inside (21.6mm x 21.6mm).

• Really TOP_LEFT angle is inclined, so LEFT and TOP edges are 23.50mm. • Create External IO PADS at board edges (TOP 31 + RIGHT 34 + BOTTOM 34 and LEFT 32). • Create Internal IO PADS at hole edges (TOP 20 + RIGHT 20 + BOTTOM 20 + LEFT 9) • Create 10 TAMPER PADS

We strongly suggest to follow this procedure in order to build appropriate carrier shape for nanoSOM™ NS02:

1) Outline: Draw (outline) rectangle 25.40 mm x 24.50 mm (dimensions of nanoSOM™), having in mind that TOP-LEFT angle is inclined.

2) TOP ext. connector (pads T4-T34): Place 31 rectangle PADS 0.508mm x 1.041mm (20mil x 41 mil) with distance 0.7mm between them. First PAD center is 3.25mm right from LEFT edge and 0.075 mm lower of TOP edge of outline.

3) RIGHT ext. connector (pads R1-R34): Place 34 rectangle PADS 1.041mm x 0.508 (41mil x 20 mil) with distance 0.7mm between them. First PAD center is 1.15mm lower of TOP edge and 0.075 mm left from RIGHT edge of outline.

4) BOTTOM ext. connector (pads B1-B34): Place 34 rectangle PADS 0.508mm x 1.041mm (20mil x 41 mil) with distance 0.7mm between them. First PAD center is 1.15mm left from LEFT edge and 0.075 mm above BOTTOM edge of outline.

5) LEFT ext. connector (pads L3-I34): Place 32 rectangle PADS 1.041mm x 0.508 (41mil x 20 mil) with distance 0.7mm between them. First PAD center is 2.55mm lower of TOP edge and 0.075 mm right from LEFT edge of outline.

6) TOP int. connector (pads IT1-IT20): Place 20 rectangle PADS 0.7mm x 1.0mm (27.6mil x 39.4 mil) with distance 1mm between them. First PAD center is 3.20mm right from LEFT edge and 1.4 mm under TOP edge of outline.

7) RIGHT int. connector (pads IR1-IR20): Place 4 rectangle PADS 1.0mm x 0.7mm (39.4 mil x 27.6 mil) with distance 1mm between them. First PAD center is 1.40mm left from RIGHT edge and 3.20 mm under TOP edge of outline.

8) BOTTOM int. connector (pads IB1-IB20): Place 20 rectangle PADS 0.7mm x 1mm (39.4 mil x 27.6 mil) with distance 1mm between them. First PAD center is 3.20mm right from LEFT edge and 1.40 mm above BOTTOM edge of outline.


9) LEFT int. connector (pads IL1-IL7 and IL19-IL20): This connector is divided in two parts,. First place 7 rectangle PADS 1.0mm x 0.7mm (39.4mil x 27.6 mil) with distance 1mm between them. First PAD center is 1.4mm right from LEFT edge and 3.20mm lower of TOP edge of outline. After that, place two pads IL19 and IL20 the same type as previous 7. X position for these two pads is the same as pads IL1-IL7 and Y position is the same as Y position of pads IR19 and IR20.

10) TAMPER pads (Tamper 1-10). Place 10 circle PADS, D=30mil (0.762mm) with distance 1mm between them. First PAD is located: 1.20mm from LEFT edge and 10.83 mm from TOP edge of outline.

11) PCB hole: Provide PCB hole 21.60mm x 21.60mm. Note that PCB hole is full symmetric in X and Y axis, respecting virtual board center. TOP side of carrier (under microSOM™) can be used for routing (of course where is available).

12) Provide some arrow at silk screen near LEFT TOP angle for board orientation (origin).

For external, internal and tamper IO pads: Make Solder mask shape 4 mils bigger of PAD (all PADS). Make Solder past shape the same as PAD. Drawing below shows picture of NS02 carrier board pattern with some main dimensions.


Two drawings below show more details for building internal and external pins (except TAMPER pads). It is presented LEFT_TOP angle as specific one (some PADS are missing) and TOP_RIGHT angle. Other two angles are not presented, because are full symmetric with TOP_RIGHT angle (only different orientation). Really, these two drawings are only for some additional verification. If customer strongly follows procedure, presented above (1-12), shape creation shouldn’t be any problem. Building TAMPER PADS is also very simple. Customer should start with first TAMPER PAD (see dimensions and position above) and simple add adjacent PADS with pitch 1mm.

25.40mm

21.60mm

25.4

0mm

21.6

0mm

23.5

0mm

10.8

3mm

1.20mm

Origin

HOLEedge


6.1 One Important addition for internal pads

Procedure above, presents building all PADS for nanoSOM™ NS02 as simple TOP only SMD pads. Really, internal pads are not so simple how are presented above.

0.075mm

0.075mm

3.25mm

0.7mm

1.0mm

1.4m

m

1.0m

m

0.7m

m2.

55m

m3.20mm

1.4mm

3.20

mm

T4

IT1

IL1L3

0.075mm

0.7mm 1.15mm

T34

R1

1.15

mm

0.7m

m

IT20IR1

0.075mm

3.20mm1mm

1.4m

m

3.20

mm

1mm

1.4mm


This procedure was part 1 in internal pads creation. Goal was not to complicate creation immediately with special shapes for internal PADS. Really, internal PADS are not so simple and this chapter is really part 2 (continuation of pads creation). Practically, customer must take special attention to internal PADS only (not external and not Tamper) and this chapter explains it. Practically, due to more reasons, simple only SMD PADS for internal PADS (total 20 + 20 + 20 + 9) must be modified:

• Reason 1. There is no sufficient space at carrier board for access to internal PADS via using normal VIAs

• Reason 2. Creating these PADS with metallization offers possibility to better control soldering of these internal PADS.

Drawing below shows in which way internal PADS must be modified.

• TOP layer holds original dimensions and position (0.7mm x 1.0 mm) with adding ARC at hole edge

• All other signal layers (including BOTTOM) must have “COOPER” and ARC like TOP layer, but can be really smaller respecting TOP PAD. For example 0.5 mm x 0.7 mm is one good choice. Customer can hold all signal layers (of course also BOTTOM) the same as TOP layer, but there is no any sense to lose precious PCB space.

It is very important that “ARC” side of PADS is metalized. This way, we have:

1) PADS connection to all layers without classic hole. 2) Possibility of (optionally) manual resoldering if there is need for it.

This chapter describes procedure for building this complex PAD in PCAD6 tool. (PCAD6 doesn’t allow directly built this type of PAD, but with some explanation for PCB manufactures. it can be resolved).

SimpleSMD PAD

ModifiedSMD PAD

ModifiedSMD PAD

(other signal layers)

(TOP layer)

Hole edge

1mm

1mm

0.5m

m

0.7mm 0.7mm 0.7mm


Some newest tools probably provides direct this way of PADS building.

1) Create normal “through hole” PADS with rectangle shapes (explained above) with

rectangle 0.7mm x 1mm at TOP layers for 20 + 20 pins horizontal internal PADS and 1mm x 0.7 mm for total 20 + 9 vertical internal PADS also at TOP layer (respect pad positon explained in previous chapter). For other signal layers create “smaller” PADS 0.7mm x 0.5 mm (0.5mm x 0.7mm) or, if user prefers, leave the same dimension like in TOP layer.

2) Create these PADS with “virtual” hole 1mils in PAD center.

3) In production file (GBR) inform PCB manufacturer to change “virtual” hole 1mm with real hole D=27mils and to move them 29mils towards board center.

4) After metallization process and removing central rectangle hole from board, we will have these complex PADS, where part of ARC (see drawing below) will be metallized. This way all signal layers for internal pads are connected and we don’t need VIA for them.

Here is, for example, directive for creation these special pads, used by EXOR

6.2 Some specific signals

This chapter describes some specific signals (system signals), important in carrier board building. Drawing below shows typical using these signals: nanoSOM™ NS02 is supplied by +3V3S (system) supply (+3V3 +- 5 %)


1) VBB is input for connecting to some Battery source, used for RTC. Typical are used Lithium

battery, Lithium rechargeable or Super CAP. Range is 2V-5.5V. In case of using rechargeable battery or Super CAP, user must provide additional circuits at carrier board.

2) RES_OUT* is standard RESET_OUT* signal for resetting external circuits, located at carrier board. Note that RES_OUT* follows local, on board main reset (signal CPU_RST). In addition, also CPU () can independently create RES_OUT* via signal RST_OUT_L (see chapter 5.2.3 –RES_OUT*).

3) RES_IN* is optionally RESET_IN* (Max +3V3, active 0) signal for whole system, coming from carrier board. For example can be used external standard CPU supervisors, or simple manual RESET key. Using external circuits is optional, because nanoSOM™ NS02 contains embedded power on RESET circuits.

4) PFAIL_IN* is optionally PFAIL_INTERRUPT*, for interrupting CPU in case of early power supply power detection. Really, there is not dedicated PFAIL_IN* pin in nanoSOM™ NS02. It is only presented one idea for using any of available INT (really GPIO). It could be important for backup some critic application, where early power down event can be used for file or application closing. Typical using for this is connecting this signal to some comparator which controls main power supply.

5) POW_GOOD is one mandatory signal (out from nanoSOM™ NS02, active high) to enable supply auxiliary circuits at carrier board. nanoSOM™ NS02 is supplied by +3V3S (system) from carrier board, but supply for circuits at carrier must be controlled by this signals to respect power up procedure for CPU at nanoSOM™ NS02. External circuits, connected to I/O pins of nanoSOM™ NS02 shouldn’t be supplied before POW_GOOD is asserted (see drawing above).

Used for carriercircuits supply

DC/DC24V/3V3

Pow_good

+3V3

In Load switchOr P-CH mosfet

+3V3S nanoSOMsupply

Out

DC/DC24V/3V3

PFAILDetection

(optionally)

PFAIL_IN*INT

RESET_INcircuits

(optionally)

RESET_inRes_in*

Res_out*

(optionally)

(optionally)

SYS_RESET_OUT*(optionally)

Battery orSuper CAP

Vbb2V-5.5V

24V

nano

SOM

(active HIGH)


6.3 Using FRAM with nanoSOMTM NS02

nanoSOM™ NS02 doesn’t contain FRAM (on board), but due to fact that FRAM can be often used, it is reserved SPI channel for direct support at user’s carrier board. It means that user must connect FRAM always in this way (see below) in order to have direct FRAM support. It is used SPI2 channel. Note that SPI2 channel is only channel with two CS*. CS0* is reserved for FRAM and CS1* is free for user (see bottom using TPM module). This way, SPI2 channel remains free (using CS1*) for user. See two drawings below.

6.4 Using TPM module with nanoSOMTM NS02

In case that nanoSOM™ NS02 is used for Trusted zone application, good solution is using with TPM (Trusted Platform Module) SLB9670. Module SLB9670 exists in version TPM 1.2 and TPM 2.0, which are fully compatible with hardware view point. The best solution is to connect to, above mention SPI2 channel, using free CS1*. Practically, using FRAM and TPM module SLB9670 SPI2, channel is full occupied for these two system functions.

Picture below shows using TPM SLB9670 module with nanoSOM™ NS02:

nanoSOMNS02

SPI3

FRAM

SPI2_CS0*SPI2_MOSISPI2_MISOSPI2_CLK

SPI2_CS1*SPI2_MOSISPI2_MISOSPI2_CLK

Remains SPI2channel free for user

Carrier board


It is provided also interrupt from SLB9670. Solution for interrupt can be to use one of four free GPIO.

6.5 NS01 and NS02 compatibility

One of main requests in phase of nanoSOM™ NS02 building was compatibility with nanoSOM™ NS01. Customer should have choice to select less expensive NS01 and higher performance NS02 in the same carrier board design (optionally). It wasn’t simple task because processors are different and also embedded peripherals are not the same. For example, NS01 CPU has two RMII ports, while CPU of NS02 has one RMII. In addition, it was also hard job to route NS02 peripherals to exactly the same positions like these in NS01. Anyway, we accomplished good job and we can say that boards have high level of compatibility. This chapter explain this issue and shows points where special attention should be taken,


NS01 carrier pattern NS02 carrier pattern

First diference is mechanical (number of pads). NS01 is only subset of NS02. This chapter explains compatibility of all resources in NS01 and NS02 and show optionally differences and how to resolve. In this chapter below with black caption are presented points withot issues and with red caption points where customer must take attention. Attention: This chapter describes compatibilty’ of default NS01 and NS02 versions, presented in data sheets. It means that if, for example, SPI port (X) in NS01 can be used also as additional UART (Y), it is only some special features. probably not supported in NS02 and not analyzed.

6.5.1. Common NS01 and NS02 resources

Power Supply Power supply contains five +3V3 pins and numerous GND pins distribuited around all edges. Of course, NS02 contains some GND pins more. SPI ports Both boards contain 4 SPI ports working in master mode. Three ports are with 1 CS* and one port is with two CS*. UARTS Both boards contain 2 ports with 4 lines (TX,RX,RTS,CTS) and one port with 2 lines (RX,TX).


USB Both boards contain one OTG port and two HOST ports. Connection these ports in carrier is very simple. OTG port provides directly 100mA 5V supply in OTG or HOST mode, directly form NSx, while two USB HOSTS must provide USB_5V supply (100 mA or 500mA) using USB load switches. For example can be used MIC2009A-1. Load switches must be equipepd with one control input EN (activ high) and open drain output OC* (overcurrent). NS01 has separate control EN and OC* and , while NS02 really has one control signal. In schematic we can see two signals, but these are connected inside NS02. This control signal is capable to support both function (EN and OC*) in the same pin in NS02. Customer simple need to connect both signals. LCD Video out Both boards contain 24 bits LCD (RGB) video controller followed with additional control signals (En_VDD, PWM, Wn_BL). Main control signals (RES_OUT*, RES_IN*, POW_GOOD) Both boards contain these control signals. Boot signal (Boot M0, M1,M2) Both boards contain three control signals. responsible for BOOT. See in next chapter for details. SD port Both boards contain main SD port. Can be used standard SD or micro SD card. CAN port Both boards contain two CAN ports GPIO Both boards contain seven GPIO. Some of them (GPIO1 and GPIO2) can be used also as PWM. JTAG Both boards contain JTAG, but these is one difference. JTAG port in NS01 is possible use also as I2S port, while NS02 contains separate JTAG port and I2S port . It means that customer, in case of using I2S in own design, and if wants to provide using both boards (NS01 and NS02) must via zero ohm to separate these lines/


Ethernet It is alraedy noted before that the main difference between NS01 and NS02 is in Ethernet ports. First port (RMII1) is the same for both boards, but second one is different

• NS01 for second port uses separate RMII2 from CPU (the same like RMII1) • NS02 for second port uses LAN port from LAN9512 HUB inside NS02.

In order to have solution which satisfy both cases (NS01 and NS02), one typical solution could be one, presented at next page. This drawing shows one typical RMII interface, which can be used for:

• RMII1 port of NS01 and NS02 • RMII2 port of NS02

I2S controller

Zero ohm

Zero ohm

Position of JTAG

Position of I2S in NS02


Drawing shows how is possible in case of using NS02 avoid whole PHY chip and go direct from NS02 pads to appropriate points near the transformer/connectors.


It is presented default mounting for RMII1 (for NS01). With dashed lines are presented zero ohm, which are mounted for NS02 and which really bypassing RMII PHY. This schematic is one ideal and shows only necessary connections, but there is serious job in real PCB realization. Customer must to provide:

• Don’t leave wire stubs-antenas (part of wires remained at inputs/outputs of unsoldered parts) • Take attention that RX and TX are realy differential pairs and route them taking in account all

necessary rules for such high speed signals. • In case of using NS02, place R345 = 10 Ohm

To achive this goal, probably more zero ohm should be added. Pins IL2,IL3,IL4 Also pins IL2, IL3 and IL4 can have possible issue.

Pin IL2: For NS01 it is signal JTAG MODE and should be connected via 560 ohm to GND For NS02 it is signal DSI_D1_P. Having in mind that NS01 doesn’t contain DSI out, realization is very simple. Drawing below shows typical solution. It is important only that resistor for JTAG MODE creates very small stub and this way have negligible influence to high speed DSI_D1_P signal.

Pin IL2

Pins IL3,IL4

DSI_D1_P(for NS02)

(for NS01)560


Pins IL3, IL4: For NS01 to these pins is routed one diff. clock from CPU. This clock mainly is not used. For NS02 these two pins are used as DSI_D1_N and DSI_D0_P. Practically, it means that pins IL3 and IL4 are not any issue if customer uses LCD (not DSI). Even if customer uses DSI, and it is possible only with NS02, so anyway there is no problem, but customer should be aware of these minimal differences.

6.5.2. Only NS02 resources

In chapter above are described resources common for NS01 and NS02. This chapter depicts resources available only in NS02. Normally, these resouces are located only at additional internal pads (see below). In chapters before are well described all of them. This chapter only gives one comprehensible review of all of them.

DCMI AN_IN

MIP

I DSI

SD3

I2 S


6.5.3. Boot modes for NS02/NS01 and differences

For both CPU (NS01 and NS02) are provided total 3 pins for BOOT. These bits are located at pins R8, R9 and R10.

PIN NS01 NS02 R8 Boot mode 1 Boot mode 2 R9 Boot mode 0 Boot mode 0 R10 Boot mode Ctrl Boot Mode 1

NS01 CPU inside NS01 really contains two BOOT pins (Boot mode 0 and Boot mode 1). In addition, there is also Boot mode CTRL pin (R10). NS01 is done in this way that this pin is responsible for controlling Boot mode 0 inside NS01 (inversion). It means:

• Pins R8 and R9 can be left free, because there is local pull down inside NS01. • Via pin R10 (Boot mode control) user can select either Boot from FUSE/eMMC (leave

floating) or Boot from USB-serial (connect Boot mode control to GND). Boot mode 0 and Boot mode 1 can even be used as GPIO after finishing BOOT process. Customer must take attention that start up levels at these pins, coming from external circuits, will not influence levels in boot time. It is recommended to use them use as outputs for places with meaningless values at start up.

NS02


Boot procedure for NS02 is a little different. The next table shows boot modes. Note that there is also other modes, without interests for NS02 (not provided).

Boot2 Boot1 Boot0 Initial boot mode Comments

0 0 0 UART and USB Wait incoming connection on: UART4/5/7 USB high-speed device

0 1 0 eMMC eMMC on SDMMC2

1 0 0 Reserved (no boot) Used to get debug access without boot from Flash memory

1 0 1 SD card SD card on SDMMC1 (1) 1 1 1 SD card SD card on SDMMC1 (2)

1) Boot source could be changed by OTP settings (e.g. initial boot on SD card, then eMMC with OTP settings)

2) Could be disabled by OTP settings. Boot pins for NS02 ae simple routed to R8, R9 and R10.

Note that NS02 has also SD card mode boot what is very usefull. Drawing above shows one simple way to select one of three modes, using only one jumper. Note that really case 0 0 0 we can’t get with these circuits, but if valid boot image is not found inside eMMC, CPU will automatically pass to boot from UART/USB, what is equivalent to condition 0 0 0.


Conclusion: Boot procedure for NS01 and NS02 are different, but designs are done in way to provide as more is possible similarity. We can see that there is one common control signal, located at pin R10. This signal is controlled grounding via simple jumper. For other two pins R8, R9 user simple need connect or leave in order to get requested boot mode.

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