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Page 1: Radar Signal Detection Using TMS320C50

CHAPTER 1

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DIGITAL SIGNAL PROCESSING

Digital signal processing (DSP) is concerned with the use of programmable

digital hardware and software (digital systems) to perform mathematical operations on a

sequence of discrete numbers ( a digital signal). Such processing is needed to facilitate

the extraction of information embedded in the signal.

1.1 INTRODUCTION

Since World War II, if not earlier, electronics engineers have speculated on the

applicability of digital hardware techniques to the many problem areas in which signal

processing plays a role. Thus, for example, Laemmel (1948) reports a lunchtime

conversation among Shannon, Bode and several other Bell Telephone Laboratories

scientists on the possibility of employing digital elements to construct a filter. Needless

to say, the conclusion then was not favorable. Cost, size and reliability strongly favoured

analog filtering and analog spectrum analysis techniques. In the 1950’s Stockham (1955)

reports that Linville, at the time an MIT professor, discussed digital filtering at graduate

seminars. By then, control theory based partly on Hurewiez’s (1945) work, had become

established as a discipline, the concepts of sampling and its spectral effects were well

understood and the mathematical tools of z-transform theory, which had existed since

Laplace’s time, were propagating into the electronics engineering community.

Technology at that point, however, was only able to support practical efforts to be

directed towards either low-frequency control problems or low-frequency seismic signal

processing problems. While seismic scientists made notable use of digital filter concepts

to solve many interesting problems, it was not until the mid 1960’s that a more formal

theory of digital signal processing began to emerge. By then, the potential of integrated

circuit technology was appreciated and it was not unreasonable to imagine complete

signal processing systems that could best be synthesized with digital components.

The first major contributions to the field of digital signal processing were by

Kaiser (at Bell Laboratories) in the area of digital filter design and synthesis. Kaiser’s

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work showed clearly how to design useful digital filters using the bilinear transform. At

about that time tremendous impetus was given to this emerging field by the Cooley-

Tukey (1965) paper on a fast method of computing the discrete Fourier transform, a

method that was subsequently popularized and extended via many papers in the IEEE

Transactions of the Group on Audio and Electro-acoustics and other journals. This set of

techniques has come to be known as the Fast Fourier Transform (FFT) technology. Its

value lies in the reduction (by one to two orders of magnitude for most practical

problems) in computing time for the discrete Fourier transform (DFT).

Digital signal processing is an area of science and engineering that has developed

rapidly over the past 30 years. This rapid development is the result of the significant

advances in digital computer technology and integrated-circuit fabrication. The digital

computers and associated digital hardware of three decades ago were relative by large

and expensive and, as a consequence, their use was limited to general–purpose non-real

time (off-line) scientific computations and business applications. The rapid

developments in integrated-circuit technology, starting with medium scale integration

(MSI) and processing to large scale integration (LSI) , and now, very large scale

integration (VLSI) of electronic circuits has spurred the development of powerful,

smaller, faster and cheaper digital computers and special purpose digital hardware. These

inexpensive and relatively fast digital circuits have been made it possible to construct

highly sophisticated digital systems capable of performing complex digital signal

processing functions and tasks, which are usually too difficult and /or too expensive to be

performed by analog circuitry or analog signal processing systems. Hence many of the

signal processing tasks that were conventionally performed by analog means are realized

today by less expensive and often more reliable digital hardware.

Of course, it is not true that digital signal processing is the only solution for all

signal processing problems. Indeed, for many signals with extremely wide bandwidths,

real time processing is a requirement. For such signals, analog or, perhaps, optical signal

processing is the only possible solution. However, where digital circuits are available

and have sufficient speed to perform the signal processing, they are usually preferable.

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Not only do digital circuits yield cheaper and more reliable systems for signal

processing, they have other advantages as well. In particular, digital processing hardware

allows programmable operations. Through software, one can more easily modify the

signal processing functions to be performed by the hardware. Thus digital hardware and

associated software provide a greater degree of flexibility in system design. Also, there is

often a higher order of precision achievable with digital hardware and software compared

with the analog circuits and analog signal processing systems. For all these reasons, there

has been an explosive growth in digital signal processing theory and applications over

the past three decades.

1.2 AIM

The aim of the project is to develop a suitable algorithm and hardware interface

for RADAR signal detection using real time digital signal processor TMS320C50

1.3 AN OVERVIEW OF DIGITAL SIGNAL PROCESSING

Thus the field of digital signal processing has grown enormously in the past

decade to encompass and provide firm theoretical background for a large number of

individual areas. Fig 1.1 illustrates one view of how the field has emerged and spread

out. Since digital signal processing, for the most part, refers on the theory of discrete-

time linear time-invariant system, this has major unifying influence for the entire field.

The major sub-divisions of the field of digital signal processing are digital

filtering and spectrum analysis. The field of spectrum analysis is broken into calculation

of spectra via the Discrete Fourier Transform(DFT) and via statistical technique as in the

case of random signals, (eg, quantization noise in a digital systems). The Fast Fourier

Transform(FFT) and the related area of fast convolution are almost exclusively used in

practical spectrum analysis techniques. Two-dimensional signal processing is relatively a

new area.

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The remaining aspects of digital signal processing, as shown in Fig 1.1, are the

important topics of implementations of digital systems and application areas. Almost all

the theoretical considerations involved in the design of digital filters and spectrum

analyzers would be of little value if a good understanding of the issues involved in

practical implementations of such systems in finite precision software or hardware were

not also available. Thus the area of implementation is first concerned with the

mathematical basis of quantization in discrete systems; then, depending on whether a

software or hardware implementation is desired, it is important to understand the inherent

limitations and advantages in both these implementations.

It should be noted that all the application areas listed in Fig 1.1 are established

fields that have traditionally relied on analog components for their signal processing.

Many questions have been raised as to the desirability of applying digital signal

processing technology when so much progress has been and continues to be made with

analog methods. Although many signal processing systems will be most economically

implemented with analog methods, it is the capability of digital systems to achieve a

guaranteed accuracy and essentially perfect reproducibility that is so appealing to

engineers. This, in turn, will help motivate components manufacturers to emphasize

ways of improving digital technology that should eventually bias the economics toward

the digital implementation. To summarize, the importance of digital signal processing

should eventually surpass that of analog signal processing for the same reasons that

digital computers have surpassed analog computers.

1.4 BASIC ELEMENTS OF DSP

Most of the signals encountered in science and engineering are analog in nature.

That is, the signals are functions of a continuous variable, such as time or space, and

usually take on the values in a continuous range. Such signals may be processed directly

by appropriate analog systems (such as filters or frequency analyzers) or frequency

multipliers for the purpose of changing their characteristics or extracting some desired

information. In such a case we say that the signal has been processed directly in its

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analog form, as illustrated Fig 1.2. Both the input signal and the output signal are in

analog form.

Fig. 1.1 Analog Signal Processing

Digital signal processing provides an alternative method for processing the analog

signal. To perform the processing digitally, there is a need for interface between the

analog signal and the digital processor. This interface is called an analog-to-digital

(A/D) converter. The output of the A/D converter is a digital signal that is appropriated

as an input to the digital processor.

The digital signal processor may be a large programmable digital computer or a

small microprocessor to perform the desired operations on the input signal. It may also

be a hardwired digital processor configured to perform a specified set of operations on

the input signal. Programmable machines provides the flexibility to change the signal

processing operations through a change in the software, whereas, hardwired machines

are difficult to reconfigure. Consequently, programmable signal processors are in very

common use. On the other hand, when signal processing operations are well defined, a

hardwired implementation of the operations can be optimized, resulting in a cheaper

signal processor and, usually, one that runs faster than its programmable counterpart. In

applications where the digital output from the digital signal processor is to be given to

the user in analog form, such as in speech communications, we must provide another

interface from the digital domain to the analog domain. Such an interface is called a

digital-to-analog (D/A) converter. Thus the signal is provided to the user in analog form ,

as illustrated in the block diagram of Fig 1.2. However, there are other practical

applications involving signal analysis, where the desired information is conveyed in

digital form and no D/A converter is required. For example, in the digital processing of

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Analog signal

Processor

Analog Inputsignal

Analog 0utput signal

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radar signals, the information extracted from the radar signal, such as the position of the

aircraft and its speed, may simply be printed on paper. There is no need for a D/A

converter in this case.

Fig .1.2 Block Diagram of a Digital Signal Processing

1.5 ADVANTAGES & DISADVANTAGES OF DSP

There are many reasons why an analog signal is often preferred to process

digitally rather to process the signal directly in the analog domain, as mentioned briefly

earlier. First, a digital programmable system allow flexibility in reconfiguring the digital

signal processing operation simply by changing the program. Reconfiguration of an

analog system usually implies a redesign of hardware, testing, and verification that it

operates properly.

Accuracy consideration also play an important role in determining the form of the

signal processor. Digital signal processing provides better control of accuracy

requirements. Tolerance in analog circuit components make it extremely difficult for the

system designer to control the accuracy of analog signal processing system. On the other

hand, a digital system provides much better control of accuracy requirements. Such

requirements, in turns, result in specifying the accuracy requirements in the A/D

converter and the digital signal processor, in terms of word length, floating point versus

fixed point arithmetic, and similar factors.

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A/DConverter

Digital signalprocessor

D/AConverter

AnalogInputsignal Digital

input signal

DigitalOutputsignal

Analog outputsignal

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Digital signals can be easily stored on magnetic media (tape or disks) without

deterioration or loss of signal fidelity. As a consequence, the signals become

transportable and can be processed off-line in a remote laboratory. The digital signal

processing method also allows for the implementation of more sophisticated signal

processing algorithms. It is usually very difficult to perform precise mathematical

operations on signals in analog form. However, these operations can be routinely

implemented on a digital computer by means of software.

In some cases a digital implementation of the signal processing system is cheaper

than its analog counterpart. The lower cost may be due to the fact that the digital

hardware is cheaper, or perhaps it is a result of the flexibility for modification provided

by the digital implementation.

As a consequence of the advantages cited above, digital signal processing has

been applied in practical systems covering a broad range of disciplines. For example,

the application of digital signal processing techniques in speech processing and signal

transmission on telephone channels, image processing and transmission, in seismology

and geophysics, in oil exploration, in the detection of nuclear exploration, in the

processing of signal received from outer space, and in a vast variety of other applications.

As already indicated, however, one practical limitation of digital implementation

is the speed of operation of A/D converters and digital signal processors. Signals having

extremely wide bandwidth require fast-sampling-rate A/D converters and fast digital

signal processors. Hence there are analog signals with large bandwidths for which a

digital processing approach is beyond the state-of-the-art of digital hardware.

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1.6 DSP TMS 320C5X

DSP TMS 320 C5X generation consists of the ’C50, the ’C51, and the C53

devices. These digital signal processors (DSPs) are fabricated in accordance with static

CMOS integrated- circuit technology. Their architectural design is based on an advanced

Harvard architecture ( separate buses for program memory and data memory), additional

on chip peripherals, more on chip memory, and highly specialized instruction set is the

basis of the operational flexibility and speed of these DSP devices. The TMS320C5X

devices are designed to execute more than 28 MIPS ( million instructions per second).

The TMS 320 family of DSP chips are world famous chips. These are

manufactured by Texas Instruments. We feel that a suitable basic introduction to the

main feature of the DSP chips and to associated implementation considerations can be

achieved via a concise study of Texas instruments’ TMS 320 C5X DSP chip, which has

been used to producing their relatively inexpensive TMS320 C5X DSP Starter Kit (a PC

peripheral-cad containing a TMS 320C 5X and a TLC 32040 analogue interface circuit).

The TMS 320 family consists of 16 bits fixed point and 32 bit floating point

single chip digital signal processing device. The processor possess the operational

flexibility of high-speed controllers and the numerical capability of array processors.

Combining those two qualities, the TMS320 processors are inexpensive alternatives to

custom-fabricated VLSI and multi-chip bit-slice processors. The following qualities

make this family the ideal choice for a wide range of processing applications:

(a) Very flexible instruction set

(b) Inherent operational flexibility

(c) High-speed performance

(d) Innovative, parallel architectural design

(e) Cost effectiveness

The details about the DSP TMS 320C5X is given in chapter 2.

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1.7 OBJECTIVE OF THE WORK

The purpose of the radar is detection and identification of the distant targets. If

there is a moving target, we can estimate the parameters of the target like velocity and

distance. Sophisticated signal processing methods are required to estimate the target

parameters; much of the processing work can be done by the DSP processor. The

objective of the present work is to improve the target detecting facilities using visual

system in Radar BFSR MK-II as previously there was no visual system incorporated in

this radar. This work is done using TMS320C50 chips. The process of detection of the

target is automated for the radar. Different types of targets are studied and the results are

encouraging.

1.8 ORGANIZATION OF THE WORK

Chapter 1 gives a brief idea on the Digital Signal Processors, their advantages and

disadvantages and TMS320C5x. Digital Signal Processing is the central idea on which

the project is based.

Chapter 2 deals mainly with the TMS320C5x digital signal processor and its family. It

gives the information on the various fields in which they can be used. It deals with an in-

depth analysis of the processor like its memory organization, its basic architecture, basic

features of the processor blocks and various addressing modes.

Chapter 3 deals with the basic blocks (components) of the project that are used and

explains them briefly.

Chapter 4 deals with the analysis of FFT and an understanding of the FFT algorithm. The

set of algorithms known as the fast Fourier transform (FFT) consists of a variety of tricks

for reducing the computation time required to compute a Discrete Fourier Transform

(DFT). Since the DFT is the central computation in most spectrum analysis problems, it

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follows that the FFT implementation of the DFT, which, in some practical cases can

improve performance by a factor of 100 or more over direct evaluation of the DFT, is

crucially important and must be understood as part of any serious effort to utilize the

digital signal processing techniques of spectral analysis.

Chapter 5, this chapter covers the radar signal detection using FFT approach. The Radar

which works on Doppler principle gives the Doppler shift which is related with the

movement of the target. By using the FFT algorithm, the shift in frequency or the doppler

shift is detected and displayed on the monitor of the PC using FFT and Graphic interface

on TMS32050 kit. The BFSR is a non-coherent pulse Doppler radar working on Doppler

principle. It is a portable, primarily meant for use by Infantry during conditions of poor

visibility such as pitch dark night, fog, mist, smoke, dust etc. The detection of this radar

system is 1500 m max for group of moving personnel and 3000m max for moving

vehicles. The BFSR extracts the moving target information and present this in the form of

audio tone at a head set assembly, the range of the target being displayed on a LED

display by a range read out system.

The nature of the audio tone depends on the type of target and its speed of motion.

Thus an operator has to be trained to identify the difference in the audio tone heard and

decide on the type of the target picked up. This in most cases is guesswork depending

on the operators training and his experience. At present there is no means available with

the operator to corroborate his educated guess. This drawbacks in this system are :-

(a) An any infantry soldier may not have enough training and experience to

distinguish the type of target.

(b) Ambiguity in the info received due to various battle noises embedded in

the doppler.

There is a requirement of developing certain means of aiding the operator in

correct identification of the target. So in this project work we developed visual display

of the target doppler frequency by using DSP TMS32050 kit. In this project first we takes

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the FFT of the real time signal and then it displays on the screen of the monitor. With

help of this project radar operator is able to identify the nature of the target easily, which

was difficult in previous case.

The set of algorithms known as the fast Fourier transform (FFT) consists of a

variety of tricks for reducing the computation time required to compute a Discrete

Fourier Transform (DFT). Since the DFT is the central computation in most spectrum

analysis problems, it follows that the FFT implementation of the DFT, which, in some

practical cases can improve performance by a factor of 100 or more over direct

evaluation of the DFT, is crucially important and must be understood as part of any

serious effort to utilize the digital signal processing techniques of spectral analysis.

Digital signal processing is concerned with the representation of signals by

sequences of numbers of symbols and the processing of these sequences. The major

subdivisions of the field of digital signal processing are digital filtering and spectrum

analysis. The field of spectrum analysis is broken into calculation of spectra via the

Discrete Fourier Transform (DFT) and via statistical techniques as in the case of random

signals, eg. Quantization noise in a digital system. The evolution of a new point of view

towards digital signal processing was accelerated by the disclosure in 1965 of an efficient

algorithm for computation of Fourier Transforms or FFT. The Fast Fourier Transform

(FFT) and the related area of fast convolution are almost exclusively used in practical

spectrum analysis techniques.

1.9 CONCLUSIONS

Digital Signal Processing techniques find applications in many field as

Biomedical, Radar, Speech, Communication, Acoustics, Seismic and Sonar. To

implement these technique, we can use general purpose computers or dedicated digital

hardware systems. Recently many DSP processors chips are developed. Many of the

signal processing algorithms can easily implemented using the DSP processors.

Therefore the development of a digital dedicated system becomes very simple and cost

effective.

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CHAPTER 2

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TMS320C5X DIGITAL SIGNAL PROCESSOR

There are number of well developed Digital Signal Processors used in field of

signal processing like TMS 320 family from Texas Instruments, ADSP 2100 family

DSP from Analog Devices etc. All the DSPs are well developed but we found after

studied and availability of Digital signal processor that TMS 320 family is better. The

key features of the TMS 320 C5X are discussed.

2.1 TMS320 FAMILY OVERVIEW

The TMS320 family consists of 16 bits fixed point and 32 bit floating point single

chip digital signal processing device. The processor possess the operational flexibility of

high-speed controllers and the numerical capability of array processors. Combining these

two qualities, the TMS320 processors are inexpensive alternatives to custom-fabricated

VLSI and multi-chip bit-slice processors. The following qualities make this family the

ideal choice for a wide range of processing applications:

In 1982, Texas Instruments introduced the first fixed-point Digital Signal

Processor in the TMS320 family, the TMS32010. Before the year had ended, the

Electronic Products magazine awarded the TMS32010 the title Product of the year.

The TMS32010 became the model for future TMS320 generations.

Today, the TMS320 family consists of five generations: ‘C1X, ‘C2X, ‘C3X,

‘C4X, ‘C5X,‘C6X, and ‘C8X. Fig –2.1 illustrates the performance gains that the

TMS320 family has made over time with successive generations. Note that the ‘C1X,

‘C2X, ‘C5X and ‘C54X generations are fixed point and the ‘C3X, ‘C4X generations are

floating points and ‘C8X generation is both floating and fixed point multiprocessors.

Source code is upward compatible from one fixed point generation to the next fixed point

generation and, likewise, from one floating generation to the next floating generation.

Compatibility preserves the software portion of investment, thereby providing a

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convenient and cost-efficient roadmap to a higher performance, more versatile DSP

system.

FAMILY OVERVIEW OF THE TMS320 DSPs

Fig .2.1 family overview of DSP

Each generation of TMS320 devices has an internal core CPU and a

variety of memory and peripheral configurations. New combinations of on-chip memory

and peripheral options can create spin-off devices. Which can satisfy a wide range of

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C5x

C54x

C6x

FUTURE

C3X

C4X

FUTURE

C8x

FUTURE

FIXEDPOINTDSPs

MULTIPRO-CESSOR DSPs

FLOATINGPOINT DSPs

C1X

C2X

c

C2xx

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needs in the electronic market. When memory and peripherals are integrated into one

processor, overall system cost is greatly reduced and board space is saved.

2.2 TYPICAL APPLICATIONS

With the unique versatility and real-time performance, a C5X generation

processor offers better, more adaptable approaches to traditional signal-processing

problems such as vocoding and filtering. Furthermore, the C5X supports complex

applications which requires several operations to be performed simultaneously. Listed

below are those applications for which a ‘C5X device is well suited.

TYPICAL APPLICATIONS FOR THE TMS320 FAMILY

Automotive Customer Control

Adaptive Ride Control Digital Radio/TV Disk Drive Control

Antiskid Brake Educational toys Engine Control

Cellular Telephone Music Synthesizer Laser Printer Control

Digital Radio Power Tools Motor Control

Engine Control Radar Detector Robotics Control

Navigation Solid State Answer Servo Control

Global positioning Machines

Vibration Analysis

Voice Commands

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General Purpose Graphical/Imaging Industrial

Adaptive Filtering 3-D Rotation Numeric Control

Convolution Animation/Digital Map Power Line Monitor

Correlation Pattern Recognition Robotics

Digital Filtering Image Enhancement Security Access

FFT Transmission

Waveform Generation Robot Vision

Windowing Workstation

Instrumentation Medical Military

Digital Filtering Diagnostic Eqpt Image Processing

Function Generation Fetal Monitoring Missile Guidance

Pattern Matching Hearing Aids Navigation

Phase-Locked Loops Patient Monitoring Radar Processing

Seismic Processing Prosthetics Radar Frequency

Spectrum Analysis Ultra Sound Eqpt Modem

Transient Analysis Secure Commn

Sonar Processing

Telecommunication Voice/Speech

1200-to 19200-bps DTMF Encoding/Decoding Speech Enhancement

Modems Echo Cancellation Speech Recognition

Adaptive Equalizer FAX Speech Synthesis

Cellular Telephone Speaker Phone Speaker Verification

Channel Multiplexing Spread Spectrum Speech Vocoding

Data Encryption Communication Text-to-Speech

Digital PBXs Video Conferencing

DSI (Digital Speech X.25 Packet Switching

Interpolation)

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2.3 KEY FEATURES

Key features of the ‘C5x DSPs are listed in below. Where a feature is exclusive

to a particular device, the devices name is enclosed within parentheses and noted after

that features.

50ns single-cycle fixed-point instruction execution time (28.6/20 mips)

Upward source-code compatible with all ‘C1x and ‘C2x devices

RAM –based memory operation (‘C50)

ROM-based memory operation (‘C51)

9Kx16-bit single-cycle on-chip program/data RAM (‘C50)

1Kx16-bit single-cycle on-chip program/data RAM (‘C51)

3Kx16-bit single-cycle on-chip program/data RAM (‘C53)

2Kx16-bit single-cycle on-chip boot ROM (‘C51)

8Kx16-bit single-cycle on-chip program ROM (‘C51)

16Kx16-bit single-cycle on-chip program ROM (‘C53)

1056x16-bit dual-access on-chip data RAM

224X16-BIT maximum addressable external memory space (64K program,

64K data, 64K I/O and 32K global)

32-bit arithmetic logic unit (ALU), 32 Bit accumulator (ACC), and 32 bit

accumulator buffer (ACCB)

16-bit parallel logic unit (PLU)

16x16-bit parallel multiplier with a 32-bit product capability

Single cycle multiply/accumulate instruction

Eight Auxiliary register with a dedicated arithmetic unit for indirect

addressing

11 context-switch registers (shadow registers) for storing strategic CPU-

controlled registers during an interrupt service routine

Eight level hardware stack

0 to 16 bit left and right data barrel shifter and a 64 bit incremental data shifter

To indirectly address circular buffers for circular addressing

Single-instruction repeat and block repeat operation for program mode

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Block memory move instruction for better program/data management

Full-duplex synchronous serial port direct communication between the C5x

and another serial device

Time division multiple-access (TDM) serial port

Interval timer with period, control, and counter registers for software stock,

start, and reset.

2.4 FUNCTIONAL OVERVIEW : DSP START KIT

This DIGITAL SIGNAL PROCESSOR KIT has been fabricated in accordance

with static CMOS integrated circuit technology. Its architecture design is based upon the

combination of advance hardware architecture ie. Separate buses for program & data

memories. It has three parallel buses, these are:

(a) Program R/W bus (PAB)

(b) Data Read Bus (DAB 1)

(c) Data Write Bus (DAB 2)

Each bus accesses different memory space for different aspects of device

operation. Its memory is organized into four individually selectable spaces, program,

local data, global data and I/O ports. These spaces compose an addresses range of 224K

words. Within any of these spaces RAM EEPROM or memory peripherals can reside

either on or off chip. It includes 9 K words program/data, single access RAM (SARAM)

and 1056 words of dual access data RAM (DARAM).

The single access RAM required a full machine cycle to perform a Read/Write,

the dual access RAM can be Read and Written to in the same cycle.

This section explains the key features and provides a functional overview of the

DSP starter kit.

(a) Industry standard TMS320C50 fixed point DSP

(b) 50 ns instruction cycle time.

(c) 32K byte PROM

(d) Voice quality analog data acquisition via the TMS320C40

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(e) Standard RCA connectors for analog i/p and o/p that provide direct

connection to microphone and speaker.

(f) XDS 510 emulator connector

(g) I/O expansion bus for external design

(h) Modular architectural design for fast development of spin-off devices

(i) Advanced IC processing technology for increased performance

(j) Enhanced instruction set for faster algorithms and for optimized high level

language operation

(k) New static design techniques for minimizing power consumption &

maximizing radiation hardness.

(l) The basic block diagram of the DSP kit is shown Fig – 2.2 . In this system

the PC communication are via the RS 232 port on the DSK board.

The start kit enables experimentation with and use of DSP for real time signal

processing. It gives the freedom to create software to run on the board, as in, or to

built new board and expand the system in any number of ways. The DSK

Assembler and the Debugger are software interfaces that help to develop, test and

refine DSK assembly language program.

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BASIC BLOCK DIAGRAM OF TMS320C5X DSK

ExpansionConnector

32K x 8PROMBootcode

XDS510 Port14 -Pin Header

TMS320C50Control Serial PortD0 - D15A0 - A15 TDM Port

JTAG Emulation Port

Analog InterfaceTLC32040

RCA jackAnalog Out

RCA jackAnalog In

Fig 2.2 basic block diagram of tms320c5x

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2.5

2.5 KEY FEATURE OF ASSEMBLER

(i) Quick: The DSK assembler differ from many other assemblers in that it does

not go through a link up phase up to create an O/P file, instead it uses special directivities

to assemble code at an absolute addresses during the assembly phase. As a result, one

can create small programs quickly and easily.

(ii) Easy to use: If one desires to create larger programs he can do so by simply

changing files together with the include directive.

2.6 KEY FEATURES OF DEBUGGER

(i) Easy to use Windows oriented interface: It separates code, data and commands into

manageable portions.

(ii) Powerful commands set: It does not force to learn large, intricate command set,

however, it supports a small but powerful command set.

(iii) Flexible command entry: There are two main way to enter command, at the

command line or by using the menu bar of which, one can choose the method that suits

the best.

2.7 MEMORY MAP OF ‘C50 DSK

The on-chip dual access RAM (DARAM) B2 is reserved as a buffer for the status

register. The single access (SARAM), is configured as program and data memory. The

kernel program is stored in this area from 0x840h-0x980h. If the kernal program is to

perform an overwrite, a reset signal is required to let the DSK reload the kernal program.

Since the kernal program is stored in the SARAM, this on-chip memory can not be

configured as data memory only (RAM = 0). The interrupt vectors are allocated,

starting from 0x800h. The IPTR in the PMST register should not be modified. The

memory mapping of ‘C50 DSK is shown in fig 2.3

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Fig 2.3 memory mapping of tms320c5x

2.8 ANALOG INTERFACE CIRCUIT TLC 32040

The TLC 32040AIC on the board provides a single channel I/P, O/P voice quality

analog interface with the following features:

(a) A single chip D/A and A/D conversion with 14 bit of dynamic RAM

(b) Variable D/A and A/D sampling rate and filtering. The AIC interfaces

directly to the TMS320C50 serial port. The master input clock to the AIC is

provided by a 10Mhz timer output from the TMS320C50

(c) The AIC is hard wired for 16 bit word mode operation. The reset pin of the AIC

is connected to the B/R pin of the TMS320C50. DSK analog capabilities are

22

BOOTLOADER (On –chip) ROM

Interrupt Vectors

Debugger Kernelprogram

User’s Program

Eternal Space

(B0)

0000H

0800H

0840H

0980H

2C00H

FE00H

FFFFH

Memory MapRegisters

Reserved By Kernel B2

Reserved

(B0)

B1

Reserved

Reserved By Debugger Kernel B2

User’s Space

External space

0060H

0080H

0100H

0300H

0500H

0800H

0980H

2C00H

FFFFH

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suited to many applications including audio data processing. We can directly

connected most speakers and microphone to the DSK analog i/p and o/p.

(d) The DSK provides 6 headers, including the XDS510 header, to design

own external hardware. The majority of the TMS320C50 signals and other IC

signals to the board are connected to these headers. The XDS510 header allows

the DSK to become portable XDS510 target system.

(e) The TMS320C50 DSK as its own window-oriented debugger that makes it easier

to develop and debug software code. The DSK communicate with the PC using the XS

and BIOS/pins through the RS 232 serial port.

With its unique versatility and real time performance, DSP processors offer better,

more adaptable approaches to traditional signal processing problems such as filtering.

Further more, they support complex applications that often requires several operation to

the perform simultaneously.

2.9 SERIAL I/O PORTS

The C5X devices carry two high-speed serial ports. These serial ports are

capable of operating at upto one-fourth the machine cycle rate (CLKOUT 1). One of

the two circuits Sa synchronous, full-duplex serial port. Its transmitter and receiver and

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BYT/ WORDCOUNTER

double buffered and individually controlled by maskable external interrupt signal. Data

is framed either as bytes or as words. The sequence circuit is a full-duplex serial port

that can be configured either or synchronous for time-division multiple-access (TDN)

operations. The TDM serial port is commonly used in multiprocessor application. The

bock diagram of serial port is shown in fig no 2.4.

The SPC controls serial port operation; the functions of SPC bit fields are

described in below given table. Transmit data is written to the DXR, while receiving

data is read from the DRR. A transmit is executed by writing data to the DXR, which

copies the data to the SXR when the XSR is empty (the last word has been serially

transmitted that is driven on the DX pin). The XSR manage the shifting of the data to

the DX pin, thus allow another write to DXR as soon as the DXR-to-XSR copy is

completed.

Upon completion of the DXR-to-XSR copy, a 0-1 transmit occurs on the

transmit ready XRDY bit in the SPC and generate a serial port transmit interrupt that

signals that DXR is ready for a new work. The processors is received data from the DR

is shifted into the RSR, which copy it to the data receive register(DRR) from which it

may read. Upon completion of the RSR-to-DRR copy, a 0-to-1 transmission occurs on

the received ready (RRDY) bit in the SPC and generates a serial port receive interrupt

(RINT). Thus the serial port is double-buffered because data can be transferred to or

from DXR or DRR while another transmit or receive is being performed. Note that the

transfer timing is synchronized by the frame sync pulse in burst mode

16 16

LOAD

16 16

24

DATA BUS

LOAD CONTROLLOGIC

DXR (16)DRR (16)

XSR (16)

BYTE/ W0RDCOUNTER

RSR (16)

LOADCONTROLLOGIC

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RINT ON XINT ON

RSR-DRR LOAD

Transfer DXR-XSR transfer

DR Clear Clear DX

Clock Clock

FSR FSX

CLKR CLKX

Fig2.4 serial port block diagram

2.10 INTERRUPTS

The C5X devices have four external maskable user interrupts (INT4 – INT1) the

external device can use to interrupts the processor; there is one external non-maskable

interrupts (NMI). Internal interrupts are generated by the serial port (RINT & XINT),

the timer (TIMT), the TDM PORT (TRNT & TXNT), and the software interrupts

instruction (TRP, NMI & INTR). Interrupts priority are set so the reset (RS) as the

highest priority and INT for as the lowest priority. The NMI has the second highest

priority.

2.11 INTERRUPTS, PRIORITY AND FUNCTIONS

Name Priority Function

RS 1(highest) External Reset Signal

NMI 2 Non-Maskable interrupt

INTI 3 External User Interrupt # 1

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INT2 4 External User Interrupt # 2

INT3 5 External User Interrupt # 3

TINT 6 Internal Timer Interrupt

RINT 7 Serial Port Receive Interrupt

XINT 8 Serial Port Transmit Interrupt

TRNT 9 TDM port Receive interrupt

TXNT 10 TDM port transmit interrupt

INT4 11 External User Interrupt # 4

__ N/A Reserved

TRAP N/A Trap Instruction Vector

__ N/A Reserved

__ N/A Software Interrupt

When an interrupt occurs, it is stored in the 16- bit interrupt flag register (IFR),

note that this happens regardless of whether that interrupt is currently enabled or

disabled. Each interrupt set a flag in IFR. The flag can be cleared in any of the

following three ways.

i) Device reset (RS active low)

ii) The program takes the interrupt trap, or

iii) The program writes a one to the appropriate bit in the IFR.

The IFR is located at address 6 in the data memory space and can be read

to identify active interrupts and written to clear interrupts. The IFR register is lead out

as follows:

15 9 8 7 6 5 4 3 2 1 0

2.12 MEMORY ADDRESSING MODES

The C5X instruction set provides six basic memory addressing modes:

Direct addressing mode

Indirect addressing mode

26

Reserved I NT4 TXNT TRNT XINT RINT TINT INT3 INT2 INT1

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Immediate addressing mode

Dedicated Register addressing mode

Memory-mapped Register addressing mode

Circular Addressing mode

2.13 DIRECT ADDRESSING MODE

In the direct memory addressing mode, the instruction contains the lower 7 bit

of the data memory address(dma). This field is concatenated with the 9 bit of the data

memory page pointer (DP) register to form the full 16-bit data memory address. Thus,

the DP register points to one of 512 possible 120-words data memory pages, and the 7-

bit address in the instruction point of the specific location within that data memory

page. The DP register is loaded by using the LDP (low data memory page pointer) or

the LST #0 (load status register STO) instruction.

Bits 15 through 8 contain the opcode. Bit 7=0 defines the addressing mode as

direct, and the bit 6 through 0 contain the data memory address (dma).

DIRECT ADDRESSING BLOCK DIAGRAM

7 LSBs From Instruction Register

16-Bit Data Address

Fig 2.5 Direct Addressing

INDIRECT ADDRESSING BLOCK DIAGRAM

Auxiliary Registers

27

Data Bus (16)

DP (9)

Data Bus (16)

ARB (3) ARP (3)

AR0 (16)AR1 (16)AR2 (16)AR3 (16)AR4 (16)AR5 (16)AR6 (16)AR7 (16)

ARAU (16)

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3

3

ARP=2

16

16 –Bit Data Address

Fig 2.6 Indirect Addressing

2.14 INDIRECT ADDRESSING MODE

Eight auxiliary registers (AR0-AR7) provides flexible and powerful indirect

addressing on the C5X. To select a specific auxiliary register, load the auxiliary

register pointer (ARP) with a value from 0 To 7 designating AR0 through AR7

respectively. In direct addressing, any location in the 64K data memory space can be

accessed via a 16-bit address contain in an auxiliary register. The LAR instruction loads

the address into the register.

Indirect addressing can be used with all instructions except those with

immediate operands or with no operands. Bit 15 through 8 contain the opcode, and bit

7=1 defines the addressing mode as indirect. Bit 6 through 0 contain the indirect

addressing control bits.

Bit 6 contain the increment/decrement value (IDV). The IDV bits determines

whether the INDX register will be used to increment or decrement the current auxiliary

register. If bit 6-0, an increment or decrement (if any) by one occurs to the current

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auxiliary register. If bit 6=1, the INDEX register is added to or subtracted from the

current auxiliary register as defined by bit 5 &4.

Bit 5 and 4 control the arithmetic operation to be performed with AR (ARP) and

the INDX register. When set, bit 5 indicates that an increment is to be performed. If bit

4 is set, a decrement is to be performed.

2.15 IMMEDIATE ADDRESSING MODE

In immediate addressing, the instruction word(s) contains the value of the

immediate operand. The ‘C5X has both single-word (8-bit, 9-bit, and 13-bit constant)

short immediate instructions and two-word (16-bit constant) long immediate

instructions. In short immediate instructions, the immediate operant is contained within

the instruction word itself. In long immediate instructions, the word following the

instruction word is used as the immediate operant.

The instruction word format for RPT with short immediate addressing is as follows:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0

For long immediate instructions, the constant is a 16-bit value in the word

following the opcode. The 16-bit value can be optionally used as an absolute constant or

as a 2s-complement value. The following is an example code and the instruction word

format for the RPT instruction with long immediate addressing:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

29

1 0 1 1 1 0 1 1 8-bit constant

1 0 1 1 1 1 1 0 1 1 0 0 0 1 0 0

16-bit constant

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2.16 DEDICATED REGISTER ADDRESSING

Nine instructions in the ‘C5X instruction set can use one of two special-purpose

memory-mapped registers in the core CPU. These two registers are the block move

address register (BMAR) and the dynamic bit manipulation register (DBMR). The APL,

OPL, CPL, and XPL Parallel logic unit (PLU) instructions use the contents of the

DBMR register when an immediate value is not specified as one of the operands. The

BLDD,BLDP, and BLPD instructions can use the BMAR register to point at the

source or destination space of a block move. The MADD and MADS also use the

BMAR register to address an operand in program memory for a multiply-accumulate

operation.

2.17 MEMORY-MAPPED REGISTER ADDRESSING

Memory-mapped register addressing is used for modifying the memory-mapped

registers without affecting the current data page pointer value. In addition, any scratch

pad RAM location or data page 0 can be modified by using this addressing mode The

figure given below illustrates how this is done by forcing the 9 MSBs of the data

memory address to zero, regardless of the current value of the DP when direct

addressing is used or of the current auxiliary register value when indirect addressing is

used. The use of these instructions does not affect the contents of the DP.

9

7 7 LSBs from

30

All bits 0s

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Instruction Register (IR)

Or Current Auxiliary

16 Register

16-Bits Memory-mapped Register Address

Fig 2.7 Memory- Mapped Register Addressing

This addressing mode allows greater flexibility for dealing with memory-mapped

registers. The overhead required to perform operations involving a memory-mapped

register is greatly reduced because the data page pointer (DP) does not need to be

modified before and after the operation.

2.18 CIRCULAR ADDRESSING

Many algorithms such as convolution, correlation, and FIR filters can make use

of circular buffers in memory. In these algorithms, a circular buffer is used to

implement a sliding window, which contains the most recent data to be processed. The

‘C5X supports two concurrent circular buffers operating via the auxiliary registers. The

following five memory-mapped registers control the circular buffer operation.

CBSR1 --Circular Buffer One Start Register

CBSR2 --Circular Buffer Two Start Register

CBER1 --Circular Buffer One End Register

CBER2 --Circular Buffer Two End Register

CBCR --Circular Buffer Control Register

The 8-bit circular buffer control register enables and disables the circular buffer

operation. In order to define circular buffers, the start and end addresses should first be

loaded into the corresponding buffer registers; next, a value between the start and end

registers for the circular buffer is loaded into an auxiliary register. The proper auxiliary

register value is loaded, and the corresponding circular buffer enable bit is set in the

control register. In circular addressing, the step is the quantity that is being added to or

subtracted from the specified auxiliary register. Circular buffers can be used in

increment- or decrement-type updates.

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2.19 STATUS AND CONTROL REGISTER ORGANIZATION

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STO

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ST1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CBCR

PMST

There are four key status and control registers for the ‘C5x core. STO and STI

contain the status of various conditions and modes compatible with the ‘C25 while PMST

and CBCR contain extra status and control information for control of the enhanced

features of the ‘C5x core. These registers can be stored into data memory and loaded

from data memory, thus allowing the status of the machine to be saved and restored for

subroutines.

The organization of the four status registers, indicating all status bits contained

each. The index register, compare register, are the eight LSBs of the instruction register

can be used as one of the inputs of the capital ARAU. The other input is fed by the

32

ARP OV OVM 1 INTM DP

ARB CNF TC SXM C 1 1 MH 1 XF 1 1 PM

RESERVED CENB2 CAR2 CENB1 CAR1

I A O R MP N T B P 0 0 0 V 0 V A D R R T I L M MC X M A R F

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current AR(being pointed to by ARP). AR (ARP) refers to the contents of the current AR

pointed to by ARP. The ARAU performs the function shown in table.

2.20 AUXILIARY REGISTER ARITHMETIC UNIT FUNCTIONS

Auxiliary Register Operation Description

AR(ARP) + INDX AR(ARP) Index the current AR by adding an

unsigned

16-bit integer contained in INDX.

Example:

ADD *0+

AR(ARP) – INDX AR(ARP) Index the current AR by subtracting an un-

Signed 16-bit integer contained in INDX.

Example: ADD*0-

AR(ARP) + 1 AR(ARP) Increment the current AR by one. Example

: ADD *+

AR(ARP) – 1 AR(ARP) Decrement the current AR by one.

Example

: ADD*-

AR(ARP) AR(ARP) Do not modify the current AR. Example:

ADD*

AR(ARP) + IR(7-0) AR(ARP) Add an 8-bit immediate value to current

AR. Example: ADDRK *55h

AR(ARP) – IR(7-0) AR(ARP) Subtract an 8-bit immediate value from

Current AR. Example: SBRK *55h

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AR(ARP) + rc(INDX) AR(ARP) Bit-reversed indexing ; add INDX with

Reverse-carry (rc) propagation.

Example: ADD *BRO+

AR(ARP) – rc (INDX) AR(ARP) Bit-reversed indexing ; subtract INDX with

reversed-carry (rc) propagation. Example:

ADD *BRO-

If(AR(ARP)) = (ARCR) then TC=1 Compare the current AR to ARCR and, if

If(AR(ARP)) < (ARCR) then TC = 1 condition is true, then set TC bit of the

If(AR(ARP)) > (ARCR) then TC = 1 status register ST1 to one. If false, then

If(AR(ARP)) = (ARCR) then TC = 1 clear the TC bit. Example: CMPR 3

If(AR(ARP)) = (CBER) then (AR(ARP)) If at end of circular buffer, reload start

= CBSR address. The test for this condition is done

prior to the execution of the

auxiliary

register modification. Example: ADD*+

2.21 HARDWARE/SOFWARE REQUIREMENTS

The software-hardware requirements are as given below:-

Host : An IBM PC/AT or 100% compatible PC with a hard disk system and a 1.2 M

byte floppy disk drive.

Memory : Minimum of 640K bytes

Display : Monochrome or colour (colour recommended)

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Power requirements : A 9 Vac @ mA (or greater) power supply with a 2.1 mm

power jack connector, which is common t most wall mounted AC transformers. A

low-current UL transformer is recommended, because it is designed to hold up under

brief power

Board : DSK circuit board

Port : An asynchronous RS-232 serial communication link

Cable : RS –232 with a DB-9 interface

Optional Hardware : An EGA or VGA-compatible graphics display card and a large

monitor. The debugger has two options that allows us to change the overall size of

the debugger display. To use a larger screen size, you must invoke the debugger with

the –1 option.

Miscellaneous materials : Blank, formatted disks

Operating System : MS-DOS OR PC-DOS (version 4.01 or later)

Files : dsk5a.exe is an executable file for the DSK assembler. DSD 5d.exe is an

executable file needed for running the DSK debugger interface.

2.22 CONNECTING THE DSK TO PC

Steps to connect DSK board to PC:-

Turn off PC’s power

Connect RS – 232 cable to either communication port 1 or 2 on PC

Connect RS 232 cable to a 25-to-9 pin adapter, if necessary.

Plug the RS-232 cable (or adapter) into the DSK board connect the 9 V AC

transformer into the DSK board plug the transformer into a wall socket

Turn PC’s power on

2.23 INSTALLATION OF THE DSK SOFTWARE

This section explains the process of installing the debugger software on a hard

disk system.

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(a) Make a back up copy of the product disk

(b) On hard disk or system disk create a directory named dsktools. The

directory will contain the DSK assembler and debugger software. To create

the directory, enter: and C:\dsktools

(c) Inset product disk into drive a:. Copy the content of the disk: Copy a:\*.*

c:\dsktools\*.*/v

(d) When using the debugger, we can have only 20 files open or active at one

time. To tell the system not to allow more than 20 active files, we must add

the following to config.sys file: Files = 20. Once we have edit config.sys

file and added the line, invoke the file by turning off the PC’s power and

turning it on again.

(e) Modifying the PATH statement

(i) To ensure that debugger work correctly, we must modify the PATH

statement to identify the dsktools directory. Not only must we do

this before we invoke the debugger for the first time, we must do it

any time we power up or reboot the PC.

(ii) We can accomplish this by entering individual DOS commands, but

it’s simpler to put the commands in system’s autoexec.bat files.

The general for doing this is :

PATH = C:\dsktools:pathname2:pathname…..

(iii) This allow us to invoke the debugger without specifying the name

of the directory that contains debugger executable file.

(iv) If we are modifying autoexec.bat file and it already contains a

PATH statement, simply include: C:\dsktools at the end of the

statement as shown below Path statement PATH = C:\dos\dsktools.

2.24 APPROACH FOR SOFTWARE APPLICATION

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The syndicate had three options available to it for carrying out the software

applications. The options are as given below:

(i) ‘C’ Language (using DSP compiler)

(ii) Assembly Language of DSP Kit

(iii) Combination of Assembly Language and ‘C’ Language

The syndicate selected the third option ie combination of both Assembly

Language and ‘C’ Language for carrying out the software applications.

2.25 TMS320C1X/C2X/C2XX/C5X

ASSEMBLY LANGUAGE DEVELOPMENT FLOW

The following list describes the tools.

Compiler:The C2X/C2XX/C5X optimizing ANSI C compiler is

a full-featured Optimizing compiler that translates standard NSI

C programs into C2XX Assembly language source, key

characteristics include:

Standard ANSI C. The ANSI standard is a precise definition of the C language , agreed

upon by the C community. The standard encompasses most of the recent extensions to C.

To an increasing degree, ANSI conformance is a requirement for C compilers in the DSP

community.

Optimization. The compiler uses several advanced techniques for generating efficient

compact code from C source.

Assembly language output. The compiler generates assembly language source that you

can inspect (and modify, if desired).

ANSI Standard runtime support. The compiler package comes with a complete run

time library that confirms to the ANSI library standard. The library includes functions

for string manipulation, dynamic memory allocation, data conversion, timekeeping,

37

C Compiler

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trigonometry, exponential operations, and hyperbolic operations. Functions for I/O and

signal handling are not include, because they are application specific.

Flexible assembly language interface. The compiler has straightforward calling

conventions, allowing you to easy write assy and C functions that call each other.

Shell program. The compiler package include a shell program that enables you to

compile, assemble, and link program in a single step.

Source interlist utility. The compiler package include a utility that interlist your original

C source statement into the assembly language output of the compiler. This utility

provides you with an easy method for inspecting the assembly code generated for each C

statement.

The assembler translates C2XX assembly language source files

into machine language object files.

The linker combines object file into a

signal, executable object module. As the linker creates the

executable module, it performs re-location and resolves external

reference. The linker is a tool that allows you to define your

systems memory map and to associate blocks of code with

defined memory areas.

The main purpose of the development process is to produce a

module that can be executed in a C2XX target system. You

can use one of several debugging tools to refine and correct

your code. Available products include:

A scan-based emulator

A software simulator

Each of these tools use the C2XX debugger as a

software interface Hex conversion utility is also available; it

converts a COFF object File into an ASCII-Hex, Intel, Motorola-

S, Tektronix, or TI-tagged object-format file that can be

downloaded to an EPROM program.

38

Assembler

Linker

Debugging Tools

Hex Conversion Utility

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2.26 CONCLUSION

Digital Signal Processing (DSP) is concerned with representation of the signals

by sequences of numbers and with the transformation or processing of such a signal

representations of by numeric-computational procedures. In the past, digitals filters were

implemented in software using mini- or main–frame computers for non real- time

operation or on specialized dedicated digital hardware for real time processing of signals.

The recent advances in VLSI technology have resulted in the integration of these

digital signal processing systems into small integrated circuits (ICs), such as TMS320

Family of digital signal processors from Texas Instruments. The TMS320

implementation of digital filters allows the filter to operate in real time signals. This

method combines the ease of flexibility of the software implementation of filters with

reliable digital hardware.

Because of their computational power, high I/O throughput, and real time

programming, the TMS320 processors have been widely adapted in telecommunications,

data communication , and computer applications. The TMS320 has efficient DSP-

oriented instructions and complete hardware/software development tools, thus making the

TMS320 highly suitable for DSP applications.

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CHAPTER 3

3.1 Basic Components used in the Project:

The basic blocks of our project are:

1. Function Generator

2. Amplifier and voltage limiter

3. Digital Signal Processor Starter Kit (DSK)

4. Personal Computer with WIN’98 OS.

Function Generator: A device used to generate required signals such as sine,

square..etc. In this project with the help function generator we will generate required sine

wave and we will treat it as echo signal from the moving target.

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Amplifier and voltage limiter: To amplify the signal reflected from the moving target ,

we use a amplifier. The inverting Amplifier with IC741 having a gain of 10 is used. The

output of the amplifier is a signal of amplitude few Volts (less than 5V). voltage limiter

limits the voltage to 5V beyond which which the kit may spoiled.

Fig 3.1 amplifier

Digital Signal Processor Starter Kit (DSK): The DSK basically consists of a Processor,

an Expansion Connector, 32K x 8 PROM, an Analog Interface Circuit (AIC). The AIC is

used to convert Analog signal into a Digital signal. This signal is processed by the

processor and converted back to Analog. The Expansion Connector is used to interface

other DSK’s with this kit.

Graphic User Interface (GUI): A method for interfacing with the computer that allows

any image to be displayed on screen (Graphics based). The major GUI’s are The

Windows and MAC Interface.

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Fig 3.2 Basic Blocks of the Project

42

Function generator (Receiver)

Amplifier and limiter

AIC (H/W)

DSP TMS 320 C5x(H/W)

GUI(S/W)

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CHAPTER 4

4.1 INTRODUCTION TO FFT

The radar signal detection on TMS320C5X is a good approach in radar signal

detection field. Here we are detecting signal of BFSR( Battle Field Surveillance Radar),

in this radar only audio system is their but on video system is given.

The Battle- Field Surveillance Radar (BFSR) is a non- coherent pulse Radar and

works on Doppler principle. In a non-coherent Radar, moving target detection is possible

only when the target movement takes place in the presence of stationary targets as a

background.

The ability with which a non-coherent radar can detect moving target in the

presence of clutter depends upon the ratio, which should be at least 1/10 , of the moving

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target vector amplitude to the resultant fixed echo vector amplitude. Target detection will

be difficult under two extreme conditions. When the fixed target signal or clutter is very

large compared to the moving target and when the clutter signal strength is very small.

Moving target includes not only those moving from place to place, such as man

walking or running, but also those that stay in one place and make a to and fro motion

such as man standing in one place and waving his arms. Fixed targets include building,

stationary vehicles, hill features or anything that reflects RF energy but does not move

above. Trees and tall grass, for example, can be considered to be fixed target when there

is no wind, but become moving targets under breezy condition. The detection of radar

signal is first takes the FFT of the signal and then this signal displays on the screen of the

monitor of the PC with graphic interface. Here first we will discussed about FFT on DSP

TMS32050 and after radar theory and then detection of the signal.

The Fourier transform converts information from the time domain into the

frequency domain. It is an important analytical tool in such diverse fields as acoustic,

optics, seismology, telecommunications, speech, signal processing, and image

processing. In discrete-time systems, the Discrete Fourier Transform (DFT) is a

counterpart of the continuous-time Fourier Transform. Since the DFT is computation-

intensive, it had relatively few applications, even with modern computers. Fast Fourier

Transform (FFT) is the generic name for a class of computationally efficient algorithms

that implement the DFT and are widely used in the field of Digital Signal Processing.

Recent advances in VLSI hardware, such as the Texas Instruments TMS 320

family processor, have further enhanced the popularity of the FFT. The application report

describes the implementation of FFT algorithms using the TMS 320 processor, which has

features particularly suited to Digital Signal Processing.

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4.2 DERIVATION OF THE FFT ALGORITHM

Amore efficient methods of computing the DFT the significantly reduces the

number of required arithmetic operations is the called decimation in time (DIT) FFT

algorithm. With the FFT , N is a factorable number that allows the overall N-point DFT

to be decomposed into successively smaller and smaller transforms. The size of the

smallest transform thus derived is known as the radix of the FFT algorithm. Thus , for a

radix –2 FFT algorithm , the smallest transform or “butterfly” (basic computational

unit )used is the 2-point DFT. Generally, for an N-point FFT, there are N resultant

frequency samples corresponding to N time samples of the input signal x(n). For a radix-

2 FFT, N is a power of 2.

The number of arithmetic operations can be reduced initially by decomposing the

N-point DFT into two N/2 -point DFTs. This means that the input time sequences (hence

the name, decimation-in-time), which consist of its even numbered and odd numbered

samples with time indices expressed mathmatically 2n and 2n+1, respectively.

Substituting these time indices into the original DFT equation gives

………… (4.1)

…..(4.2)

= k= 0,1,2……N-1

where y(k) is the first summation and z(k) is the second summation term.

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Y(k)and z(k) are further seen be the N/2–point DFTs of the even-numbered and odd

numbered time samples, respectively. In this case, the number of complex multiplications

and additions is approximately N+2(N/2)2 because, according to (6.2) , the N-point DFT is

spilt in two N/2-point DFTs, which are then combined by N complex multiplications and

additions. Thus, by splitting the original N-point DFT into two N/2 -point DFTs, the totals

number of arithmetic operations has been reduced This reduction is illustrated in figure

(4.1).

Implicit in the above derivation is the periodicity of x(k), y(k),and z(k). x(k) is

periodic in k with a period N, while y(k)and z(k) are both periodic in k with period N/2.

Consequently, despite the fact that the index k ranges over N values from 0 to N-1 for

x(k), both y(k) and z(k) must be computed for k between 0 to (N/2)-1 only. The

periodicity of y(k)and z(k) is also assumed in figure 2.

Although (4.2) can be used to evaluate X(k) for 0 k N-1, further reduction

in the amount of computation is possible when symmetry property and periodicity of the

twiddle factor are utilized to compute X(k) separately over the following ranges:

1st Half of frequency spectrum: 0 k ( N/2)-1

2nd Half of frequency spectrum : N/2 k N-1

Equation (4.2), for N/2 k N-1, can be written as

…….(4.3)

Therefore, (4.2) can be used to compute the first half of the frequency spectrum

X(k) for the index range 0 k (N/2)-1, while equation (4.3) can be used to compute

the second half of the frequency spectrum X(k+N/2).

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x(2n) x(0) y(0) X(0)

x(2) y(1) X(1) x(4) y(2) X(2) . . . . . . x(N-2) y[(N/2)-1] X[(N/2-1]

x(2n+1) x(1) z(0) X(N/2) x(3) z(1) X[(N/2)+1] x (5) z(2) X[(N/2)+2] . . . . . x(N-1) z[(N/2)-1] X(N-1)

Figure 4.1. Decomposition of a DFT using the symmetry property

Figure (4.1) depicts the situation when the symmetry property of the twiddle

factor is used to compute X(k). The above decimation process and symmetry exploitation

can reduce the DFT computation tremendously. By further decimating the odd numbered

and even numbered time samples in a similar fashion, four N/4 –point DFTs can be

obtained, resulting in further reduction in the DFT computation. Consequently, to arrive

at the final radix-2 DIT FFT algorithm, the decimation process is repetitively carried out

until eventually the N-point DFT can be evaluated as a collection of 2-point DFTs or

butterflies.

4.3 RADIX-2 DECIMATION- IN- TIME (DIT) FFT BUTTERFLY

47

n = 0

N/2 -1

n = 0

N/2 -1

N/2-point DFT z(k)

N/2 –point DFT Y(k)

Page 48: Radar Signal Detection Using TMS320C50

In the radix-2 DIT FFT algorithm, the time decimation process passes through a

total of M stages where N =2 M with N/2 2-point FFTs or butterflies per stage, giving a

total of (N/2)log2N butterflies per N-point FFT.

For the case of an 8-point DFT implemented using the radix-2 DIT FFT algorithm

discussed in the previously, the input samples are processed through three stages. Four

butterflies are required per stage, giving a total of twelve butterflies in a radix-2

implementation. Each butterfly is a 2-point DFT of the form depicted in figure (4).P and

Q are the input to the radix-2 DIT FFT butterfly. In general, the inputs to each butterfly

are complex as is also the twiddle factor.

P P

Q -1 Q

Figure 4.2. A radix-2 DIT FFT Butterfly Flowgraph Figure (4.3)

As shown in figure 4.2, the outputs P’ and Q’ of the radix-2 butterfly are given by

P’ =

… (4.4)

Q’ =

4.4 IMPLEMENTATION OF THE FFT BUTTERFLY WITH SCALING

In the computation of FFT, scaling of the intermediate results become necessary

to prevent overflows. The TMS 320 C5X processor has features optimized for digital

signal processing and a number of on-chip shifters for scaling. In particular , the input

48

+

+

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scaling shifter, the 32 bit double-precision ALU and accumulator, and its output shifter

are used extensively for scaling.

To see how overflows can actually occur in FFT computations, consider the

general radix-2 butterfly in the mth stage of an N-point DIT FFT as shown in figure 4.4.

Pm Pm +1

Qm -1 Qm +1

Figure 4.4 signal flowgraph of a Butterfly at mth stage

From fig 4.4, the final form the FFT can be written as

Pm+1 = Pm + Qm

… (4.5)

Qm + 1 = Pm – Qm

Where Pm and Qm are the inputs and Pm + 1 and Qm + 1 are the output of the mth stage

of the N-point FFT, respectively. In general, Pm , Qm, Pm +1, and Qm + 1 are complex

as the twiddle factor. The twiddle factor can be expressed as

= e – j(2 / N)k = cos (X) – j sin (X) ….. (4.6)

where X = ( 2/N)k and j = -1.

The input Pm and Qm can be expressed in term of their real and imaginary parts by

Pm = PR + j PI

49

+

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Qm = QR + jQI …(4.7)

By substituting the values from equation (4.6) and (4.7), Equation (4.5) becomes

Pm + 1 = PR + jPI + ( QR cos(X) + QI sin(X) + j (QI cos(X) – QR sin(X))

= ( PR + QR cos(X) + QI sin(X) ) + j( PI + QI cos(X) – QR sin(X))

Qm + 1 = PR + jPI - ( QR cos(X) + QI sin(X) - j (QI cos(X) – QR sin(X))

= ( PR - QR cos(X) - QI sin(X) ) + j( PI - QI cos(X) + QR sin(X))

Although the inputs of each butterfly stage have real and imaginary parts with

magnitudes less than one, the real and imaginary parts of the outputs from (4.7) can have

a maximum magnitude of

1 + 1 sin(45) + 1 cos (45) = 2.414213562

To avoid the possibility of overflow, each stage of the FFT is scaled down by a factor of

2.In this way ,if an FFT consists of M stages, the output is scaled down by 2 M= N, where

N is the length of the FFT. Even with scaling, overflow is possible because of the

maximum magnitude value for complex input data. This possibility is avoided by scaling

down the input signal by a factor of 1.207106781, and then scaling up the output of the

last FFT stage by the same factor.

The TMS320 C5X reduces the execution time of all FFTs by virtue of its 50 nano

second (ns) instruction cycle time. Also, the bit reversed addressing mode helps reduce

execution time for radix-2FFTs. As demonstrated in figure (4.5) and in figure (4.6), the

inputs or outputs of an FFT are not in sequential order. This scrambling of data locations

is a direct result of the radix-2 FFT derivation. Observation of the figures and the

relationship of the input and output addressing reveal that the address indexing is in bit

reversed order. As a result, either the input data sequence or the output data sequence

must be scrambled in association with the execution of the FFT. Here the input data is

scrambled before the execution of the FFT algorithm so that the output is in order.

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The bit reversed addressing mode is a part of the indirect addressing implemented

with the auxiliary registers and the associated arithmetic unit. In this mode, a value

(index) contained in INDEX is either added to or subtracted from the auxiliary register

being pointed to by the ARP. However, the carry bit is not propagated in the forward

direction; instead, it is propagated in the reversed direction. The result is a scrambling in

the address access.

The procedure for generating the bit- reversed address sequence is to load INDX

with a value corresponding to one-half the length of the FFT and to load another

auxiliary register- for example AR1 – with the base address of the data array. However,

implementations of the FFTs involve complex arithmetic; as a result, two data memory

locations (one real and one imaginary) are associated with each data sample. For ease of

addressing, the samples are stored in workspace memory in pairs with the real part in the

even address locations and the imaginary part in the odd locations. This means that the

offset from the base address for a given sample is twice the sample index. If the incoming

data is in the following form:

XR(0), XR(1), ……..XR(7), XI(0), XI(1), ………..XI(7)

Where

XR - Real component of the input sample

XI – Imaginary component of the input sample

Then it is easily transferred into the data memory and stored in scrambled order:

XR(0) ,XI(0), XR(4), XI(4), XR(2), XI(2), ……XR(7), XI(7)

By loading INDX register with the size of the FFT and by using bit reversed addressing

to save each input word.

The following list shows the contents of the auxiliary register AR1 when INDX is

initialized with value of 8 and when the data is being transferred by the code that follows.

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MSB LSB

INDEX 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 FOR 8-POINT FFT

AR1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 BASE ADDRESS

RPT 15

BLDD # INPUT, *BR0+

AR1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 XR(0)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 XR(4)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 XR(2)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 XR(6)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 XR(1)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 XR(5)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 XR(3)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 XR(7)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 XI(0)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 XI(4)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 XI(2)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 XI(6)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 XI(1)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 XI(5)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 XI(3)

AR1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 XI(7)

This is shown in the FFT subroutine for 16 input samples.

4.5 IN-PLACE FFT COMPUTATIONS

In the butterfly implementation, the set of input registers in the data memory (PR,

PI, QR, and QI) for the two complex inputs Pm and Qm are used for holding the two

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complex inputs Pm+1 and Qm+1, respectively. When the same set of inputs registers is

used as output registers for holding the FFT results, the FFT computation is said to be

performed In-Place. Therefore, FFTs implemented on TMS 320C5X using the general

butterfly routine are performed In-Place.

As general rule, an in-place FFT computation means that a total of 2N memory

locations are required for an N-point FFT since the inputs to the FFT can be complex. On

the other hand, a total of up to 4N memory locations is required for not-in-place

computations.

Another attractive feature of the butterfly routine is that temporary or scratch-pad

registers are not needed for the intermediate results or calculations. Where coefficient

quantization and other finite word length effects are not critical, 13 bit sine and cosine

values can be used instead of 16-bit values addressed by the MPY instruction. In this

way, the registers COSX and the SINX for the twiddle factors can be dispensed with

altogether.

4.6 BIT – REVERSAL /DATA SCRAMBLING

As shown in figure (4.5), the input time samples x(n) are not in order, i.e. they are

scrambled. Such a data scrambling or bit reversal is a direct result of the radix-2 FFT

derivation. On closer inspection, it is seen that index of the each input sample is actually

bit-reversed.

Therefore, the input data sequence must be prescrambled prior to executing the

FFT in order to produce in-order outputs. To perform bit reversal on the 8-point FFT,

shown in figure(4.5), the pairs of the inputs samples, [ x(1) and x(4)] and x(3) and x(6)] ,

must be swapped. On the other hand, fig. (4.6) has in-order input samples by arranging

the ordering of all the butterflies. However, the outputs are now bit-reversed.

In general. Bit reversed or data scrambling must be performed either at input

stage on the time samples [fig (4.5)] or at the output stage on the frequency samples[ fig.

(4.6)]. Bit reversal can be performed in-place. Such a process generally requires the use

of one temporary data memory location.

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Because of its double-precision accumulator and its versatile instruction set, the

TMS 32050 processor can perform in-place bit reversal or data scrambling without the

use of a temporary data memory location.

Although bit reversal can be regarded as a separate task performed either at the

input or output stage of the FFT implementation, some FFT algorithms exist with bit

reversal as an integral part. Such a algorithms are said to be in-place and in-order, and

they tend to have higher execution speeds than that of the FFT and bit reversal

algorithms executed separately.

FIG 4.5 An IN-Place DIT FFT with In-Order outputs and Bit-reversed Inputs.

Stage 1 stage 2 stage 3

FIG. 4.6 An IN-Place DIT FFT with IN-Order Inputs but Bit- Reversed Outputs

54

W0

W2

W2

W0

W0

W1

W2

W3

X(0)

X(4)

X(2)

x(6)

x(1)

x(5)

x(3)

x(7)

W0

W0

W0

W0

x(0)

x(1)

x(2)

x(3)

x(4)

x(5)

x(6)

x(7)

W0

W0

W0

W0

W0 0

W0

W2

W2

W0

W2

W1

W3

X(0)

X(4)

X(2)

x(6)

x(1)

x(5)

x(3)

x(7)

x(0)

x(1)

x(2)

x(3)

x(4)

x(5)

x(6)

x(7)

Stage 1 stage 2 stage 3

Page 55: Radar Signal Detection Using TMS320C50

6.7

4.7 FLOWCHART FOR FFT ALGORITHM

55

Take the sampled Input Data

Count=15;ARO=Base Add;INDX=Length of FFT;

START

Page 56: Radar Signal Detection Using TMS320C50

YES

NO

Fig 4.7 Flowchart For FFT Algorithm

56

Start Bit Reversal

Count<=15

Start Butterfly Process

STOP

Page 57: Radar Signal Detection Using TMS320C50

CHAPTER 5

5. 1 INTRODUCTION TO RADAR SIGNAL DETECTION

The Battle- Field Surveillance Radar (BFSR) is a non- coherent pulsed Doppler

Radar and works on Doppler principle. In a non-coherent Radar, moving target

detection is possible only when the target movement takes place in the presence of

stationary targets as a background.

The ability with which a non-coherent radar can detect moving target in the

presence of clutter depends upon the ratio, which should be at least 1/10 , of the moving

target vector amplitude to the resultant fixed echo vector amplitude. Target detection will

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be difficult under two extreme conditions. When the fixed target signal or clutter is very

large compared to the moving target and when the clutter signal is strength is very small.

Moving target includes not only those moving from place to place, such as man

walking or running, but also those that stay in one place and make a to and fro motion

such as man standing in one place and waving his arms. Fixed targets include building,

stationary vehicles, hill features or anything that reflects RF energy but does not move

above. Trees and tall grass, for example, can be consider to be fixed target when there is

no wind, but become moving targets under breezy condition.

Fig 5.1 Explain how a moving target superimposes a modulation on the resultant

fixed vector amplitude to produce doppler frequency. Consider five fixed targets T1

through T5 within the range resolution cell of 100 meters of the radar. The echo signal

from each of these five targets can be represented by FT1 through FT5. Since all of them

are fixed echoes, FTR will represent the resultant vector of the `echoes’. If there is a

sixth target (MT) anywhere with in the same range cell of 100 meters, and if the target

moves, the phase of return echoes with reference to FTR will vary over 360 degrees,

each time the moving target traverses a distance equal to /2 where is the wave length.

As the wave length of the BFSR is 3 cm , a phase change of 180 degrees corresponding

to a target movement of 0.75cm will result in the amplitude of the resultant signal to vary

from a maximum to a minimum value .Thus if one target moves continuously with

reference to any one or several other fixed targets, the resultant signal will vary in

amplitude in a sinusoidal manner. The frequency or rate of this variation in amplitude

from one received pulse to another, will depend upon the speed of the target, or upon the

number of half wave length traveled by the target, per second, Hence, fast moving

targets will produce a higher modulation rate or higher doppler frequency and slow

moving target will produce a lower doppler frequency.

In the case of BFSR ,at the wavelength of operation of 3 cm, the doppler

frequencies will be in the range of 40 to 1200 Hz for target speeds varying from about 2

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km/h to 64 km/h. Since this frequency range lies in the lower audio band, echoes from

moving targets like men and vehicles can be heard in headsets.

Clutter back ground is therefore, necessary for operation of the radar. It will not,

for example be possible to detect the movement of a Jet propelled Aircraft with the

BFSR Radar as there is no static or fixed background against which the movement could

be detected . It is, however, possible to detect movement of the helicopters in the sky. In

this case, body of the helicopter provides the static background against which the rotation

of the propeller blades could be detected.

Static or fixed targets will not produce any doppler signal at the head

sets/monitor, since the RF return echo from static targets will be of constant amplitude

for all transmitted pulses.

FT4 FT5

FT3 FTR

FT2 FT1

Fig 5.1 Fixed Target Resultant

FTR is the fixed target resultant vector. Echo signal(video amplitude ) From this

resultant will be constant for all received echo pulses. This figure have no Doppler

information.

If a moving target (MT) is also present, the fixed target resultant vector will be

modulated by moving target. Echo signal will now be changing in amplitude from one

received pulse to an other. The rate of change of amplitude is proportional to the speed of

the moving target as shown in fig (5.2).

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Fig 5.2 : Moving Target Resultant (Doppler production)

5.2 DOPPLER PRINCIPLE

It is well known in the field of optics and acoustics that if either the source of

oscillation or the observer of the oscillation is in motion, an apparent shift in the

frequency will result. This is the Doppler effect. If R is the distance from the radar to

target, the total number of wavelength contained in the two way path between the radar

and the target is 2R/. The distance R and the wavelength are assumed to be measured

in the same units. Since one wavelength corresponds to an angular excursion of 2

radians, the total angular excursion made by the electromagnetic wave during its transit

to and from the target is 4R/ radians. If the target is in motion ,R and are continually

changing. A change in with respect to time is equal to a frequency. This is the doppler

angular frequency d , given by

…(6.7)

where fd = doppler frequency shift and vr = relative (or radial) velocity of the target with

respect to radar. The doppler frequency shift is

60

MT

FTR

Page 61: Radar Signal Detection Using TMS320C50

(6.8)

where f0 = transmitted frequency and c= velocity of propagation = 3x108 m/s. If fd is in

hertz, vr in knots, and in meters,

f d =1.03 vr/

…(6.9)

The relative velocity may be written vr = cos , where v is the target speed and is the

angle made by the target trajectory and the line joining radar and target. When = 0 the

doppler frequency is maximum. The doppler frequency is zero when the trajectory is

perpendicular to radar line of sight ( = 900).

5.3 FUNCTIONAL BLOCK DIAGRAM

The functional block diagram of radar BFSR MK II is shown in fig 5.4. The important

subsystems are as listed below

1) Power converter unit

2) Transmitter

3) I F Amplifier

4) Signal processing unit

The power converter unit receive 24 volts from battery and provides voltages

required for the operation of the various sub systems.

The modulator unit produces a transmitter pulse of 0.66 microsecond duration at

an amplitude level of 2.9 KV by employing a line type of modulator. This high voltage

pulse is applied to the cathode of a magnetron, which produces oscillations in the X-band.

The peak power output of the transmitter tube is at least 275W. The transmitted power is

than radiated into space by using a parabolic antenna with dipole feed. A three port

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circulator used as duplexer provides sufficient isolation between transmitter and the

receiving system. It also couples the return echoes from the targets to the receiving

system with negligible loss. The return echoes are fed to an RF limiter through the

circulator. The limiter output is connected to the balanced mixer. The RF limiter limits

the input power to the balanced mixer to a level which will not damage the diode in the

balanced mixer. The balanced mixer also receives the output from the varactor tunned

Gunn oscillator. The Gunn oscillator is tunned at the frequency 30 MHz above the

transmitter frequency.

The balanced mixer down converts the received RF frequency to an IF frequency

of 30 MHz. The IF signal is then amplified. The IF signal is then amplified in the IF

amplifier unit, detected and the detected pulse envelope is amplified in the video

amplifier stages. The output of the video amplifier is fed to the doppler extraction circuit.

The doppler information contained in the return echo from the moving target is

extracted employing a conventional type of the boxcar detector circuit. This doppler

frequency is then amplified in a chain of the active filters which cuts off both high and

low frequency noises which does not fall in the audio frequency of interest to the radar.

This signal is then applied to the Analog interface circuit (AIC) which also have

a programmable band pass filter and then applied to DSP TMS320C5X. The

TMS320C50 DSK board has built in A/D converter which converts the analog signal

into digital form. The spectrum then computed using TMS 320C50 assembly language

and C language with the help of Graphic interface the echo signal and its spectrum can be

displayed on the monitor of the PC.

As there was no visual display of the target information in the radar ( BFSR MK

- II).So it was very difficult to identified the type and nature of the target. Only

experienced operators was able to recognize the type of the target. And detection

efficiency was totally depended upon the skillness of the operator. This drawback can be

eliminated using TMS 320 C50 DSK. And with help of this work operator is now easily

identified the nature and type of the target on the monitor of the PC.

62

TIME

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FIG BOXER DETECTOR WAVEFORM – MOVING TARGET

AMP

FIG BOXER DETECTOR WAVEFORM – STATIC TARGET TIME

63

AMPLITUDE

30 KHZCRYSTAL

PRF GEN

O/P TO DSP KIT

Regulator

TR

RADARSIG

TGT ECHOGEN

ECHOGATE GEN

AMP ANALOGSWITCH

RANGEGATEDELAYGENR

RANGEGATEGENR

AMP DOPPLERDEMODUL-TOR

Page 64: Radar Signal Detection Using TMS320C50

Fig5.3 block diagram of Doppler extraction

64

DSK

TX

circulator

RF Limiter

MIX IF AMP Detector

Doppler Extraction cct

Band PassFilter

Low FreqAmp

AIC (H/W)

DSP TMS 320 C5x(H/W)

GUI(S/W)

PC WITHMONITOR

Page 65: Radar Signal Detection Using TMS320C50

Fig 5.4 Block diagram of bfsr radar signal system by using tms 320 c5x

5.4 CONCLUSIONS

In this chapter syndicate has discuss implementation of the FFT on real time

DSP TMS320C5X using radix-2 methods. The general theory of radar BFSR and

block description also given in this chapter. The main objective of the signal

processing using DSK TMS320 C50 is to extract the information hidden in the signal

so that operator of radar easily identified nature of the target and number of the targets

even though the speed of the target can also be find out. The radar signal detection

using FFT on DSP TMS 320 C5X is a good approach as shown in the results

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waveform. This project work provides visual systems on the monitor of the PC for

operator.

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CHAPTER 6

6.1 RESULTS AND CONCLUSIONS

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Fig1

The above figure gives a view of the signal spectrum of the Doppler signal from a

moving target. The spectrum gives a relationship between magnitude of the signal

strength (in dB) of the reflected Doppler signal versus frequency of the signal. Here for

the signal, the magnitude at 1KHz is highest relative to other frequencies. Therefore this

implies that the signal is of 1KHz frequency. Hence from the formula of Doppler

principle Fd = 2Vr/(wavelength), where Vr is the relative velocity and Fd is the Doppler

frequency. Therefore we have F0 = Transmitted freq = 10GHz and hence wavelength =

3cm.

So Vr is 15m/s.

Similarly, the below figure shows spectrum of 2KHz signal of 1V amplitude.

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Fig2

The below figure shows spectrum of 2KHz signal andof 2V amplitude. Hece from above

formula we get Vr as 30m/s.Clearly we can observe the change in amplitude from fig 2

and fig3.

Fig3

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Fig4

The above shown spectrum is of 3.8KHz frequency and 1V amplitude.Hence we get Vr

as 57m/s.

Fig5

The above shown spectrum is of 6.175KHz frequency and 2V amplitude. Since the

maximum frequency shown by above spectrum analyser is 4.75KHz,the spectrum of

6.175KHz signal gets folded back and signal component present at 3.325KHz as shown

above. Here we get Vr as 114m/s.

REFERENCES

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1. TMS320C5x User’s Guide.

2. TMS320C5x General-Purpose Applications User’s Guide.

3. Brigham, E.O., The Fast Fourier Transform, Englewood Cliffs, NJ: Prentice-Hall.

4. Oppenheim, Alan V., and R.W. Schafer, Digital Signal Processing, Engle-wood Cliffs,

NJ.

5. www.ti.com/dsps 6. www.wikipedia.com

7. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, “Optimization by simulated annealing,” Science, vol. 220, pp. 671–680, May 1983.

8. Moharir.P.S, Singh.R.and Maru .,”S-K-H algorithm for signal design”, Electronic letter, vol 32, no 18, pp.1642-1649, Aug 1996.

9. Moharir.P.S and Maru .V.M and Singh.R., “Bi-parental Product algorithm for coded waveform design in radar”, sadhana, vol.22, no.5,pp 589-599, Oct. 1997.

10. S.P.Singh, and Dr K. Subba Rao, “A Modified Simulated Annealing Algorithm for Binary Coded Radar signal design” IRSI 2005, Banglore, 19-23 Dec 2005.

11. Hai Deng “Polyphase Code Design for orthogonal Netted Radar Systems” IEEE Trans. Signal processing, vol. 52, pp 3126-3135, Nov 2004.

12. M. I. Skolnik, Introduction to Radar Systems. New York: McGraw- Hill, 1980.

13. E. C. Farnett and G. H. Stevens, “Pulse compression radar,” in Radar Handbook, Second ed. New York: McGraw-Hill, 1990, ch. 10.

14. C. E. Cook and M. Bernfield, Radar Signals: An Introduction to Theory and Application. New York: Academic, 1967..

15. S. White, “Concept of scale in simulated annealing,” in Proc. IEEE Int. Conf. Comput. Design, 1984, pp. 646–651.

16. M. D. Huang, F. Romeo, and A. Sangiovanni-Vincentelli, “An efficient general cooling schedule for simulated annealing,” in Proc. IEEE Int. Conf. CAD, 1986, pp. 381–384.

17. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, “Optimization by simulated annealing,” Science, vol. 220, pp. 671–680, May 1983.

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Appendix A

Program code for FFT

* TAKE THE SAMPLED INPUT DATA

; 0400h & 0300h = N

; 0401h & 0301h = No. of groups per stage

; 0402h & 0302h = Butterflies per group

; 0403h & 0303h = node_space

; 0404h & 0304h = Twiddle factors or Block exponents

; 0405h & 0305h = No. of stages

.include "sine"

.include "cosine"

N .set 0300h

N1 .set 0400h

N_2 .set 0301h

N_21 .set 0401h

LOGN .set 0305h

LOGN1 .set 0405h

S_RATE .set 0310h

S_RATE1 .set 0410h

ADD1 .set 0320h

.ds 0302h

.byte 01h,01h,01h

.ds 0402h

.byte 01h,01h,01h

.mmregs

.ps 080ah

B LOP1

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B LOP2

.ps 00a00h

.entry ; Program execution starts

; from this location (0a00h)

.include "parmeter"

* LAR AR0,#0300h

* SPLK #10h,*+,AR0

* SPLK #04h,*+,AR0

* LAR AR0,#0400h

* SPLK #10h,*+,AR0

* SPLK #04h,*+,AR0

ZAP

LDP DRR

LDP #0h ; Pointing to page0

LAR AR0,#1100h

LDP #06h

LACC 0h,0 ; Take no of points from 0300h location

SACB

LDP #0h

LAMM IMR ; Enabling the

OR #010h ; RINT and

SAMM IMR ; XINT interrupts

LOOP: ZAP

LDP DRR

MAR *,AR0

LDP #0

LAMM DRR

SFR

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SACL *+,0,AR0

LACB

SUB #01h

BCND JMP,LT,EQ

SACB

NOP

MAR *,AR6

LAR AR6 #0310h

RPT *,AR6

NOP

RPT *,AR6

NOP

RPT *,AR6

NOP

RPT *,AR6

NOP

RPT *,AR6

NOP

RPT *,AR6

NOP

NOP

NOP

NOP

MAR *,AR0

B LOOP

* RINT INTERRUPT SERVICE ROUTINE

LOP1:

RETE

* XINT INTERRUPT SERVICE ROUTINE

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LOoP2:

RETE

* BIT REVERSAL OF INPUT DATA

JMP: MAR *,AR0

LDP #06h

LAR AR0,20h

LACC 0,0

A1: SACB

LACC #0,0

SACL *+,0,AR0

LACB

SUB #01h

BCND A1,GT

LDP #0h

LAMM IMR

AND #0FFCFh

SAMM IMR

NOP

LDP #06h

LACC 0h,0

LDP #0h

SAMM INDX

LDP #06h

LAR AR0,#1000h

LACC 0,1

SUB #01h

SACL 30,0

RPT 30,AR0

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BLDD #1100h,*BR0+

NOP

NOP

NOP

NOP

* BUTTERFLY CALCULATIONS

* LDP #06h

* SPLK #01h,02h

* SPLK #01h,03h

* SPLK #00h,04h

* SPLK #03h,05h

* LDP #08h

* SPLK #01h,02h

* SPLK #01h,03h

* SPLK #00h,04h

* SPLK #03h,05h

LAR AR1,#1000h

LAR AR2,#1002h

LAR AR3,#1200h

LAR AR4,#1300h

LAR AR5,#1290h

MAR *,AR2

BFLY_ST: LT *+,AR3

MPY *,AR2

LTP *-,AR4

MPY *,AR3

MPYA *+,AR2

LT *,AR5

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SACH *,1,AR1

ADD *,15

SACH *+,0,AR5

SUB *,16,AR2

SACH *+,0,AR1

LACC *,15,AR4

MPYS *+,AR2

APAC

SACH *+,0,AR1

NEG

ADD *,16

btflyend: SACH *+,0,AR2

* MORE BUTTERFLIES

LDP #06h

LACC 02h,0

SUB #01h

SACL 02h,0

RPT #10h

SFL

BCND LOOP1,GT

* MORE GROUPS

LDP #06h

LACC 01h,0

SUB #01h

SACL 01h,0

RPT #10h

SFL

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BCND LOOP2,GT

* MORE STAGES

LDP #06h

LACC 05h,0

SUB #01h

SACL 05h,0

RPT #10h

SFL

BCND LOOP3,GT

* OUTPUT THE COMPUTED SPECTRUM

IDLE

* SETUP FOR NEXT BUTTERFLY

LOOP1:

* LDP #06h

* LACC 03h,1

* MAR *,AR1

*N1: MAR *+,AR1

* SUB #01h

* BCND N1,GT

* LACC 03h,1

* MAR *,AR2

*N2: MAR *+,AR2

* SUB #01h

* BCND N2,GT

B BFLY_ST

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* SETUP FOR NEXT GROUP

LOOP2: LDP #06h

LACC 03h,1

SFR

SFL

SAR AR1,08h

ADD 08h,0

SACL 08h,0

LAR AR1,08h

LACC 03h,1

SFR

SFL

SAR AR2,08h

ADD 08h,0

SACL 08h,0

LAR AR2,08h

B BFLY_ST

* SETUP FOR NEXT STAGE

LOOP3: LDP #08h

LACC 01h,0 ; Divide the no. of

SFR ; groups per stage

SACL 01h,0 ; by 2

LACC 02h,1 ;

SACL 02h,0 ;

LACC 03h,1

SACL 03h,0

LAR AR1,#1000h

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LAR AR2,#1000h

LACC 03h,1

MAR *,AR2

N3: MAR *+,AR2

SUB #01h

BCND N3,GT

* TRANSFERRING NEXT STAGE VALUES TO 0300 TO 0303 LOCATIONS

MAR *,AR6

LAR AR6,#0300h

RPT #03h

BLDD #0400h,*+

MAR *,AR2

B BFLY_ST

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Appendix B

Program code for Triangular wave Generation

.mmregs

.ps 0080ch

B XINT ;

.ps 00a00h

.entry

LDP #0 ;

CALL sp_init ;

LAMM IMR ;

OR #20h ;

SAMM IMR ;

SPLK #0ffffh, IFR ;

LOOP: ADD #10 ;

SACL DXR,3 ;

IDLE

B LOOP ;

XINT: RETE ;

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Appendix C

Program code for Square wave Generation

.mmregs

.ds 1000H

.ps 0A00H

.entry

AMP+VE .SET 7FFFH

AMP-VE .SET 9FFFH

TON .SET 0F00H

TOFF .SET 0F00H

.ENTRY

SETC INTM

SPLK #22H,IMR

SPLK #0H,CWSR

SPLK #0H,PDWSR

CLRC INTM

LOOP LAR AR0,#TON

LAR AR1,#TOFF

LACC #AMP+VE

AND #0FFFCH

RPT #TON

SAMM DXR

LACC #AMP-VE

AND #0FFFCH

RPT #TOFF

SAMM DXR

B LOOP

.end

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