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PROJECT REPORT ON DESIGN AND SIMULATION OF 16 BIT MICROPROCESSOR SUBMITTED BY –
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Project Report Vhdl

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Page 1: Project Report Vhdl

PROJECT REPORT

ON

DESIGN AND

SIMULATION OF 16 BIT

MICROPROCESSOR

SUBMITTED BY –

RICHA SHUKLA ACKNOWLEDGEMENT

Page 2: Project Report Vhdl

This project report bears the imprint of many persons and I would be failing my duty if do not express sincere regards to those who have been instrumental in the finalization of the report.

First of all I would like to express sincere and heartfelt sense of gratitude to my mentor Er. Pankaj Singh for the continuous guidance through out the training period .I owe a deep sense of gratitude to him and learned a lot from him. A big contribution and hard work from you during the four week is very great indeed.Also I learnt how to work in a team.

Beside this I am thankful to the faculty of Cetpa InfotechPvt. Ltd. for their support throughout the training period .

It goes without saying that I alone will be held for any errors in the report .

RICHA SHUKLA

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CONTENTS

Abstract Introduction Microprocessor

Origin of µP History What is µP ? Developments and Researches

VHDL Scope of VHDL Definition Benefits of using VHDL Basic language elements

Data Types Describing a design

Styles of Modelling Design of 16-bit microprocessor

Coding RTL view Simulation

Why we used VHDL ? Conclusion

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ABSTRACT

A microprocessor (sometimes abbreviated µP) is a digital electronic component with transistors on a single semiconductor integrated circuit (IC). One or more microprocessors typically serve as a central processing unit (CPU) in a computer system or handheld device. Microprocessors made possible the advent of microcomputer. Before this, electronic CPUs were typically made from bulky discrete switching devices containing the equivalent of only a few transistors . By integrating the processor onto one or a very few large-scale integrated circuit packages, the cost of processor power was greatly reduced. Since the advent of the IC in the mid-1970s, the microprocessor has become the most prevalent implementation of the CPU, nearly completed replacing all other forms. This project is trying to design 16 bit microprocessor by using VHDL. VHDL stands for Very High Speed Integrated Circuit Hardware Description Language. It is one of the most popular design application used by most of the designers nowadays. The microprocessor will be synthesized in VHDL using Xilinx ISE. Then it will be simulated using ModelSim and the programs are burn into FPGA board.the FPGA should act as actual microprocessor.

INTRODUCTION

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This project entitles 16 bit microprocessor design using VHDL. Microprocessors are the important part of the field of Electronics Engineering. This is a very interesting project because processors are not as flexible as programmable logic. The ability to emulate a microprocessor on a programmable chip can lead to cheaper, more efficient and more flexible performance.

The design is implemented by programming it into a FPGA. The design was first completed and simulated. Once the simulation proved successful, the VHDL is implemented on the FPGA. The desired instructions are executed and the data to be operated on, is given to the system as inputs. The result of the executed instruction is the output. The final goal is to program FPGA with the VHDL code that was written.

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ORIGIN OF µP

WHOSE BRAINCHILD WAS THE BRAIN CHIP?

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In 1969, year-old Intel Corp. was working feverishly to invent the dynamic random-access memory, or DRAM. Intel unveiled the chip in 1970. By the mid-1980s, however, Intel was forced to abandon this early success as Japanese rivals dumped DRAMs on the market.

So Intel was fortunate that in those early days it was also dragged into the race to design the first microprocessor. Researchers had been discussing the idea of a computer-on-a-chip since the mid-1960s, and if Intel had dallied, someone else would almost certainly have built one first.

What got Intel going was a visit by Japanese engineer Masatoshi Shima in April, 1969. He brought with him plans for a set of seven chips that his company, Busicom Corp., wanted for a desktop calculator. Intel took the job of turning the plans into silicon chips.

BREATHING SPELL. Initially, things moved slowly because Intel was preoccupied with DRAMs. Engineers repeatedly were taken off the Busicom project to work on DRAMs. That summer, though, Marcian E. ''Ted'' Hoff Jr. had a brainstorm. He quickly blocked out an alternative design for the new chip. He wanted to discard Shima's decimal design--specifically suited for things like calculators--in favor of a digital processor using binary logic. This processor would do math by executing three dozen 4-bit instructions. Busicomapproved, but the project continued only to inch ahead.

Then, in November, 1969, a team led by Victor D. Poor at Datapoint Corp. (then called Computer Terminal Corp.) hatched a plan for an 8-bit programmable computer terminal. It contained the nucleus for all modern microprocessors. Poor asked both Intel and Texas Instruments Inc. to take a crack at it. That heightened Intel's interest. At TI, Gary W. Boone initially figured the processor would require a set of three chips. But his team switched to a single-chip approach after Boone heard that Intel was taking that tack.

In the spring of 1970, Shima made another visit to Intel. Disappointed by the lack of progress, he stayed on to lend a hand, working on the logic design of Hoff's digital chip while Hoff concentrated on the overall integration of the logic chip and three types of support chips. Pitching in were Stanley Mazor, who took charge of software matters, and Federico Faggin, who ran the program and engineered silicon circuits from Shima's blueprints. This is the team that was recently inducted into the National Inventor's Hall of Fame.

In March, 1971, Intel produced the first microprocessor and began deliveries to Busicom. Two months later, Texas Instruments built the first 8-bit microprocessor for Datapoint. Although Datapoint decided the chip didn't measure up, TI became the first chipmaker to publicly announce a microprocessor. Boone began adapting the technology to other TI chips, but he failed to persuade TI to promote the technology. That gave Intel a chance to catch up.

Intel's engineers eventually convinced the company's marketing chief that the Busicom chip had broad potential. In November, 1971, Intel announced its 4-bit chip family with ads proclaiming ''a new era of integrated electronics.'' Each fingernail-size 4004 chip packed as much computing power as the first electronic computer, ENIAC, which was almost as big as a two-car garage when it was built from 18,000 vacuum tubes in 1946.

With only 2,300 transistors, the 4004 microprocessor was primitive by today's standards. But it was the launchpad for Intel's eventual domination of the PC market. And even today, the

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4004 is still blazing new trails. It's the brain of Pioneer 10, which was launched on Mar. 2, 1972, to gather the first close-up images of Jupiter--and is now exploring space beyond the solar system, where no microprocessor has gone before.

The Microprocessor Arrives 

The average number of electronic components packed on a silicon chip doubled each year after 1965, and this progress led to a dramatic development: the creation of a microprocessor that could be placed on a single chip. A microprocessor contains all the circuits needed to perform arithmetic-logic and control functions. A complete processor unit can be built with a microprocessor, a few additional primary storage chips, and other support circuitry.

The origin of the microprocessor can be traced back to the late 1960s. During this time, Victor Poor, a Datapoint Corporation electronics engineer, was working on the design and development of special-purpose computers. Each time a custom-designed device was needed, Poor and other engineers started the design effort from scratch. This seemed a bug waste of time to Poor. Instead, he reasoned, if the basic arithmetic-logic and control elements of a computer could be placed on a single silicon chip, the chip could be mass-produced and the programmed in different ways to perform special jobs.

In 1969, Poor and Harry Pyle, another young Datapoint engineer, developed a model of a microprocessor chip. Since Datapoint Corporation did not make electronic components, Poor took his "chip processor" model to two component manufacturers - Texas Instruments and Intel Corporation - in hopes they would manufacture the chip for Datapoint. No immediate decisions came from these meetings, but the component manufacturers were free to use the microprocessor chip concept - and they did.

HISTORY

A microprocessor incorporates the functions of a computer's central processing unit (CPU) on a single integrated circuit (IC or microchip). It is a multipurpose, programmable, clock-driven, register-based electronic device that accepts digital data as input, processes it according to instructions stored in its memory, and provides results as output. It is an

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example of sequential digital logic, as it has internal memory, i.e. its registers. Nearly all microprocessors, currently and historically, accept, produce, and internally operate on binary data (binary code and binary numbers), making them binary digital computer processors. (This is one point that differentiates microprocessors as a class, architecturally, from early non-integrated circuit computers such asvacuum tube computers, many of which used decimal digital logic in their vacuum tube circuits.)

Microprocessors are generally a category of finite state machines. Most microprocessors, in combination with external main memory and essential supporting hardware (typically such as a main timing oscillator and I/O "glue logic") also meet the definition of a Turing machine, except that their memories are finite. (A Turing machine has infinite memory space, so, strictly speaking, it is only theoretical.) Most modern microprocessors are also Von Neumann machines, meaning mainly that they store the data that controls their processing and the data that they process in the same single memory (rather than in two separate memories as in the Harvard architecture.) However, there are exceptions, and a device does not have to have the Von Neumann design in order to be a microprocessor.

During the 1960s, computer processors were often constructed out of small and medium-scale ICs each containing from tens to a few hundredtransistors. For each computer built, all of these had to be placed and soldered onto printed circuit boards (usually by hand), and often multiple boards would have to be interconnected in a chassis. The large number of discrete logic gates used more electrical power—and therefore, produced more heat—than a more integrated design with fewer ICs, and, even more significantly, the distance that signals had to travel between ICs on the boards limited the speed at which a computer could operate.

The integration of a whole CPU onto single chip or only a handful of chips greatly reduced the cost of processing power. It did this in many ways: it reduced the manufacturing cost by reducing the assembly labor and energy, the amount of materials required, and the size and weight of each finished computer (benefitting stocking and shipping); and it reduced the operating cost by, again, reducing the size and weight of a computer and its power and cooling requirements (all reducing facilities costs and saving on energy bills), increasing reliability (as there were many fewer electrical connections to fail, the processor was physically encapsulated, and less heat was generated), increasing computing speed (with additional efficiency benefits, since it generally takes less additional energy [power] to run one computer faster than to run more computers simultaneously for the same net throughput increase. Consider also, for example, that a computer that finishes in half the time needs the air conditioning system to run for only half as long.) As microprocessor designs get faster, the cost of manufacturing a chip (with smaller components built on a semiconductor chip the same size) generally stays the same.

The first microprocessors merely integrated into one or a few large-scale ICs the same level of sophistication that had previously been implemented using many more medium- and small-scale integrated circuits. From these beginnings, humble by today's standards (but exciting and cutting-edge by the standards of the time) continued increases in microprocessor capacity have rendered other forms of computers almost completely obsolete (see history of computing hardware), with one or more microprocessors used in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers.

The first microprocessors emerged in the early 1970s and were used for electronic calculators, using binary-coded decimal (BCD) arithmetic on 4-bit words. Other embedded uses of 4-bit and 8-bit microprocessors, such as terminals, printers, various

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kinds of automation etc., followed soon after. Affordable 8-bit microprocessors with 16-bit addressing also led to the first general-purpose microcomputers from the mid-1970s on.

Since the early 1970s, the increase in capacity of microprocessors has followed Moore's law, which suggests that the number of transistors that can be fitted onto a chip doubles every two years. Although originally calculated as a doubling every year, Moore later refined the period to two years. It is often incorrectly quoted as a doubling of transistors every 18 months.

Enabling the construction of general-purpose computers that are much smaller, less expensive, more powerful, and more energy efficient than their less integrated historical counterparts is only one side of the transformative story of the microprocessor. Microprocessors have also revolutionized many technologies and products by making it possible to put a computer, and even one so inexpensive that it can be adisposable computer, into thousands of items that were traditionally not computer-related. These include large and small household appliances, cars (and their accessory equipment units), carkeys, tools and test instruments, toys, lightswitches/dimmers and electrical circuit breakers, smoke alarms, battery packs, and hi-fi audio/visual components (from DVD players to phonograph turntables.) It is instructive to note that the DVD video system and the American TSC HDTV broadcast system fundamentally require consumer devices that are entirely based around relatively powerful microprocessors. The ubiquity of the microprocessor is a starting point of DVD and ATSC (and most if not all other national HDTV systems). In contrast, the popular predecessor of DVD, the VHS analog videotape system, was originally introduced [in the late 1970s] with machines (VCRs) that were solely a combination of electromechanical and analog electronic (solid-state) technology—with no digital electronics whatsoever. The predecessor of ATSC, the NTSC analog broadcast video system, was designed in the 1940s specifically for analog vacuum tube technology, and was updated in the 1960s to add color, still using analog vacuum tube or solid-state circuitry. By the mid-1990s, however, all new NTSC TV sets contained at least one microprocessor, as did all VCRs; some had several. All of the examples of microprocessor applications in this paragraph are examples of embedded microprocessors; the products that contain microprocessors are embedded systems.

WHAT IS µP ?

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A silicon chip that contains a CPU. In the world of personal computers, the terms microprocessor and CPU are used interchangeably. At the heart of all personal

computers and most workstations sits a microprocessor. Microprocessors also control the logic of almost all digital devices, from clock radios to fuel-injection systems for

automobiles.

Three basic characteristics differentiate microprocessors:- Instruction set: The set of instructions that the microprocessor can execute.

-bandwidth : The number of bits processed in a single instruction.

- clock speed : Given in megahertz (MHz), the clock speed determines how many instructions per second the processor can execute.

In both cases, the higher the value, the more powerful the CPU. For example, a 32-bit microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that runs at 25MHz.In addition to bandwidth and clock speed, microprocessors are classified as being either RISC (reduced instruction set computer) or CISC (complex instruction set computer).

The first commercial microprocessor was the Intel 4004 which appeared in 1971. This was the CPU member of a set of four LSI integrated circuits called the MCS-4, which was originally designed for use in a calculator but was marketed as "programmable controller for logic replacement". The 4004 is referred to as a 4-bit microprocessor since it processed only 4 bits of data at a time. This very short word size is due mainly to the limitations imposed by the maximum integrated circuit density then achievable. As integrated circuit densities increased with the rapiddevelopment of integrated circuit manufacturing technology, thepower and performance of the microprocessors also increased.This is reflected in the increase in the CPU word size to 4, 8, 16and by mid-1980s, 32 bits. The smaller microprocessors haverelatively simple instruction sets, e.g., no floating point instructions, but they are nevertheless suitable ascontrollers for a very wide range of applications such as carengines and microwave ovens. The Intel 4004 was followed with, among others the 4040, 8008,8080, 8086, 80186, 80286, 80386, 486 and Pentium. Otherfamilies include the Motorola 6800 and 680x0 families, National Semiconductor 16000 and National Semiconductor 32000, SPARC,ARM, MIPS, Zilog Z8000, PowerPC and the Inmos Transputer  family. The larger, more recent microprocessors families have graduallyacquired most of the features of large computers. As themicroprocessor industry has matured, several families ofmicroprocessors have evolved into de facto industrial standardswith multiple manufacturers and numerous "support" chipsincluding RAM, ROM, I/O controllers etc. A single chip microprocessor may include other components suchas memory ( RAM, ROM, PROM), memory management, caches,floating-point unit, input/output ports and timers. Such devicesare also known as microcontrollers.The one-chip microcomputer is in many respects, a landmarkdevelopment in computer technology because it reduces thecomputer to a small, inexpensive, and easily replaceable designcomponent. 

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Microcomputers have given rise to a new class of general-purpose machines called personal computers. These are small lowcost computers that are designed to sit on an ordinary officedesk or to be portable and fuelled the computer boom of the late1980s. The most widespread example is the also IBM PC, basedon microprocessors from Intel Corporation. Apple Computers, Inc. have also produced a range of personal computers, as haveseveral other companies. 

DEVELOPMENTS AND RESEARCHES

Intel 4004

The Intel 4004 is generally regarded as the first microprocessor, and cost thousands of dollars. The first known advertisement for the 4004 is dated November 1971 and appeared inElectronic News.

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TMS 1000

The Smithsonian Institution says TI engineers Gary Boone and Michael Cochran succeeded in creating the first microcontroller (also called a microcomputer) in 1971. The result of their work was the TMS 1000, which went commercial in 1974.

TI developed the 4-bit TMS 1000 and stressed pre-programmed embedded applications, introducing a version called the TMS1802NC on September 17, 1971 which implemented a calculator on a chip.

TI filed for the patent on the microprocessor.

Pico/General Instrument

The PICO1/GI250 chip introduced in 1971. This was designed by Pico Electronics (Glenrothes, Scotland) and manufactured by General Instrument of Hicksville NY

In 1971 Pico Electronics and General Instrument (GI) introduced their first collaboration in ICs, a complete single chip calculator IC for the Monroe/Litton Royal Digital III calculator. This chip could also arguably lay claim to be one of the first microprocessors or microcontrollers having ROM, RAM and a RISC instruction set on-chip. The layout for the four layers of the PMOS process was hand drawn at x500 scale on mylar film, a significant task at the time given the complexity of the chip.

Calculators were becoming the largest single market for semiconductors and Pico and GI went on to have significant success in this burgeoning market. GI continued to innovate in microprocessors and microcontrollers with products including the CP1600, IOB1680 and PIC1650.In 1987 the GI Microelectronics business was spun out into the Microchip PIC microcontroller business.

CADC

In 1968, Garrett AiResearch (which employed designers Ray Holt and Steve Geller) was invited to produce a digital computer to compete with electromechanical systems then under development for the main flight control computer in the US Navy's new F-14 Tomcat fighter. The design was complete by 1970, and used a MOS-based chipset as the core CPU. The

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design was significantly (approximately 20 times) smaller and much more reliable than the mechanical systems it competed against, and was used in all of the early Tomcat models. This system contained "a 20-bit, pipelined, parallel multi-microprocessor". According to Parab et al. (2007), "The scientific papers and literature published around 1971 reveal that the MP944 digital processor used for the F-14 Tomcat aircraft of the US Navy qualifies as the first microprocessor. Although interesting, it was not a single-chip processor, and was not general purpose – it was more like a set of parallel building blocks you could use to make a special-purpose DSP form. It indicates that today’s industry theme of converging DSP-microcontroller architectures was started in 1971." This convergence of DSP and microcontroller architectures is known as a Digital Signal Controller.

Four-Phase Systems AL1

The Four-Phase Systems AL1 was an 8-bit bit slice chip containing eight registers and an ALU.It was designed by Lee Boysel in 1969.

 At the time, it formed part of a nine-chip, 24-bit CPU with three AL1s, but it was later called a microprocessor when, in response to 1990s litigation by Texas Instruments, a demonstration system was constructed where a single AL1 formed part of a courtroom demonstration computer system, together with RAM, ROM and an input-output device.

8-bit designs

The Intel 4004 was followed in 1972 by the Intel 8008, the world's first 8-bit microprocessor. In late 1970 or early 1971, TI dropped out being unable to make a reliable part. In 1970, with Intel yet to deliver the part, CTC opted to use their own implementation in the Datapoint3300, using traditional TTL logic instead (thus the first machine to run “8008 code” was not in fact a microprocessor at all). Intel's version of the 1201 microprocessor arrived in late 1971, but was too late, slow, and required a number of additional support chips.

The 8008 was the precursor to the very successful Intel 8080 (1974), which offered much improved performance over the 8008 and required fewer support chips, Zilog Z80 (1976), and derivative Intel 8-bit processors.

The Western Design Center, Inc. (WDC) introduced the CMOS 65C02 in 1982 and licensed the design to several firms. It was used as the CPU in the Apple IIe and IIc personal computers as well as in medical implantable grade pacemakers and defibrilators, automotive, industrial and consumer devices. WDC pioneered the licensing of microprocessor designs, later followed by ARM and other microprocessor Intellectual Property (IP) providers in the 1990s.

Motorola introduced the MC6809 in 1978, an ambitious and thought-through 8-bit design source compatible with the 6800 and implemented using purely hard-wired logic. (Subsequent 16-bit microprocessors typically used microcode to some extent, as CISC design requirements were getting too complex for purely hard-wired logic only.)

Another early 8-bit microprocessor was the Signetics 2650, which enjoyed a brief surge of interest due to its innovative and powerful instruction set architecture.

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12-bit designs

The Intersil 6100 family consisted of a 12-bit microprocessor (the 6100) and a range of peripheral support and memory ICs. The microprocessor recognised the DEC PDP-8 minicomputer instruction set. As such it was sometimes referred to as the CMOS-PDP8. Since it was also produced by Harris Corporation, it was also known as the Harris HM-6100. By virtue of its CMOS technology and associated benefits, the 6100 was being incorporated into some military designs until the early 1980s.

16-bit designs

The first multi-chip 16-bit microprocessor was the National Semiconductor IMP-16, introduced in early 1973. An 8-bit version of the chipset was introduced in 1974 as the IMP-8.

Other early multi-chip 16-bit microprocessors include one used by Digital Equipment Corporation (DEC) in the LSI-11 OEM board set and the packaged PDP 11/03 minicomputer, and the Fairchild Semiconductor MicroFlame 9440, both of which were introduced in the 1975 to 1976 timeframe.

In 1975, National introduced the first 16-bit single-chip microprocessor, the National Semiconductor PACE, which was later followed by anNMOS version, the INS8900.

Another early single-chip 16-bit microprocessor was TI's TMS 9900, which was also compatible with their TI-990 line of minicomputers. The 9900 was used in the TI 990/4 minicomputer, the TI-99/4A home computer, and the TM990 line of OEM microcomputer boards. The chip was packaged in a large ceramic 64-pin DIP package, while most 8-bit microprocessors such as the Intel 8080 used the more common, smaller, and less expensive plastic 40-pin DIP. A follow-on chip, the TMS 9980, was designed to compete with the Intel 8080, had the full TI 990 16-bit instruction set, used a plastic 40-pin package, moved data 8 bits at a time, but could only address 16 KB. A third chip, the TMS 9995, was a new design. The family later expanded to include the 99105 and 99110.

The Western Design Center, Inc. (WDC) introduced the CMOS 65816 16-bit upgrade of the WDC CMOS 65C02 in 1984. The 65816 16-bit microprocessor was the core of the Apple IIgs and later the Super Nintendo Entertainment System, making it one of the most popular 16-bit designs of all time.

Intel followed a different path, having no minicomputers to emulate, and instead "upsized" their 8080 design into the 16-bit Intel 8086, the first member of the x86 family, which powers most modern PC type computers. Intel introduced the 8086 as a cost effective way of porting software from the 8080 lines, and succeeded in winning much business on that premise. The 8088, a version of the 8086 that used an 8-bit external data bus, was the microprocessor in the first IBM PC, the model 5150. Following up their 8086 and 8088, Intel released the 80186 and 80188, the 80286 and, in 1985, the 32-bit 80386, cementing their PC market dominance with the processor family's backwards compatibility. The 80186 and 80188 were essentially versions of the 8086 and 8088, respectively, enhanced with some onboard peripherals and a few new instructions; they were not used in IBM-compatible PCs because the built-in peripherals and their locations in the memory map were incompatible with the IBM design. The 8086 and successors before the 80286 had an innovative but limited method

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of memory segmentation, while the 80286 introduced a full-featured segmented memory management unit (MMU), and the 80386 introduced a flat 32-bit memory model with paged memory management.

32-bit designs

16-bit designs had only been on the market briefly when 32-bit implementations started to appear.

The most significant of the 32-bit designs is the MC68000, introducedin 1979. The 68K, as it was widely known, had 32-bit registers in its programming model but used 16-bit internal data paths, 3 16-bit Arithmetic Logic Units, and a 16-bit external data bus (to reduce pin count), and supported only 24-bit addresses. In PC-based IBM-compatible mainframes the MC68000 internal microcode was modified to emulate the 32-bit System/370 IBM mainframe.[30] Motorola generally described it as a 16-bit processor, though it clearly has 32-bit capable architecture. The combination of high performance, large (16 megabytes or 224 bytes) memory space and fairly low cost made it the most popular CPU design of its class.

The world's first single-chip fully-32-bit microprocessor, with 32-bit data paths, 32-bit buses, and 32-bit addresses, was the AT&T Bell Labs BELLMAC-32A, with first samples in 1980, and general production in 1982[31][32] After the divestiture of AT&T in 1984, it was renamed the WE 32000 (WE for Western Electric), and had two follow-on generations, the WE 32100 and WE 32200. These microprocessors were used in the AT&T 3B5 and 3B15 minicomputers; in the 3B2, the world's first desktop supermicrocomputer; in the "Companion", the world's first 32-bit laptop computer; and in "Alexander", the world's first book-sized supermicrocomputer, featuring ROM-pack memory cartridges similar to today's gaming consoles. All these systems ran the UNIX System Voperating system.

Intel's first 32-bit microprocessor was the iAPX 432, which was introduced in 1981 but was not a commercial success. It had an advancedcapability-based object-oriented architecture, but poor performance compared to contemporary architectures such as Intel's own 80286 (introduced 1982), which was almost four times as fast on typical benchmark tests. However, the results for the iAPX432 was partly due to a rushed and therefore suboptimal Ada compiler.

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Other large companies designed the 68020 and follow-ons into embedded equipment. At one point, there were more 68020s in embedded equipment than there were Intel Pentiums in PCs. The ColdFire processor cores are derivatives of the venerable 68020.

During this time (early to mid-1980s), National Semiconductor introduced a very similar 16-bit pinout, 32-bit internal microprocessor called the NS 16032 (later renamed 32016), the full 32-bit version named the NS 32032. Later the NS 32132 was introduced which allowed two CPUs to reside on the same memory bus, with built in arbitration. The NS32016/32 outperformed the MC68000/10 but the NS32332 which arrived at approximately the same time the MC68020 did not have enough performance. The third generation chip, the NS32532 was different. It had about double the performance of the MC68030 which was released around the same time. The appearance of RISC processors like the AM29000 and MC88000 (now both dead) influenced the architecture of the final core, the NS32764. Technically advanced, using a superscalar RISC core, internally overclocked, with a 64 bit bus, it was still capable of executing Series 32000 instructions through real time translation.

In the late 1980s, "microprocessor wars" started killing off some of the microprocessors. Apparently, with only one major design win, Sequent, the NS 32032 just faded out of existence, and Sequent switched to Intel microprocessors.

From 1985 to 2003, the 32-bit x86 architectures became increasingly dominant in desktop, laptop, and server markets, and these microprocessors became faster and more capable. Intel had licensed early versions of the architecture to other companies, but declined to license the Pentium, so AMD and Cyrix built later versions of the architecture based on their own designs. During this span, these processors increased in complexity (transistor count) and capability (instructions/second) by at least three orders of magnitude. Intel's Pentium line is probably the most famous and recognizable 32-bit processor model, at least with the public at large.

64-bit designs in personal computers

While 64-bit microprocessor designs have been in use in several markets since the early 1990s, the early 2000s saw the introduction of 64-bit microprocessors targeted at the PC market.

With AMD's introduction of a 64-bit architecture backwards-compatible with x86, x86-64 (also called AMD64), in September 2003, followed by Intel's near fully compatible 64-bit extensions (first called IA-32e or EM64T, later renamed Intel 64), the 64-bit desktop era began. Both versions can run 32-bit legacy applications without any performance penalty as well as new 64-bit software. With operating systems Windows XP x64, Windows Vista x64, Windows 7 x64, Linux, BSD and Mac OS X that run 64-bit native, the software is also geared to fully utilize the capabilities of such processors. The move to 64 bits is more than just an increase in register size from the IA-32 as it also doubles the number of general-purpose registers.

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SCOPE OF VHDL

VHDL is suited to the specification, design and description of digital electronic hardware.

System levelVHDL is not ideally suited for abstract system-level simulation, prior to the hardware-software split. Simulation at this level is usually stochastic, and is concerned with modelling performance, throughput, queueing and statistical distributions. VHDL has been used in this area with some success, but is best suited to functional and not stochastic simulation.

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DigitalVHDL is suitable for use today in the digital hardware design process, from specification through high-level functional simulation, manual design and logic synthesis down to gate-level simulation. VHDL tools usually provide an integrated design environment in this area.VHDL is not suited for specialized implementation-level design verification tools such as analog simulation, switch level simulation and worst case timing simulation. VHDL can be used to simulate gate level fanout loading effects providing coding styles are adhered to and delay calculation tools are available. The standardization effort named VITAL (VHDL Initiative Toward ASIC Libraries) is active in this area, and is now bearing fruit in that simulation vendors have built-in VITAL support. More importantly, many ASIC vendors have VITAL-compliant libraries, though not all are allowing VITAL-based sign-off - not yet anyway.

AnalogueIn 1999, the IEEE approved Standard 1076.1, which is informally known as VHDL-AMS. It is a true super-set of VHDL, and includes analog and mixed-signal extensions.

Design processThe diagram below shows a very simplified view of the electronic system design process incorporating VHDL.

DEFINITION

VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.

INITIAL DESIGN ENTRY

LOGIC OPTIMIZATION

TECHNOLOGY MAPPING (SYNTHESIZE)

PLACEMENT

ROUTE

PROGRAMMING UNIT

CONFIGURED DEVICE (FPGA)

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VHSIC is an abbreviation for Very High Speed Integrated Circuit. It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits.VHDL is a notation, and is precisely and completely defined by the Language Reference Manual ( LRM ). This sets VHDL apart from other hardware description languages, which are to some extent defined in an ad hoc way by the behaviour of tools that use them. VHDL is an international standard, regulated by the IEEE. The definition of the language is non-proprietary.VHDL is not an information model, a database schema, a simulator, a toolset or a methodology! However, a methodology and a toolset are essential for the effective use of VHDL.Simulation and synthesis are the two main kinds of tools which operate on the VHDL language. The Language Reference Manual does not define a simulator, but unambiguously defines what each simulator must do with each part of the language.VHDL does not constrain the user to one style of description. VHDL allows designs to be described using any methodology - top down, bottom up or middle out! VHDL can be used to describe hardware at the gate level or in a more abstract way. Successful high level design requires a language, a tool set and a suitable methodology!

BENEFITS OF USING VHDL

Executable specificationVHDL allows this issue to be addressed in two ways: A VHDL specification can be executed in order to achieve a high level of confidence in its correctness before commencing design, and may simulate one to two orders of magnitude faster than a gate level description. A

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VHDL specification for a part can form the basis for a simulation model to verify the operation of the part in the wider system context (eg. printed circuit board simulation). Behavioural simulation can reduce design time by allowing design problems to be detected early on, avoiding the need to rework designs at gate level. Behavioural simulation also permits design optimization by exploring alternative architectures, resulting in better designs.

ToolsVHDL descriptions of hardware design and test benches are portable between design tools, and portable between design centres and project partners. You can safely invest in VHDL modelling effort and training, knowing that you will not be tied in to a single tool vendor, but will be free to preserve your investment across tools and platforms. Also, the design automation tool vendors are themselves making a large investment in VHDL, ensuring a continuing supply of state-of-the-art VHDL tools.

TechnologyVHDL permits technology independent design through support for top down design and logic synthesis. To move a design to a new technology you need not start from scratch or reverse-engineer a specification - instead you go back up the design tree to a behavioural VHDL description, then implement that in the new technology knowing that the correct functionality will be preserved.

Benefits Executable specification Validate spec in system context (Subcontract) Functionality separated from implementation Simulate early and fast (Manage complexity) Explore design alternatives Get feedback (Produce better designs) Automatic synthesis and test generation (ATPG for ASICs) Increase productivity (Shorten time-to-market) Technology and tool independence (though FPGA features may be unexploited) Portable design data (Protect investment)

BASIC LANGUAGE ELEMENTS

Comments

Comments are preceded by two consecutive hyphens ( -- ) and are terminated at the end of the line.

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Example:

-- This is a comment

Identifiers

VHDL identifier syntax:

A sequence of one or more upper case letters, lower case letters, digits, and the underscore.

Upper and lower case letters are treated the same, i.e. case insensitive. The first character must be a letter. The last character cannot be the underscore. Two underscores cannot be together.

Data ObjectsThere are three kinds of data objects: signals, variables, and constants. The data object SIGNAL represents logic signals on a wire in the circuit. A signal does not have memory, thus, if the source of the signal is removed, the signal will not have a value.

A VARIABLE object remembers its content and is used for computations in a behavioral model.

A CONSTANT object must be initialized with a value when declared and this value cannot be changed.

Example:

SIGNAL x: BIT;

VARIABLE y: INTEGER;

CONSTANT one: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";

Data Types

BIT and BIT_VECTOR

The BIT and BIT_VECTOR types are predefined in VHDL. Objects of these types can have the values ‘0’ or ‘1’.

The BIT_VECTOR type is simply a vector of type BIT.

Example:

SIGNAL x: BIT;

SIGNAL y: BIT_VECTOR(7 DOWNTO 0);

x <= '1';

y <= "0010";

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STD_LOGIC and STD_LOGIC_VECTOR

The STD_LOGIC and STD_LOGIC_VECTOR types provide more values than the BIT type for modelinga real circuit more accurately. Objects of these types can have the following values:

‘0’ −normal 0.

‘1’ −normal 1.

‘Z’ −high impedance.

‘−’ −don’t care.

‘L’ −weak 0.

‘H’ −weak 1.

‘U’ −uninitialized.

‘X’ −unknown.

‘W’ −weak unknown.

The STD_LOGIC and STD_LOGIC_VECTOR types are not predefined and so the two library statements just be included in order to use these types:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

If objects of type STD_LOGIC_VECTOR are to be used as binary numbers in arithmetic manipulations, then either one of the following two USE statements must also be included:

USE ieee.std_logic_signed.ALL; for signed number arithmetic or

USE ieee.std_logic_unsigned.all; for unsigned number arithmetic.

Example:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

SIGNAL x: STD_LOGIC;

SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0);

x <= 'Z';

y <= "001-";

INTEGER

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The predefined INTEGER type defines binary number objects for use with arithmetic operators. By default, an INTEGER signal uses 32 bits to represent a signed number. Integers using fewer bits can also be declared with the RANGE keyword.

Example:

SIGNAL x: INTEGER;

SIGNAL y: INTEGER RANGE –64 to 64;

Enumeration TYPE

An enumeration type allows the user to specify the values that the data object can have.

Syntax:

TYPE identifier IS (value1, value2, … );

Example:

TYPE state_type IS (S1, S2, S3);

SIGNAL state: state_type;

state<= S1;

ARRAY

The ARRAY type groups single data objects of the same type together into a one or multi- dimensional array.

Syntax:

TYPE identifier IS ARRAY (range) OF type;

Example:

TYPE byte IS ARRAY(7 DOWNTO 0) OF BIT;

TYPE memory_type IS ARRAY(1 TO 128) OF byte;

SIGNAL memory: memory_type;

memory(3) <= "00101101";

SUBTYPE

A SUBTYPE is a subset of a type, that is, a type with a range constraint.

Syntax:

SUBTYPE identifier IS type RANGE range;

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Example:

SUBTYPE integer4 IS INTEGER RANGE –8 TO 7;

SUBTYPE cell IS STD_LOGIC_VECTOR(3 DOWNTO 0);

TYPE memArray IS ARRAY(0 TO 15) OF cell;

Describing a design

         In VHDL an entity is used to describe a hardware module.

An entity can be described using,

         1. Entity declaration.

         2. Architecture.

         3. Configuration

         4. Package declaration.

         5. Package body.  

Entity declaration:

    It defines the names, input output signals and modes of a hardware module.

Syntax:    entity entity_name is        Port declaration;    end entity_name;  

       An entity declaration should starts with ‘entity’ and ends with ‘end’ keywords.

        Ports are interfaces through which an entity can communicate with its environment. Each port must have a name, direction and a type. An entity may have no port declaration also. The direction will be input, output or inout.

               

In Port can be read

Out Port can be written

Inout Port can be read and written

Buffer Port can be read and written, it

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can have only one source.

Architecture:

   It describes the internal description of design or it tells what is there inside design. Each entity has atleast one architecture and an entity can have many architecture. Architecture can be described using structural, dataflow, behavioral or mixed style. Architecture can be used to describe a design at different levels of abstraction like gate level, register transfer level (RTL) or behavior level.  

Syntax:

           architecture architecture_name of entity_name         architecture_declarative_part;     begin        Statements;     end architecture_name; 

      Here we should specify the entity name for which we are writing the architecture body. The architecture statements should be inside the begin and end keyword. Architecture declarative part may contain variables, constants, or component declaration. 

Package declaration:

  Package declaration is used to declare components, types, constants, functions and so on.

Syntax:   

          package package_name is       Declarations;    end package_name;

Package body:

   A package body is used to declare the definitions and procedures that are declared in corresponding package. Values can be assigned to constants declared in package in package body. 

Syntax:

    package body package_name is        Function_procedure definitions;    end package_name;    

  

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STYLES OF MODELLING

1.      Dataflow modeling.

2.      Behavioralmodeling.

3.      Structural modeling. 

Structure of an entity:

        

Dataflow modeling:

    In this style of modeling, the internal working of an entity can be implemented using concurrent signal assignment.

Let’s take half adder example which is having one XOR gate and a AND gate.

 

Library IEEE;use IEEE.STD_LOGIC_1164.all; entityha_en is  port (A,B:inbit;S,C:outbit);endha_en; 

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architecture behavioralofha_enisbegin                S<=A xor B; C<=A and B; end behavioral;

 Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic type, called STD_ULOGIC. use is a keyword, which imports all the declarations from this package. The architecture body consists of concurrent signal assignments, which describes the functionality of the design. Whenever there is a change in RHS, the expression is evaluated and the value is assigned to LHS.  

Behavioralmodeling:

    In this style of modeling, the internal working of an entity can be implemented using set of statements.

      It contains:

   Process statements    Sequential statements    Signal assignment statements    Wait statements

Process statement is the primary mechanism used to model the behavior of an entity. It contains sequential statements, variable assignment (:=) statements or signal assignment (<=) statements etc. It may or may not contain sensitivity list. If there is an event occurs on any of the signals in the sensitivity list, the statements within the process is executed.

Inside the process the execution of statements will be sequential and if one entity is having two processes the execution of these processes will be concurrent. At the end it waits for another event to occur. 

 library IEEE;use IEEE.STD_LOGIC_1164.all; entityha_beha_enisport( A :inBIT; B :inBIT; S :outBIT;  C :outBIT );endha_beha_en;  

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architectureha_beha_arofha_beha_enisbeginprocess_beh:process(A,B)begin S<= A xor B; C<=A and B;  endprocessprocess_beh; endha_beha_ar;

 Here whenever there is a change in the value of a or b the process statements are executed.  

Structural modeling:

   The implementation of an entity is done through set of interconnected components.

It contains:

 Signal declaration.  Component instances  Port maps.  Wait statements.

 Component declaration:

   Syntax:

componentcomponent_name [is]List_of_interface ports;endcomponentcomponent_name;  

Before instantiating the component it should be declared using component declaration as shown above. Component declaration declares the name of the entity and interface of a component.

   Let’s try to understand this by taking the example of full adder using 2 half adder and 1 OR gate.

 

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library IEEE;

use IEEE.STD_LOGIC_1164.all;

entityfa_enisport(A,B,Cin:inbit; SUM, CARRY:outbit);endfa_en;

architecturefa_aroffa_enis

componentha_enport(A,B:inbit;S,C:outbit);

endcomponent;

signal C1,C2,S1:bit;

begin

HA1:ha_en portmap(A,B,S1,C1); HA2:ha_enportmap(S1,Cin,SUM,C2); CARRY<= C1 or C2;

endfa_ar;

The program we have written for half adder in dataflow modeling is instantiated as shown above. ha_en is the name of the entity in dataflow modeling. C1, C2, S1 are the signals used for internal connections of the component which are declared using the keyword signal. Port map is used to connect different components as well as connect components to ports of the entity.

Component instantiation is done as follows.

    Component_label: component_name port map (signal_list); 

Signal_list is the architecture signals which we are connecting to component ports. This can be done in different ways. What we declared above is positional binding.

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CODING

ALU

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

USE WORK.ctrlPACK.ALL;

entity ALU is

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Port ( a,b : in t_data;

s : in t_alu;

y,z : out t_data);

end ALU;

architectureBehavioral of ALU is

functionbtoi(a: in std_logic_vector)

return integer is

variableu,v: integer;

begin

u:= 0;

v:= 1;

for i in 0 to 15 loop

if(a(i)='1') then

u:= u+v;

else

NULL;

endif;v:= v*2;

end loop;

return u;

end function btoi;

functionitob(a: in integer)

returnstd_logic_vector is

variable w: std_logic_vector(31 downto 0);

variable v: integer;

begin

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v:= a;

for i in 0 to 31 loop

if( v rem 2 =1) then

w(i):= '1';

else

w(i):= '0';

end if;

v:= v/2;

end loop;

return w;

end function itob;

begin

process(a,b,s)

variable m,n: integer;

variablep,q,r: std_logic_vector(31 downto 0);

begin

case s is

when pass => -- Pass a no.

y<=a after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

whenandop => -- AND two nos.

y<=a and b after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

whenorop => -- OR two nos.

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y<=a or b after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

whenxorop => -- XOR two nos.

y<=a xor b after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

whennotop => -- Invert a no.

y<=not a after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

when add => -- Addition without Carry

y<=a+b after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

whenadc => -- Addition with Carry

p(15 downto 0):= a;

p(31 downto 16):= "0000000000000000";

q(15 downto 0):= b;

q(31 downto 16):= "0000000000000000";

r:= p+q;

y<= r(15 downto 0) after 1 ns;

z<= r(31 downto 16)after 1 ns;

when sub => -- Subtraction withour Borrow

y<=a-b after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

whenmul => -- Multiply two nos.

m:= btoi(a)*btoi(b);

r:= itob(m);

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y<= r(15 downto 0) after 1 ns; -- (LSB of Product)

z<= r(31 downto 16) after 1 ns; -- (MSB of Product)

wheninc => -- Increment a no.

y<=a+"0000000000000001" after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

whendec => -- Decrement a no.

y<=a-"0000000000000001" after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

when zero => -- Pass zero

y<="0000000000000000" after 1 ns;

z<="ZZZZZZZZZZZZZZZZ" after 1 ns;

end case;

end process;

endBehavioral;

BIREGISTER

library IEEE; --"BIREGISTER Coding"

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

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--use UNISIM.VComponents.all;

entity BIREGISTER is

Port ( a : in std_logic_vector(15 downto 0);

clk : in std_logic;

y : out std_logic_vector(15 downto 0));

end BIREGISTER;

architectureBehavioral of BIREGISTER is

begin

process(a,clk)

begin

if(clk='1' and clk'event) then

y<= a after 1 ns; -- Input data appears at Output

else

NULL;

end if;

end process;

endBehavioral;

TRIREGISTER

--"TRIREGISTER Coding"

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

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-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity TRIREGISTER is

Port ( a : in std_logic_vector(15 downto 0);

clk : in std_logic;

en : in std_logic;

y : out std_logic_vector(15 downto 0));

end TRIREGISTER;

architectureBehavioral of TRIREGISTER is

signal u: std_logic_vector(15 downto 0);

begin

process

begin

wait until clk'event and clk='1'; -- Input data is stored in register

u<= a after 1 ns;

end process;

process(en,u)

begin

if en='1' then -- Data stored in register appears at output

y<= u after 1 ns;

elsif en='0' then

y<= "ZZZZZZZZZZZZZZZZ" after 1 ns;

else

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y<= "XXXXXXXXXXXXXXXX" after 1 ns;

end if;

end process;

endBehavioral;

COMPARATOR

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

usework.ctrlpack.all;

entity COMP is

Port ( a,b : in t_data;

s : in t_comp;

y : out std_logic);

end COMP;

architectureBehavioral of COMP is

begin

process(a,b,s)

begin

case s is

wheneq => -- Checking 'Eqaul to' condition

if (a=b) then

y<='1' after 1 ns;

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else

y<='0' after 1 ns;

end if;

whenneq => -- Checking 'Not equal to' condition

if (a/=b) then

y<='1' after 1 ns;

else

y<='0' after 1 ns;

end if;

whengt => -- Checking 'Greater than' condition

if (a>b) then

y<='1' after 1 ns;

else

y<='0' after 1 ns;

end if;

whenlt => -- Checking 'Less than' condition

if (a<b) then

y<='1' after 1 ns;

else

y<='0' after 1 ns;

end if;

whengte => -- Checking 'Greater than or equal to' condition

if (a>=b) then

y<='1' after 1 ns;

else

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y<='0' after 1 ns;

end if;

whenlte => -- Checking 'Less than or equal to' condition

if (a<=b) then

y<='1' after 1 ns;

else

y<='0' after 1 ns;

end if;

end case;

end process;

endBehavioral;

RAM

--"REGISTER ARRAY(RAM) Coding"

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

usework.ctrlpack.all;

entity RAM is

Port ( a : in t_data;

sel : in t_reg;

clk : in std_logic;

en : in std_logic;

y : out t_data);

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end RAM;

architectureBehavioral of RAM is

begin

process(a,sel,clk,en)

variablem,n,o,p,q,r,s,t: std_logic_vector(15 downto 0);

begin

if(clk'event and clk='1') then

casesel is -- Storing data in the chosen register

when "000"=>

m:=a;

when "001"=>

n:=a;

when "010"=>

o:=a;

when "011"=>

p:=a;

when "100"=>

q:=a;

when "101"=>

r:=a;

when "110"=>

s:=a;

when"111"=>

t:=a;

when others=>

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NULL;

end case;

end if;

if(en='1') then

casesel is -- Retrieving data from the chosen register

when "000"=>

y<=m;

when "001"=>

y<=n;

when "010"=>

y<=o;

when "011"=>

y<=p;

when "100"=>

y<=q;

when "101"=>

y<=r;

when "110"=>

y<=s;

when "111"=>

y<=t;

when others=>

NULL;

end case;

else

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y<="ZZZZZZZZZZZZZZZZ";

end if;

end process;

endBehavioral;

SHIFT REGISTER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

usework.ctrlpack.all;

entity SHIFT is

Port ( a : in t_data;

s : in t_shift;

y : out t_data);

end SHIFT;

architectureBehavioral of SHIFT is

begin

process(a,s)

begin

case s is

whenshp => -- Pass a no.

y<=a after 1 ns;

whenshl => -- Shift Left operation

y<=a(14 downto 0) & '0' after 1 ns;

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whenshr => -- Shift Right operation

y<='0' &a(15 downto 1) after 1 ns;

whenrotl => -- Rotate Left operation

y<=a(14 downto 0) & a(15) after 1 ns;

whenrotr => -- Rotate Right operation

y<=a(0) & a(15 downto 1) after 1 ns;

end case;

end process;

endBehavioral;

CONTROL UNIT

--"CONTROL UNIT Coding"

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

packagectrlpack is

subtypet_data is std_logic_vector(15 downto 0);

typet_alu is (andop, orop, notop, xorop, add, adc, sub, mul,

inc, dec, pass, zero);

typet_shift is (shl, shr, rotl, rotr, shp);

typet_comp is (eq, neq, gt, lt, gte,lte);

subtypet_reg is std_logic_vector(2 downto 0);

type state is (reset1,reset2,reset3,reset4,reset5,reset6,

execute,nop,load,store,move,load2,load3,

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load4,store2,store3,store4,move2,move3,

move4,incpc,incpc2,incpc3,incpc4,incpc5,

incpc6,loadpc,loadpc2,loadpc3,loadpc4,

bgti2,bgti3,bgti4,bgti5,bgti6,bgti7,bgti8,

bgti9,bgti10,brai2,brai3,brai4,brai5,brai6,

loadi2,loadi3,loadi4,loadi5,loadi6,inc2,

inc3,inc4);

end package ctrlpack;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

usework.ctrlpack.all;

entity CONTROL is

Port ( clk : in std_logic;

reset : in std_logic;

instrregout : in t_data;

compout : in std_logic;

ready : in std_logic;

progcntrwr : out std_logic;

progcntrrd : out std_logic;

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addrregsel : out std_logic;

flagregwr: out std_logic;

flagregrd: out std_logic;

outregwr : out std_logic;

outregrd : out std_logic;

shiftsel : out t_shift;

alusel : out t_alu;

compsel : out t_comp;

opregsel : out std_logic;

instrregsel : out std_logic;

regsel : out t_reg;

regwr : out std_logic;

regrd : out std_logic;

vma : out std_logic;

wrb : out std_logic);

end CONTROL;

architectureBehavioral of CONTROL is

signalcurrent_state,next_state : state;

begin

process(clk,reset)

begin

if (reset='1') then

current_state<= reset1 after 1 ns;

elsif (clk'event and clk='1') then

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current_state<= next_state after 1 ns;

end if;

end process;

process(current_state,instrRegout,compout,ready)

begin

progcntrwr<='0';

progcntrrd<='0';

addrregsel<='0';

flagregwr<='0';

flagregrd<='0';

outregwr<='0';

outregrd<='0';

shiftsel<=shp;

alusel<=pass;

compsel<=eq;

opregsel<='0';

instrregsel<='0';

regsel<="000";

regrd<='0';

regwr<='0';

wrb<='0';

vma<='0';

casecurrent_state is

when reset1 =>

alusel<=zero after 1 ns;

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shiftsel<=shp;

next_state<=reset2;

when reset2 =>

alusel<=zero;

shiftsel<=shp;

outregwr<='1';

next_state<=reset3;

when reset3 =>

outregrd<= '1';

next_state<=reset4;

when reset4 =>

outregrd<='1';

progcntrwr<='1';

addrregsel<='1';

next_state<=reset5;

when reset5 =>

vma<='1';

wrb<='0';

next_state<=reset6;

when reset6 =>

vma<='1';

wrb<='0';

if (ready='1') then

instrregsel<='1';

next_state<=execute;

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else

next_state<=reset6;

end if;

when execute =>

caseinstrregout(15 downto 11) is

when "00000" => --nop

next_state<=incpc;

when "00001" => --load

regsel<=instrregout(5 downto 3);

regrd<='1';

next_state<=load2;

when "00010" => --store

regsel<=instrregout(2 downto 0);

regrd<='1';

next_state<=store2;

when "00011" => --move

regsel<= instrregout(5 downto 3);

regrd<='1';

alusel<=pass;

shiftsel<=shp;

next_state<=move2;

when "00100" => --loading

progcntrrd<='1';

alusel<=inc;

shiftsel<=shp;

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next_state<=loadi2;

when "00101" => --branching

progcntrrd<='1';

alusel<=inc;

shiftsel<=shp;

next_state<=brai2;

when "00110" => --branching

regsel<=instrregout(5 downto 3);

regrd<='1';

next_state<=bgti2;

when "00111" => --inc

regsel<=instrregout(2 downto 0);

regrd<='1';

alusel<=inc;

shiftsel<=shp;

next_state<=inc2;

when others =>

next_state<=incpc;

end case;

when load2 =>

regsel<=instrregout(5 downto 3);

regrd<='1';

addrregsel<='1';

next_state<=load3;

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when load3 =>

vma<='1';

wrb<='0';

next_state<=load4;

when load4 =>

vma<='1';

wrb<='0';

regsel<=instrregout(2 downto 0);

regwr<='1';

next_state<=incpc;

when store2 =>

regsel<=instrregout(2 downto 0);

regrd<='1';

addrregsel<='1';

next_state<=store3;

when store3 =>

regsel<=instrregout(5 downto 3);

regrd<='1';

next_state<=store4;

when store4 =>

regsel<=instrregout(5 downto 3);

regrd<='1';

vma<='1';

wrb<='1';

next_state<=incpc;

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when move2 =>

regsel<=instrregout(5 downto 3);

regrd<='1';

alusel<=pass;

shiftsel<=shp;

outregwr<='1';

next_state<=move3;

when move3 =>

outregrd<= '1';

next_state<=move4;

when move4 =>

outregrd<='1';

regsel<=instrregout(2 downto 0);

regwr<='1';

next_state<=incpc;

when loadi2 =>

progcntrrd<='1';

alusel<=inc;

shiftsel<=shp;

outregwr<='1';

next_state<=loadi3;

when loadi3 =>

outregrd<='1';

next_state<=loadi4;

when loadi4 =>

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outregrd<='1';

progcntrwr<='1';

addrregsel<='1';

next_state<=loadi5;

when loadi5 =>

vma<='1';

wrb<='0';

next_state<=loadi6;

when loadi6 =>

vma<='1';

wrb<='0';

if (ready='1') then

regsel<=instrregout(2 downto 0);

regwr<='1';

next_state<=incpc;

else

next_state<=loadi6;

end if;

when brai2 =>

progcntrrd<='1';

alusel<=inc;

shiftsel<=shp;

outregwr<='1';

next_state<=brai3;

when brai3 =>

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outregrd<='1';

next_state<=brai4;

when brai4 =>

outregrd<='1';

progcntrwr<='1';

addrregsel<='1';

next_state<=brai5;

when brai5 =>

vma<='1';

wrb<='0';

next_state<=brai6;

when brai6 =>

vma<='1';

wrb<='0';

if (ready='1') then

progcntrwr<='1';

next_state<=loadpc;

else

next_state<=brai6;

end if;

when bgti2 =>

regsel<=instrregout(5 downto 3);

regrd<='1';

opregsel<='1';

next_state<=bgti3;

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when bgti3 =>

opregsel<='1';

regsel<=instrregout(2 downto 0);

regrd<='1';

compsel<=gt;

next_state<=bgti4;

when bgti4 =>

opregsel<='1' after 1 ns;

regsel<=instrregout(2 downto 0);

regrd<='1';

compsel<=gt;

if (compout ='1') then

next_state<=bgti5;

else

next_state<=incpc;

end if;

when bgti5 =>

progcntrrd<='1';

alusel<=inc;

shiftsel<=shp;

next_state<=bgti6;

when bgti6 =>

progcntrrd<='1';

alusel<=inc;

shiftsel<=shp;

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outregwr<='1';

next_state<=bgti7;

when bgti7 =>

outregrd<='1';

next_state<=bgti8;

when bgti8 =>

outregrd<='1';

progcntrwr<='1';

addrregsel<='1';

next_state<=bgti9;

when bgti9=>

vma<='1';

wrb<='0';

if (ready='1') then

progcntrwr<='1';

next_state<=loadpc;

else

next_state<=bgti10;

end if;

when inc2 =>

regsel<=instrregout(2 downto 0);

regrd<='1';

alusel<=inc;

shiftsel<=shp;

outregwr<='1';

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next_state<=inc3;

when inc3=>

outregrd<='1';

next_state<=inc4;

when inc4 =>

outregrd<='1';

regsel<=instrregout(2 downto 0);

regwr<='1';

next_state<=incpc;

whenloadpc =>

progcntrrd<='1';

next_state<=loadpc2;

when loadpc2 =>

progcntrrd<='1';

addrregsel<='1';

next_state<=loadpc3;

when loadpc3 =>

vma<='1';

wrb<='1';

next_state<=loadpc4;

when loadpc4 =>

vma<='1';

wrb<='0';

if (ready='1') then

instrregsel<='1';

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next_state<=execute;

else

next_state<=loadpc4;

end if;

whenincpc =>

progcntrrd<='1';

alusel<=inc;

shiftsel<=shp;

next_state<=incpc2;

when incpc2 =>

progcntrrd<='1';

alusel<=inc;

shiftsel<=shp;

outregwr<='1';

next_state<=incpc3;

when incpc3 =>

outregrd<='1';

next_state<=incpc4;

when incpc4 =>

outregrd<='1';

progcntrwr<='1';

addrregsel<='1';

next_state<=incpc5;

when incpc5 =>

vma<='1';

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wrb<='0';

next_state<=incpc6;

when incpc6 =>

vma<='1';

wrb<='0';

if (ready='1') then

instrregsel<='1';

next_state<=execute;

else

next_state<=incpc6;

end if;

when others =>

next_state<=incpc;

end case;

end process;

endBehavioral;

CPU

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

usework.ctrlpack.all;

entity MAIN is

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Port ( data : inoutt_data;

clk : in std_logic;

reset : in std_logic;

ready : in std_logic;

addr : out t_data;

vma : out std_logic;

wrb : out std_logic);

end MAIN;

architectureBehavioral of MAIN is

component CONTROL is

Port ( clk : in std_logic;

reset : in std_logic;

instrregout : in t_data;

compout : in std_logic;

ready : in std_logic;

progcntrwr : out std_logic;

progcntrrd : out std_logic;

addrregsel : out std_logic;

--flagregwr: out std_logic;

--flagregrd: out std_logic;

outregwr : out std_logic;

outregrd : out std_logic;

shiftsel : out t_shift;

alusel : out t_alu;

compsel : out t_comp;

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opregsel : out std_logic;

instrregsel : out std_logic;

regsel : out t_reg;

regwr : out std_logic;

regrd : out std_logic;

vma : out std_logic;

wrb : out std_logic);

end component;

component ALU is

Port ( a,b : in t_data;

s : in t_alu;

y,z : out t_data);

end component;

component SHIFT is

Port ( a : in t_data;

s : in t_shift;

y : out t_data);

end component;

component COMP is

Port ( a,b : in t_data;

s : in t_comp;

y : out std_logic);

endCOMPonent;

component BIREGISTER is

Port ( a : in std_logic_vector(15 downto 0);

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clk : in std_logic;

y : out std_logic_vector(15 downto 0));

end component;

component TRIREGISTER is

Port ( a : in std_logic_vector(15 downto 0);

clk : in std_logic;

en : in std_logic;

y : out std_logic_vector(15 downto 0));

end component;

component RAM is

Port ( a : in t_data;

sel : in t_reg;

clk : in std_logic;

en : in std_logic;

y : out t_data);

end component;

signalopregout,aluout,shiftout,instrregout: t_data;

signalregsel : t_reg;

signalregRd,regwr,opregsel,outregrd,outregwr,addrregsel,

instrregsel,progcntrrd,progcntrwr,compout: std_logic;

signalalusel: t_alu;

signalshiftsel : t_shift;

signalcompsel : t_comp;

begin

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con1: control

port map(clk,reset,instrregout,compout,ready,

progcntrwr,progcntrrd,addrRegsel,

outRegWr,outRegRd,shiftsel,alusel,compsel,opRegsel,

instrregsel,regsel,regwr,regrd,vma, wrb);

shift1 : shift

port map(aluout,shiftsel,shiftout);

ram1: ram

port map(data,regsel,regwr,regrd,data);

opreg: biregister

port map(data,opregsel,opregout);

comp1 : comp

port map (opregout,data,compsel,compout);

outreg: triregister

port map(shiftout,outregwr,outregrd,data);

addrreg :biregister

port map(data,addrregsel,addr);

progcntr: triregister

port map(data, progcntrwr,progcntrrd,data);

instr1: biregister

port map(data,instrregsel,instrregout);

alu1: alu

port map(data,opregout,alusel,aluout);

endBehavioral;

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WHY WE USE VHDL ?

Because of its difference with Verilog.The two languages approach the task from different directions; VHDL, intended as a specification language, is very exact in its nature and hence very verbose. Verilog, intended as a simulation language, it much closer to C in style, in that it is terse and elegant to write but requires much more care to avoid nasty bugs. VHDL doesn't let you get away with much; Verilog assumes that whatever you wrote was exactly what you intended to write. If you get a VHDL architecture to compile, it's probably going to approximate to the function you wanted. For Verilog, successful compilation merely indicates that the syntax rules were met, nothing more. VHDL has some features that make it good for system-level modeling, whereas Verilog is much better than VHDL at gate-level simulation.

As VHDL can be used for the analog part of a design.

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There is a VHDL Analogue and Mixed Signal language (VHDL-AMS), based on VHDL 93, which allows modeling of both analogue and digital in the same language. However the idea of analogue synthesis is still in its early days, so currently you wouldn't normally be able to go on and synthesize an analogue model written in VHDL-AMS.

VHDL is a synthesizable languageBecause large parts of the language make no sense in a hardware context, synthesizable VHDL is a relatively small subset of VHDL. One must stick to this subset, and understand exactly how the synthesis tool you use interprets that code. For FPGA in particular one must also develop a good understanding of the structure of your chip, and know how your code must reflect the most efficient use of that structure.

Fourversions of VHDL There are four versions of vhdl. The original release of the VHDL language occured in 1987 with the adoption of the Language Reference Manual as an IEEE standard. In 1993, the IEEE-1076 standard was modified and ratified and became known as VHDL'93. This is now widely supported. In 2000, the VHDL 1076 2000 Edition appeared - this fixed shared variables by introducing the idea of protected types. Finally, VHDL 1076-2002 appeared. This includes protected mode types, but also changes ports of mode buffer to make them more usable, along with some other small changes. In practise, VHDL 1076-1993 is the current flavour of VHDL which is widely supported by tool vendors.

A VHDL design can be moved to any tool or technologyVHDL was designed to be and is a technology independent design language. However, there is less of a compliance issue between different simulators than there is for synthesis tools. Generally speaking, moving VHDL code from one simulator to another involves one or two minor changes to the VHDL. Two different synthesis tools may have broad agreement of what constitutes sythesisable code, but may interpret that code in different ways. VHDL is guaranteed to be more transportable between synthesis tools than it otherwise would be. In addition, because we are so aware of the differences between synthesis tools this means that we emphasise the best way of writing VHDL to get the best from your synthesis tool. For FPGA, code that uses one technology in the most efficient way is unlikely to be as efficient when sythesised to a different device family.

Measure of the productivity improvementsThere are considerable productivity gains to be had from using high-level design techniques in conjunction with synthesis technology, providing that your designs are: complex, amenable to synthesis, not dependent upon the benefits of a particular technologyObviously, complex means different things to different people, but a good rule of thumb is that complex means the implementation part of the design process is considerably more awkward than the specification phase. Let's face it, if the specification phase is significantly longer than the implementation phase, you need to put effort here, not into HLD. Of course, seeing the benefits from HLD productivity gains, the specification phase becomes more significant.VHDL is a HLD design entry language, so we would expect the use of VHDL with synthesis technology to improve productivity in the design process.

Simulates the actual hardware.

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The way to describe "physical" hardware in VHDL is to write VHDL models of those components. This is supported in VHDL through the use of instantiation.VHDL does not allow to physically simulate your hardware. One can only simulate a model of that component in a VHDL simulation. Historically, gate-level simulation using VHDL has been notoriously slow. This led to the creation of the 1076.4 working group to provide a mechanism to allow faster gate-level simulation using VHDL. Their effort became known as the VITAL standard.

VHDL provides source code libraries to re-invent common code fragments and functions.There are a few libraries available for most levels of VHDL design. The IEEE library contains very low-level type-and-function packages. The std_logic_1164 package is an industry standard, and practically every piece of VHDL you ever write will use this package; the types std_logic and std_logic_vector are the overwhelmingly dominant types for anything related to digital design. For arithmetic, numeric_std (from the same IEEE library) is a collection of functions that work on std_logic and its derivatives.

Inexpensive VHDL tools available.The main FPGA vendors including Altera and Xilinx provide simple toolsets, including a VHDL simulator. These toolsets are normally limited to small devices, and will also have a limit on the number of lines of code we can write; and of course the target technology for synthesis is fixed to a particular manufacture's chips.

Easy SynthesisSynthesis is the stage in the design flow which is concerned with translating your VHDL code into gates - and that's putting it very simply! First of all, the VHDL must be written in a particular way for the target technology that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

CONCLUSION

Stressing the important features of VHDL, the project entitled “DESIGN AND SIMULATION OF 16 BIT MICROPROCESSOR” includes the designing of 16 bit microprocessor and related topics. The project emphasized on fabrication and styles of modelling andbasic language elements.While synthesis tools cope pretty well with complex designs.

VHDL covers the complete range of applications and can be used to model(digitally) hardware in a general way. This language can be applied to model system behaviour independently from the target technology. The individual parts were designed separately and

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integrated into one system by building blocks from the individual modules and combining together in a schematic entry module. After testing the individual parts they were then combined to test functionality. Finally the FPGA kit was burnt withthe VHDL code .

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