Principle of ATM （3）

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Principle of ATMPrinciple of ATM（（ 33 ））

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11. 11. ATM Switch ArchitectureATM Switch Architecture

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11. The Basic Concept of the ATM Switches. The Basic Concept of the ATM Switches

• The basic switching node comprises a set of interfaces for input and output connections, a switching fabric and a set of software functions.

• The interface cards contain a buffer for input and output traffic. This buffer acts as a scheduler that selects which cells are to be placed upon the output media.

• The fabric is the high-speed component that moves cells from input buffer to output buffer.

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11. The Basic Concept of the ATM Switches (cont.). The Basic Concept of the ATM Switches (cont.)

• Software entities include the signalling stack. The signalling stack includes functions to handle signalling across the UNI and the NNI (for public or private internal inter-node signalling).

• Management software is also located here: ILMI(Interim Interim Local Management InterfaceLocal Management Interface ), configuration software and MIB structures.

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ATM Switching Nodes

Interfaces

Fabric

Input/output buffersscheduler, mappings

High-speed switching

Managementsoftware

Signallingsoftware

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22. . ATM Switch Fabric ArchitecturesATM Switch Fabric Architectures

The actual structure of the fabric is still the subject of intense research. There are, however, several 'classic' designs worth mentioning.

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22. . ATM Switch Fabric Architectures (cont.)ATM Switch Fabric Architectures (cont.)(1) Shared bus(1) Shared bus A shared bus architecture provides a high-speed bus with an

arbitration mechanism. All traffic shares a single bus. As such, the bus is an obvious bottleneck.

This design has been successfully used in practice, but modern switches tend not to use this design.

Arbiter

Shared bus

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22. . ATM Switch Fabric Architectures (cont.)ATM Switch Fabric Architectures (cont.)(2) Crosspoint The crosspoint is also a widely used design. Again, the theory

of crosspoints was well defined before the advent of ATM.

The architecture does not scale well (the number of crosspoints grows exponentially with the number of inputs).

We find this design in small to medium switches.

Crosspoint

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22. . ATM Switch Fabric Architectures (cont.)ATM Switch Fabric Architectures (cont.)(3) Shared memory(3) Shared memoryShared memory is well defined and widely implemented as a

fabric design. The design allows the easy segregation of different traffic classes.

As the memory grows, however, control grows in complexity and at about 65 thousand cells of storage, there is a need to move from 16-bit to 32-bit processing.

The design works well and is found in small to medium switches.

Queues

Queues

Queues

Shared memory

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22. . ATM Switch Fabric Architectures (cont.)ATM Switch Fabric Architectures (cont.)(3) Delta(3) Delta Large-scale design moves into parallel paths and internal

paths that are not shared. The generic name for these fabrics is Delta.

As a cell propagates across the fabric its destination (output port) is defined in small incremental steps.

In this configuration 'self-routing' fabrics emerge in cases where the cell finds its own way to the output port.

Delta

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33. . Buffers and BufferingBuffers and Buffering

Buffering can occur at the input, at the output and inside the fabric.

Input buffers tend to be small as the rate at which traffic arrives is entirely defined by the rate of the interface (line rate).

Output buffers need to be larger as several inputs could be simultaneously directing cells to a single output (n x 155 does not fit into 155).

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Buffers and BufferingInterfaces

Input/output buffersscheduler, mappings

InputBuffer

OutputBuffer

InputBuffer

OutputBuffer

InputBuffer

OutputBuffer

InputBuffer

OutputBuffer

FABRIC

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33. . Buffers and Buffering (cont.)Buffers and Buffering (cont.)

Output buffering may be implemented as part of the shared shared memory architecturememory architecture where several queues can be created, one for each service category.

With several queues, preference can be given to the CBR queue over the VBR queue.

In extreme cases, we can provide one queue per connectionand implement a very refined prioritisation scheme.

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55. . Blocking ProblemsBlocking ProblemsHead-of-Line Blocking (HOL)HOL blocking can occur when high-priority traffic is introduced

to a queue that already contains traffic of a lower priority. In this case the high-priority traffic has to wait.

Given that the high-priority traffic (for instance, voice traffic) may be delay-sensitive, this could be a problem.

A better solution is to use several queues with one queue per service category or one queue per connection, although this is expensive.

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66. . Blocking Problems (cont.)Blocking Problems (cont.)An output interface includes some form of scheduling process.

The scheduler preferentially takes cells from high-priority (low-delay) queues. This means that CBR can get preference over VBR/ABR/UBR etc.

QUEUE

SERVER

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55. . Blocking Problems (cont.)Blocking Problems (cont.)

(2) Blocking in the FabricBlocking can occur in the fabric (in all architectures) when a

resource that is in use internally is required by another cell.

The most obvious case would be a shared bus where everything has to wait for the current cell to transmit the bus before anything else happens.

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55. . Blocking Problems (cont.)Blocking Problems (cont.)(2) Blocking in the FabricIn a delta switch, two cells may be contending for the same

output of a switching element. All designs minimise the probability of blocking.

Element in the fabric

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55. . Blocking Problems (cont.)Blocking Problems (cont.)The easiest way to solve the problem is to increase the fabric

speed.

If the switch has 32 ports all rated at 155 Mbit/s, then a shared memory with a throughput of 5 Gbit/s (32 x 155 m) is able to handle the simultaneous arrival of a cell at each input.

The another way to solve the problem is to increase the width of fabric bus to depress the requirement of the fabric speed.

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12. 12. Building ATM NetworksBuilding ATM Networks

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1. 1. The Carrier NetworkThe Carrier Network

The hierarchy created by two levels of multiplexing (path and channel) is utilized by the carrier to create a scaleable network.

This scalability simplifies setting up connections and overall manageability.

At the core of the network we find VP crossconnectsVP crossconnects. These are high-capacity,high-performance switches connected by SONET/SDH rings with protection.

The structure of this network component changes slowly.

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The Carrier Network (PBX:private branch (telephone) exchange:专用分组交换机 )

AccessVP/VC Switching

Edge Devices

Edge Devices

EdgeDevices

UNI

UNI

Core/BackboneVP Crossconnect

UNI

UNI

UNI

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1. 1. The Carrier Network The Carrier Network （（ cont.cont. ））

Surrounding the core is a 'cloud' of access switches that perform VC switching.

Ideally, these VC switches are fully meshed. When a connection needs to be established, it is only necessary to select available channels on already established paths.

From this access cloud the UNI can be used to connect to customer premises, which may either be simple end-stations or connection points to a private network.

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2. Campus ATM Network2. Campus ATM Network

The diagram on the next page shows a campus network with an ATM backbone. An important point to note here is that the network is not end-to-end ATM.

Rather an existing LAN technology, for example Ethernet, is used to connect PCs.

Voice traffic may be carried across the ATM backbone, however it may well be more economically favourable to directly interconnect the PBXs.

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2. Campus ATM Network (cont.)

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2. Campus ATM Network (cont.)2. Campus ATM Network (cont.)

If the offices were geographically relocated, thus necessitating WAN links, a stronger business case may then exist to trunk voice over ATM.

In the diagram on the last page note that there is redundant links from each router to the ATM network.

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2. End-to-end ATM network2. End-to-end ATM network

For end workstations such as PCs to connect directly into the ATM network they must be equipped with ATM network interface cards (NICs).

For the PBX (private branch (telephone) exchange:专用分组交换机 ) to connect into the ATM network either the PBX will have an ATM interface card, or the ATM switch that the PBX is connected to must have either an E1 interface or circuit emulation interface cards installed.

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2. End-to-end ATM network (cont.)2. End-to-end ATM network (cont.)The private network can be quite complex in its own right, with

PNNI deployed across a campus or manufacturing plant.

This may be further refined closer to the desktop through low performance workgroup switches, and at the individual desktop where the workstation is equipped with an ATM NIC card.

An end-to-end ATM network would be expensive in comparison with traditional technologies such as Ethernet. However if the network has a high volume of traffic with many mission critical QoS requirements then such a network may be desirable.

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2. End to end ATM Network

UNI

Carrier Network

Enterprise Switch

Catalyst5000PBX

E1

PNNI

Campus Switch

ATMNIC

Cards

WorkgroupSwitch

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12. 12. Circuit EmulationCircuit Emulation

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1. Circuit Emulation1. Circuit EmulationThe Circuit Emulation (CE) function enables existing TDM

circuits to be mapped over ATM.

CE thus enables us to migrate an existing TDM network to ATM whilst preserving the investment in TDM equipment.

It is possible for the PBX (or similar TDM equipment) to have an ATM interface board. In this case the CE function is performed on the PBX which sends out ATM cells directly.

CE is broken into two versions:structured structured UnstructuredUnstructured.

All versions of CE use AAL1 CBR connections.

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1. Circuit Emulation

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2. 2. Unstructured Circuit Emulation Circuit Emulation

In unstructured CE, the network does not attempt to recognize the internal circuit structure. Rather it simply transmits the entire circuit across the network.

E1/T1 ‘pipe’E1/T1 ‘pipe’ : 2/1.54 Mbps in 2/1.54 Mbps out.

No recognition of circuit’s framing structure.

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2. Unstructured Circuit Emulation (cont.)2. Unstructured Circuit Emulation (cont.)

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2. 2. Unstructured Circuit Emulation (cont.) Circuit Emulation (cont.)

As can be seen from the diagram on last slide, a 376 bit (or 47-byte) chunk of the E1 source signal is taken. This 47 bytes have the AAL1 one-byte header added to make up the full 48-byte payload.

You may wish to review the chapter on AAL 1. An ATM cell header is added, making a full ATM cell. These cells are then sent on a CBR connection.

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3. 3. Structured Circuit Emulation Circuit Emulation

Structured CE recognizes timeslots within the circuit to be emulated.

An example of structured CE is given on next slide. In this example a single timeslot is extracted from the source E1 and mapped to an ATM cell.

This means that particular timeslots may be mapped to different virtual circuits and hence to different destinations.

Several timeslots from a source circuit may be mapped to one virtual circuit. This scenario is illustrated on the next slide.

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3. Structured Circuit Emulation (Example 1)

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3. 3. Structured Circuit Emulation (cont.) Circuit Emulation (cont.)

Recall that an E1 contains 32 timeslots per frame and that the first timeslot, timeslot 0timeslot 0, is used for framing. As framing is irrelevant within the ATM network this timeslot (timeslot 0) is often terminatedterminated within the first ATM switch and regeneratedregenerated at the destination ATM switch which produces an E1 output.

An AAL1 one-byte header will be included in each cell payload, thus to use the ATM bandwidth as efficiently as possible we should wait for 47 timeslots.

In this case the application is voice traffic which is extremely delay-sensitive.

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3. 3. Structured Circuit Emulation (cont.) Circuit Emulation (cont.)

Within structured CE it is possible to map several timeslots to one cell or VC. This is shown on the next slide.

The diagram opposite displays an example of structured CE where more than one timeslot is mapped to an ATM cell. In this case timeslots 1, 3 and 6 are mapped to the same cell stream.

The CSICSI bit in the even numbered AAL 1 headers is used to indicate that structured CE is being used.

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3. Structured Circuit Emulation (Example 2)

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4. AAL1 - Time Stamp Clocking4. AAL1 - Time Stamp ClockingThe Synchronous Residual Time Stamp ClockingSynchronous Residual Time Stamp Clocking (SRTS)

method of clock information transfer is used to convey information from one end of the connection to the other.

For this method to work, it is a requirement that the same derived network clock is available at both ends.

The clock received at the interface is compared to the common reference clock (i.e. Stratum 1) and the difference is transmitted as a time stamp to the other end of the connection.

The difference is then added to or subtracted from the common reference clock to regenerate the original clock frequency.

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Synchronous Residual Time Stamp ClockingSynchronous Residual Time Stamp Clocking

Incomingcells

Striptime

stamp

Time stamps

PLL

Local clock

Receive FIFO

Bit-rateclock islocked to sender’s clock

CBRoutput

Received SDUs

CSI bit in odd number cells contains the 4-bit time stamp.The mechanism relies upon a single system clock.

Adjust clock

PLL - Phase Locked LoopSDU - Service Data UnitFIFO - First In First Out

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4. AAL1 - Time Stamp Clocking (cont.)4. AAL1 - Time Stamp Clocking (cont.)The Residual Time StampResidual Time Stamp is actually a four-bit pattern

transmitted by using the CSI bit of the SAR-PDU header when the sequence count value is 1,3,5 or 7.

The whole technique is referred to as Synchronous Residual Synchronous Residual Time StampTime Stamp (SRTS).

The timestamp is the value contained in the counter being driven by the network clock.

The four low-order bits of the timestamp are called the residual part. Mathematically it can be demonstrated that four bits are sufficient to carry the synchronizing information across a global scale deployment.

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5. AAL1 - Adaptive Clock Recovery5. AAL1 - Adaptive Clock Recovery

The fill level of the buffer is then used to control the frequency of the local clock. * If the buffer starts to empty, the clock is running too fast, and a phase lock loop mechanism is used to slow the clock down until the buffer returns to its mid-point. * If the buffer starts to fill then the clock is speeded up.

As cells arrive at the switch, the sequence number is checked. If a cell is missing, a dummydummy is inserted into the buffer to maintain the timing integrity.

The effect may be a short burst of noise, but the synchronization is kept, and the call will not be lost.

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AAL1 - Adaptive Clock RecoveryAAL1 - Adaptive Clock Recovery

Constant bit-rate output

Timing Point

- ve+ve

Dummy SDU

Received SDUs

If FIFO empties fasterthan it fills:decrease clock rate

If FIFO fills faster than it empties:increase clock rate

Local bit-rate clock

If FIFO empties too fastinject dummy SDU toreturn to the timing point

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6. Adaptive Vs SRTS

The SRTS method is appropriate for high-speed traffic, for example, E1 or DS (T1), where it takes a relatively short time to assemble 8 cells' worth of traffic.

For slow-rate traffic however, the delay caused by waiting for 47 x 8 octets (8 cells) may be unacceptable. For these slower-rate traffic sources the adaptive scheme is more suitable, as a cell can be sent as soon as it is full.

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12. Classical IP over ATM12. Classical IP over ATM

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1. Why Use IP over ATM?Why Use IP over ATM?Why IP?

IP is the dominant global data communications standard.Why ATM?

ATM natively supports a specific Quality of Service. ATM is defined and available at higher speeds than competing technologies. ATM is currently the enabling technology for the Internet.

IP over ATM is an established and proven combination. The question is to find the best method of running IP over ATM.

IP over ATM enables the use of low cost equipment which provides very high speed forwarding

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2. Running IP over ATM - the IssuesRunning IP over ATM - the Issues

• IP is a network layer protocol, that is, it can’t be run ‘on the wire’. It has to be run ‘over’ something, in this case, ATM. In the LAN, IP is usually run over Ethernet.

• IP is connectionless, ATM is connection-orientated. Accordingly, ATM uses signalling protocols to set up connections. Being connectionless, IP has no need for signalling.

• Both IP and ATM have routing protocols, and they are are incompatible.

• IP and ATM use different addressing schemes.

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3. QoS ConsiderationsQoS Considerations

• ATM service categories - CBR, rt-VBR, nrt-VBR, ABR, UBR, GFR

• How do we map from IP?– IP is a best effort protocol– ToS field in IP header unused

• Traffic coming off LAN? No method within Ethernet to define QoS

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4. Standards Bodies（ 1 ） IP - Internet Engineering Task Force (IETF)

(www.ietf.org)（ 2 ） ATM - ATM Forum

• IETF responsible forIETF responsible for:– Encapsulation– Classical IP– Multicast Address Resolution Server (MARS)– Multi protocol Label Switching (MPLS)

• ATM Forum responsible forATM Forum responsible for:– LAN Emulation (LANE)– Multiprotocol over ATM (MPOA)

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5. Classical IP over ATM (CLIP)Classical IP over ATM (CLIP)

• CLIP was the earliest model proposed for running IP over ATM (1993)

• CLIP is a combination of IETF RFC 1577, Classical IP and ARP over ATM and RFC 1483, Multi protocol Encapsulation over AAL5

• CLIP superimposes an IP network on top of ATM such that IP routing architecture remains unchanged

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6. Classical ModelClassical Model

IP is ignorant of the underlying network structure

As IP is a network layer protocol, is necessary to bind IP destination addresses to destination hardware addresses for transmission

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6. Classical Model Classical Model （（ cont.cont. ））

CLIP and EthernetCLIP operates in much the same way as IP over EthernetIP over Ethernet. In

the case of CLIP,it is necessary to map destination IP addresses to destination ATM addresses,or, in a PVC environment, to map IP addresses to VPI/VCI values.

In an Ethernet network we use ARP to accomplish this protocol to hardware address mapping.

In CLIP we use a modified version of ARP, called ATMARPATMARP, to accomplish address mapping.

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6. Classical Model (cont.)Classical Model (cont.)

Why Use The Classical ModelWhy Use The Classical Model?There are several reasons why the classical model was

followed in deploying IP over ATM and hence in the development of CLIP:

• Administrators of IP subnets tended to follow the same models as they had traditionally deployed.

• Policy administration practices strongly rely on the security and filtering capabilities of IP firewalls. Thus, it is logical to keep the existing IP structure and superimpose it on ATM.

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6. ATM Address Resolution Protocol (ATMARP)ATM Address Resolution Protocol (ATMARP) ATMARP differs from standard ARP in that the fields within

the ATMARP packet are larger, in order to accommodate the larger ATM addresses.

A major difference between ATM and Ethernet is that Ethernet has a broadcast capability, whereas ATM does not. In order to use ATMARP, we make use of an ATMARP server which all hosts can connect to.

ATMARP messages are then sent directly to the ATMARP server, which maintains a table mapping IP addresses to ATM addresses, and processes all ATMARP requests.

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7. ATMARP Packet Format7. ATMARP Packet Format

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7. ATMARP Packet Format (cont.)7. ATMARP Packet Format (cont.)

In this ATMARP packet, the hardware type and protocol type fields specify ATM and IP respectively. The operation field can have five values, specifying the type of ATMARP packet. These five types can be:

ATMARP requestATMARP request ATMARP replyATMARP reply Inverse ATMARP requestInverse ATMARP request

Inverse ATMARP replyInverse ATMARP reply ATMARP negative acknowledgementATMARP negative acknowledgement

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8. CLIP OperationCLIP OperationEach host may have a preconfigured PVC to communicate

with the server, or alternately they may have the server’s ATM address stored on disk, allowing them to signal an SVC to the server.

In this SVC case the administrator has to manually type in the server’s address.

The ATMARP server automatically maintains a table of IP addresses mapped to ATM addresses.

To achieve this, the ATMARP server is configured so that it sends an Inverse ATMARP to any host that opens an ATM connection to the ATMARP server.

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8. CLIP Operation (cont.)CLIP Operation (cont.)A host must respond to this Inverse ATMARP request. This

has the effect of registering both the host’s IP and ATM address with the ATMARP server.

The ARP cache in the ATMARP server is timed out to remove state entries.

Every entry in the ATMARP server’s IP to ATM address table is valid for 20 minutes.

After this 20 minutes the ATMARP server checks to see whether or not the host still has an ATM connection open to the ATMARP server.

If the host has no ATM connection open, then the server deletes the table entry.

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8. CLIP Operation (cont.)8. CLIP Operation (cont.) ATMARP Server

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8. CLIP Operation (cont.)CLIP Operation (cont.)If, on the other hand, the host still has an ATM connection

open to the server,the server sends another Inverse ATMARP request to the host.

If the host then verifies its addresses with an Inverse ATMARP reply, the server resets the timer and waits another 20 minutes.

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9. CLIP Operation - SVCsCLIP Operation - SVCsConsider the case of an ATM network where signalling is

deployed, that is, where SVCs can be set up.

Computer A wants to communicate with computer B. We will assume initially that no ATM connection exists between A and B.

Computer A begins with computer B’s IP address which must be mapped to a corresponding ATM address. This mapping can be achieved by using the ATMARP server.

Computer A forms an ATMARP packet, requesting the ATM address corresponding to B’s IP address, and sends it to the server. The server responds with B’s ATM address.

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9. CLIP Operation – SVCs (cont.)CLIP Operation – SVCs (cont.)

Computer A may now use ATM signalling to set up a direct connection to computer B.

If a situation arises where the ATMARP server did not have B’s address, is sends a negative acknowledgement.

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9. CLIP Operation – SVCs (cont.)

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10. CLIP Operation - PVCsCLIP Operation - PVCsRecall that PVCs are set up manually, that is, the hosts have

no input into PVC set-up. Because of this the host has no idea of either the IP address

or the ATM address of the end-point of the connection. (It should be noted that there may be no need to have ATM addresses configured in a PVC-only environment.)

A host sends an Inverse ARP request along all open connections (PVCs). The receiver at the other end replies to this Inverse ATMARP request with an Inverse ATMARP reply.

Both the request and reply contain both the sender’s IP address and ATM address.

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10. CLIP Operation – PVCs (cont.)

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11. Logical IP Subnet (LIS)Logical IP Subnet (LIS)

• The term logical IP subnetlogical IP subnet (LIS) is used to refer to an IP subnet deployed over an ATM network as part of CLIP.

• Each separate administrative authority configures its own hosts and routers within a LIS.

• Each LIS operates and communicates independently of other LISs on the same ATM network.

• An ATMARP server is used as a mechanism within a LIS for hosts to resolve destination IP addresses to destination ATM addresses.

• An ATMARP server can only provide its services within the LIS. To communicate with hosts outside the LIS an IP router must be used.

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11. Logical IP Subnets (LISs)11. Logical IP Subnets (LISs)

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11. Logical IP Subnet (LIS) (cont.)Logical IP Subnet (LIS) (cont.)

• The IP router must have an ATM interface and be connected to two or more LISs.

• Using CLIP, hosts wishing to communicate between LISs must use the services of a router.

• Thus, we see that the classical routing modelclassical routing model is preserved, as traffic wishing to go from one subnet to another has to go through a router.